2 * SuperH Timer Support - TMU
4 * Copyright (C) 2009 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/clk.h>
17 #include <linux/clockchips.h>
18 #include <linux/clocksource.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
25 #include <linux/irq.h>
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_domain.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/sh_timer.h>
31 #include <linux/slab.h>
32 #include <linux/spinlock.h>
41 struct sh_tmu_channel {
42 struct sh_tmu_device *tmu;
49 unsigned long periodic;
50 struct clock_event_device ced;
51 struct clocksource cs;
53 unsigned int enable_count;
56 struct sh_tmu_device {
57 struct platform_device *pdev;
59 void __iomem *mapbase;
62 enum sh_tmu_model model;
64 raw_spinlock_t lock; /* Protect the shared start/stop register */
66 struct sh_tmu_channel *channels;
67 unsigned int num_channels;
73 #define TSTR -1 /* shared register */
74 #define TCOR 0 /* channel register */
75 #define TCNT 1 /* channel register */
76 #define TCR 2 /* channel register */
78 #define TCR_UNF (1 << 8)
79 #define TCR_UNIE (1 << 5)
80 #define TCR_TPSC_CLK4 (0 << 0)
81 #define TCR_TPSC_CLK16 (1 << 0)
82 #define TCR_TPSC_CLK64 (2 << 0)
83 #define TCR_TPSC_CLK256 (3 << 0)
84 #define TCR_TPSC_CLK1024 (4 << 0)
85 #define TCR_TPSC_MASK (7 << 0)
87 static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr)
92 switch (ch->tmu->model) {
94 return ioread8(ch->tmu->mapbase + 2);
96 return ioread8(ch->tmu->mapbase + 4);
103 return ioread16(ch->base + offs);
105 return ioread32(ch->base + offs);
108 static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr,
113 if (reg_nr == TSTR) {
114 switch (ch->tmu->model) {
116 return iowrite8(value, ch->tmu->mapbase + 2);
118 return iowrite8(value, ch->tmu->mapbase + 4);
125 iowrite16(value, ch->base + offs);
127 iowrite32(value, ch->base + offs);
130 static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start)
132 unsigned long flags, value;
134 /* start stop register shared by multiple timer channels */
135 raw_spin_lock_irqsave(&ch->tmu->lock, flags);
136 value = sh_tmu_read(ch, TSTR);
139 value |= 1 << ch->index;
141 value &= ~(1 << ch->index);
143 sh_tmu_write(ch, TSTR, value);
144 raw_spin_unlock_irqrestore(&ch->tmu->lock, flags);
147 static int __sh_tmu_enable(struct sh_tmu_channel *ch)
152 ret = clk_enable(ch->tmu->clk);
154 dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n",
159 /* make sure channel is disabled */
160 sh_tmu_start_stop_ch(ch, 0);
162 /* maximum timeout */
163 sh_tmu_write(ch, TCOR, 0xffffffff);
164 sh_tmu_write(ch, TCNT, 0xffffffff);
166 /* configure channel to parent clock / 4, irq off */
167 ch->rate = clk_get_rate(ch->tmu->clk) / 4;
168 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
171 sh_tmu_start_stop_ch(ch, 1);
176 static int sh_tmu_enable(struct sh_tmu_channel *ch)
178 if (ch->enable_count++ > 0)
181 pm_runtime_get_sync(&ch->tmu->pdev->dev);
182 dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
184 return __sh_tmu_enable(ch);
187 static void __sh_tmu_disable(struct sh_tmu_channel *ch)
189 /* disable channel */
190 sh_tmu_start_stop_ch(ch, 0);
192 /* disable interrupts in TMU block */
193 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
196 clk_disable(ch->tmu->clk);
199 static void sh_tmu_disable(struct sh_tmu_channel *ch)
201 if (WARN_ON(ch->enable_count == 0))
204 if (--ch->enable_count > 0)
207 __sh_tmu_disable(ch);
209 dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
210 pm_runtime_put(&ch->tmu->pdev->dev);
213 static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
217 sh_tmu_start_stop_ch(ch, 0);
219 /* acknowledge interrupt */
220 sh_tmu_read(ch, TCR);
222 /* enable interrupt */
223 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
225 /* reload delta value in case of periodic timer */
227 sh_tmu_write(ch, TCOR, delta);
229 sh_tmu_write(ch, TCOR, 0xffffffff);
231 sh_tmu_write(ch, TCNT, delta);
234 sh_tmu_start_stop_ch(ch, 1);
237 static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
239 struct sh_tmu_channel *ch = dev_id;
241 /* disable or acknowledge interrupt */
242 if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT)
243 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
245 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
247 /* notify clockevent layer */
248 ch->ced.event_handler(&ch->ced);
252 static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
254 return container_of(cs, struct sh_tmu_channel, cs);
257 static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
259 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
261 return sh_tmu_read(ch, TCNT) ^ 0xffffffff;
264 static int sh_tmu_clocksource_enable(struct clocksource *cs)
266 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
269 if (WARN_ON(ch->cs_enabled))
272 ret = sh_tmu_enable(ch);
274 __clocksource_updatefreq_hz(cs, ch->rate);
275 ch->cs_enabled = true;
281 static void sh_tmu_clocksource_disable(struct clocksource *cs)
283 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
285 if (WARN_ON(!ch->cs_enabled))
289 ch->cs_enabled = false;
292 static void sh_tmu_clocksource_suspend(struct clocksource *cs)
294 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
299 if (--ch->enable_count == 0) {
300 __sh_tmu_disable(ch);
301 pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev);
305 static void sh_tmu_clocksource_resume(struct clocksource *cs)
307 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
312 if (ch->enable_count++ == 0) {
313 pm_genpd_syscore_poweron(&ch->tmu->pdev->dev);
318 static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch,
321 struct clocksource *cs = &ch->cs;
325 cs->read = sh_tmu_clocksource_read;
326 cs->enable = sh_tmu_clocksource_enable;
327 cs->disable = sh_tmu_clocksource_disable;
328 cs->suspend = sh_tmu_clocksource_suspend;
329 cs->resume = sh_tmu_clocksource_resume;
330 cs->mask = CLOCKSOURCE_MASK(32);
331 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
333 dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n",
336 /* Register with dummy 1 Hz value, gets updated in ->enable() */
337 clocksource_register_hz(cs, 1);
341 static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced)
343 return container_of(ced, struct sh_tmu_channel, ced);
346 static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic)
348 struct clock_event_device *ced = &ch->ced;
352 clockevents_config(ced, ch->rate);
355 ch->periodic = (ch->rate + HZ/2) / HZ;
356 sh_tmu_set_next(ch, ch->periodic, 1);
360 static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
361 struct clock_event_device *ced)
363 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
366 /* deal with old setting first */
368 case CLOCK_EVT_MODE_PERIODIC:
369 case CLOCK_EVT_MODE_ONESHOT:
378 case CLOCK_EVT_MODE_PERIODIC:
379 dev_info(&ch->tmu->pdev->dev,
380 "ch%u: used for periodic clock events\n", ch->index);
381 sh_tmu_clock_event_start(ch, 1);
383 case CLOCK_EVT_MODE_ONESHOT:
384 dev_info(&ch->tmu->pdev->dev,
385 "ch%u: used for oneshot clock events\n", ch->index);
386 sh_tmu_clock_event_start(ch, 0);
388 case CLOCK_EVT_MODE_UNUSED:
392 case CLOCK_EVT_MODE_SHUTDOWN:
398 static int sh_tmu_clock_event_next(unsigned long delta,
399 struct clock_event_device *ced)
401 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
403 BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
405 /* program new delta value */
406 sh_tmu_set_next(ch, delta, 0);
410 static void sh_tmu_clock_event_suspend(struct clock_event_device *ced)
412 pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
415 static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
417 pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
420 static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
423 struct clock_event_device *ced = &ch->ced;
427 ced->features = CLOCK_EVT_FEAT_PERIODIC;
428 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
430 ced->cpumask = cpumask_of(0);
431 ced->set_next_event = sh_tmu_clock_event_next;
432 ced->set_mode = sh_tmu_clock_event_mode;
433 ced->suspend = sh_tmu_clock_event_suspend;
434 ced->resume = sh_tmu_clock_event_resume;
436 dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n",
439 clockevents_config_and_register(ced, 1, 0x300, 0xffffffff);
441 ret = request_irq(ch->irq, sh_tmu_interrupt,
442 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
443 dev_name(&ch->tmu->pdev->dev), ch);
445 dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n",
451 static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name,
452 bool clockevent, bool clocksource)
455 ch->tmu->has_clockevent = true;
456 sh_tmu_register_clockevent(ch, name);
457 } else if (clocksource) {
458 ch->tmu->has_clocksource = true;
459 sh_tmu_register_clocksource(ch, name);
465 static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,
466 bool clockevent, bool clocksource,
467 struct sh_tmu_device *tmu)
469 /* Skip unused channels. */
470 if (!clockevent && !clocksource)
476 if (tmu->model == SH_TMU_SH3)
477 ch->base = tmu->mapbase + 4 + ch->index * 12;
479 ch->base = tmu->mapbase + 8 + ch->index * 12;
481 ch->irq = platform_get_irq(tmu->pdev, index);
483 dev_err(&tmu->pdev->dev, "ch%u: failed to get irq\n",
488 ch->cs_enabled = false;
489 ch->enable_count = 0;
491 return sh_tmu_register(ch, dev_name(&tmu->pdev->dev),
492 clockevent, clocksource);
495 static int sh_tmu_map_memory(struct sh_tmu_device *tmu)
497 struct resource *res;
499 res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
501 dev_err(&tmu->pdev->dev, "failed to get I/O memory\n");
505 tmu->mapbase = ioremap_nocache(res->start, resource_size(res));
506 if (tmu->mapbase == NULL)
512 static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
514 struct sh_timer_config *cfg = pdev->dev.platform_data;
515 const struct platform_device_id *id = pdev->id_entry;
520 dev_err(&tmu->pdev->dev, "missing platform data\n");
525 tmu->model = id->driver_data;
527 raw_spin_lock_init(&tmu->lock);
529 /* Get hold of clock. */
530 tmu->clk = clk_get(&tmu->pdev->dev, "fck");
531 if (IS_ERR(tmu->clk)) {
532 dev_err(&tmu->pdev->dev, "cannot get clock\n");
533 return PTR_ERR(tmu->clk);
536 ret = clk_prepare(tmu->clk);
540 /* Map the memory resource. */
541 ret = sh_tmu_map_memory(tmu);
543 dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n");
544 goto err_clk_unprepare;
547 /* Allocate and setup the channels. */
548 tmu->num_channels = hweight8(cfg->channels_mask);
550 tmu->channels = kzalloc(sizeof(*tmu->channels) * tmu->num_channels,
552 if (tmu->channels == NULL) {
558 * Use the first channel as a clock event device and the second channel
561 for (i = 0; i < tmu->num_channels; ++i) {
562 ret = sh_tmu_channel_setup(&tmu->channels[i], i,
563 i == 0, i == 1, tmu);
568 platform_set_drvdata(pdev, tmu);
573 kfree(tmu->channels);
574 iounmap(tmu->mapbase);
576 clk_unprepare(tmu->clk);
582 static int sh_tmu_probe(struct platform_device *pdev)
584 struct sh_tmu_device *tmu = platform_get_drvdata(pdev);
587 if (!is_early_platform_device(pdev)) {
588 pm_runtime_set_active(&pdev->dev);
589 pm_runtime_enable(&pdev->dev);
593 dev_info(&pdev->dev, "kept as earlytimer\n");
597 tmu = kzalloc(sizeof(*tmu), GFP_KERNEL);
601 ret = sh_tmu_setup(tmu, pdev);
604 pm_runtime_idle(&pdev->dev);
607 if (is_early_platform_device(pdev))
611 if (tmu->has_clockevent || tmu->has_clocksource)
612 pm_runtime_irq_safe(&pdev->dev);
614 pm_runtime_idle(&pdev->dev);
619 static int sh_tmu_remove(struct platform_device *pdev)
621 return -EBUSY; /* cannot unregister clockevent and clocksource */
624 static const struct platform_device_id sh_tmu_id_table[] = {
625 { "sh-tmu", SH_TMU },
626 { "sh-tmu-sh3", SH_TMU_SH3 },
629 MODULE_DEVICE_TABLE(platform, sh_tmu_id_table);
631 static struct platform_driver sh_tmu_device_driver = {
632 .probe = sh_tmu_probe,
633 .remove = sh_tmu_remove,
637 .id_table = sh_tmu_id_table,
640 static int __init sh_tmu_init(void)
642 return platform_driver_register(&sh_tmu_device_driver);
645 static void __exit sh_tmu_exit(void)
647 platform_driver_unregister(&sh_tmu_device_driver);
650 early_platform_init("earlytimer", &sh_tmu_device_driver);
651 subsys_initcall(sh_tmu_init);
652 module_exit(sh_tmu_exit);
654 MODULE_AUTHOR("Magnus Damm");
655 MODULE_DESCRIPTION("SuperH TMU Timer Driver");
656 MODULE_LICENSE("GPL v2");