2 * linux/arch/arm/plat-mxc/time.c
4 * Copyright (C) 2000-2001 Deep Blue Solutions
5 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
6 * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
7 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/clockchips.h>
27 #include <linux/clk.h>
28 #include <linux/delay.h>
29 #include <linux/err.h>
30 #include <linux/sched_clock.h>
31 #include <linux/slab.h>
33 #include <linux/of_address.h>
34 #include <linux/of_irq.h>
35 #include <soc/imx/timer.h>
38 * There are 4 versions of the timer hardware on Freescale MXC hardware.
41 * - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)
42 * - MX6DL, MX6SX, MX6Q(rev1.1+)
45 /* defines common for all i.MX */
47 #define MXC_TCTL_TEN (1 << 0) /* Enable module */
48 #define MXC_TPRER 0x04
51 #define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
52 #define MX1_2_TCTL_IRQEN (1 << 4)
53 #define MX1_2_TCTL_FRR (1 << 8)
54 #define MX1_2_TCMP 0x08
55 #define MX1_2_TCN 0x10
56 #define MX1_2_TSTAT 0x14
59 #define MX2_TSTAT_CAPT (1 << 1)
60 #define MX2_TSTAT_COMP (1 << 0)
62 /* MX31, MX35, MX25, MX5, MX6 */
63 #define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
64 #define V2_TCTL_CLK_IPG (1 << 6)
65 #define V2_TCTL_CLK_PER (2 << 6)
66 #define V2_TCTL_CLK_OSC_DIV8 (5 << 6)
67 #define V2_TCTL_FRR (1 << 9)
68 #define V2_TCTL_24MEN (1 << 10)
69 #define V2_TPRER_PRE24M 12
72 #define V2_TSTAT_OF1 (1 << 0)
76 #define V2_TIMER_RATE_OSC_DIV8 3000000
79 enum imx_gpt_type type;
84 const struct imx_gpt_data *gpt;
85 struct clock_event_device ced;
86 enum clock_event_mode cem;
94 void (*gpt_setup_tctl)(struct imx_timer *imxtm);
95 void (*gpt_irq_enable)(struct imx_timer *imxtm);
96 void (*gpt_irq_disable)(struct imx_timer *imxtm);
97 void (*gpt_irq_acknowledge)(struct imx_timer *imxtm);
98 int (*set_next_event)(unsigned long evt,
99 struct clock_event_device *ced);
102 static inline struct imx_timer *to_imx_timer(struct clock_event_device *ced)
104 return container_of(ced, struct imx_timer, ced);
107 static void imx1_gpt_irq_disable(struct imx_timer *imxtm)
111 tmp = readl_relaxed(imxtm->base + MXC_TCTL);
112 writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
114 #define imx21_gpt_irq_disable imx1_gpt_irq_disable
116 static void imx31_gpt_irq_disable(struct imx_timer *imxtm)
118 writel_relaxed(0, imxtm->base + V2_IR);
120 #define imx6dl_gpt_irq_disable imx31_gpt_irq_disable
122 static void imx1_gpt_irq_enable(struct imx_timer *imxtm)
126 tmp = readl_relaxed(imxtm->base + MXC_TCTL);
127 writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
129 #define imx21_gpt_irq_enable imx1_gpt_irq_enable
131 static void imx31_gpt_irq_enable(struct imx_timer *imxtm)
133 writel_relaxed(1<<0, imxtm->base + V2_IR);
135 #define imx6dl_gpt_irq_enable imx31_gpt_irq_enable
137 static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm)
139 writel_relaxed(0, imxtm->base + MX1_2_TSTAT);
142 static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm)
144 writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
145 imxtm->base + MX1_2_TSTAT);
148 static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm)
150 writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT);
152 #define imx6dl_gpt_irq_acknowledge imx31_gpt_irq_acknowledge
154 static void __iomem *sched_clock_reg;
156 static u64 notrace mxc_read_sched_clock(void)
158 return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0;
161 static struct delay_timer imx_delay_timer;
163 static unsigned long imx_read_current_timer(void)
165 return readl_relaxed(sched_clock_reg);
168 static int __init mxc_clocksource_init(struct imx_timer *imxtm)
170 unsigned int c = clk_get_rate(imxtm->clk_per);
171 void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn;
173 imx_delay_timer.read_current_timer = &imx_read_current_timer;
174 imx_delay_timer.freq = c;
175 register_current_timer_delay(&imx_delay_timer);
177 sched_clock_reg = reg;
179 sched_clock_register(mxc_read_sched_clock, 32, c);
180 return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
181 clocksource_mmio_readl_up);
186 static int mx1_2_set_next_event(unsigned long evt,
187 struct clock_event_device *ced)
189 struct imx_timer *imxtm = to_imx_timer(ced);
192 tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt;
194 writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP);
196 return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ?
200 static int v2_set_next_event(unsigned long evt,
201 struct clock_event_device *ced)
203 struct imx_timer *imxtm = to_imx_timer(ced);
206 tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt;
208 writel_relaxed(tcmp, imxtm->base + V2_TCMP);
210 return evt < 0x7fffffff &&
211 (int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ?
216 static const char *clock_event_mode_label[] = {
217 [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
218 [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
219 [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
220 [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED",
221 [CLOCK_EVT_MODE_RESUME] = "CLOCK_EVT_MODE_RESUME",
225 static void mxc_set_mode(enum clock_event_mode mode,
226 struct clock_event_device *ced)
228 struct imx_timer *imxtm = to_imx_timer(ced);
232 * The timer interrupt generation is disabled at least
233 * for enough time to call mxc_set_next_event()
235 local_irq_save(flags);
237 /* Disable interrupt in GPT module */
238 imxtm->gpt->gpt_irq_disable(imxtm);
240 if (mode != imxtm->cem) {
241 u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
242 /* Set event time into far-far future */
243 writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);
245 /* Clear pending interrupt */
246 imxtm->gpt->gpt_irq_acknowledge(imxtm);
250 printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
251 clock_event_mode_label[imxtm->cem],
252 clock_event_mode_label[mode]);
255 /* Remember timer mode */
257 local_irq_restore(flags);
260 case CLOCK_EVT_MODE_PERIODIC:
261 printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
262 "supported for i.MX\n");
264 case CLOCK_EVT_MODE_ONESHOT:
266 * Do not put overhead of interrupt enable/disable into
267 * mxc_set_next_event(), the core has about 4 minutes
268 * to call mxc_set_next_event() or shutdown clock after
271 local_irq_save(flags);
272 imxtm->gpt->gpt_irq_enable(imxtm);
273 local_irq_restore(flags);
275 case CLOCK_EVT_MODE_SHUTDOWN:
276 case CLOCK_EVT_MODE_UNUSED:
277 case CLOCK_EVT_MODE_RESUME:
278 /* Left event sources disabled, no more interrupts appear */
284 * IRQ handler for the timer
286 static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
288 struct clock_event_device *ced = dev_id;
289 struct imx_timer *imxtm = to_imx_timer(ced);
292 tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat);
294 imxtm->gpt->gpt_irq_acknowledge(imxtm);
296 ced->event_handler(ced);
301 static int __init mxc_clockevent_init(struct imx_timer *imxtm)
303 struct clock_event_device *ced = &imxtm->ced;
304 struct irqaction *act = &imxtm->act;
306 imxtm->cem = CLOCK_EVT_MODE_UNUSED;
308 ced->name = "mxc_timer1";
309 ced->features = CLOCK_EVT_FEAT_ONESHOT;
310 ced->set_mode = mxc_set_mode;
311 ced->set_next_event = imxtm->gpt->set_next_event;
313 ced->cpumask = cpumask_of(0);
314 clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per),
317 act->name = "i.MX Timer Tick";
318 act->flags = IRQF_TIMER | IRQF_IRQPOLL;
319 act->handler = mxc_timer_interrupt;
322 return setup_irq(imxtm->irq, act);
325 static void imx1_gpt_setup_tctl(struct imx_timer *imxtm)
329 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
330 writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
332 #define imx21_gpt_setup_tctl imx1_gpt_setup_tctl
334 static void imx31_gpt_setup_tctl(struct imx_timer *imxtm)
338 tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
339 if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8)
340 tctl_val |= V2_TCTL_CLK_OSC_DIV8;
342 tctl_val |= V2_TCTL_CLK_PER;
344 writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
347 static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm)
351 tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
352 if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) {
353 tctl_val |= V2_TCTL_CLK_OSC_DIV8;
355 writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER);
356 tctl_val |= V2_TCTL_24MEN;
358 tctl_val |= V2_TCTL_CLK_PER;
361 writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
364 static const struct imx_gpt_data imx1_gpt_data = {
365 .reg_tstat = MX1_2_TSTAT,
366 .reg_tcn = MX1_2_TCN,
367 .reg_tcmp = MX1_2_TCMP,
368 .gpt_irq_enable = imx1_gpt_irq_enable,
369 .gpt_irq_disable = imx1_gpt_irq_disable,
370 .gpt_irq_acknowledge = imx1_gpt_irq_acknowledge,
371 .gpt_setup_tctl = imx1_gpt_setup_tctl,
372 .set_next_event = mx1_2_set_next_event,
375 static const struct imx_gpt_data imx21_gpt_data = {
376 .reg_tstat = MX1_2_TSTAT,
377 .reg_tcn = MX1_2_TCN,
378 .reg_tcmp = MX1_2_TCMP,
379 .gpt_irq_enable = imx21_gpt_irq_enable,
380 .gpt_irq_disable = imx21_gpt_irq_disable,
381 .gpt_irq_acknowledge = imx21_gpt_irq_acknowledge,
382 .gpt_setup_tctl = imx21_gpt_setup_tctl,
383 .set_next_event = mx1_2_set_next_event,
386 static const struct imx_gpt_data imx31_gpt_data = {
387 .reg_tstat = V2_TSTAT,
390 .gpt_irq_enable = imx31_gpt_irq_enable,
391 .gpt_irq_disable = imx31_gpt_irq_disable,
392 .gpt_irq_acknowledge = imx31_gpt_irq_acknowledge,
393 .gpt_setup_tctl = imx31_gpt_setup_tctl,
394 .set_next_event = v2_set_next_event,
397 static const struct imx_gpt_data imx6dl_gpt_data = {
398 .reg_tstat = V2_TSTAT,
401 .gpt_irq_enable = imx6dl_gpt_irq_enable,
402 .gpt_irq_disable = imx6dl_gpt_irq_disable,
403 .gpt_irq_acknowledge = imx6dl_gpt_irq_acknowledge,
404 .gpt_setup_tctl = imx6dl_gpt_setup_tctl,
405 .set_next_event = v2_set_next_event,
408 static void __init _mxc_timer_init(struct imx_timer *imxtm)
410 switch (imxtm->type) {
412 imxtm->gpt = &imx1_gpt_data;
415 imxtm->gpt = &imx21_gpt_data;
418 imxtm->gpt = &imx31_gpt_data;
420 case GPT_TYPE_IMX6DL:
421 imxtm->gpt = &imx6dl_gpt_data;
427 if (IS_ERR(imxtm->clk_per)) {
428 pr_err("i.MX timer: unable to get clk\n");
432 if (!IS_ERR(imxtm->clk_ipg))
433 clk_prepare_enable(imxtm->clk_ipg);
435 clk_prepare_enable(imxtm->clk_per);
438 * Initialise to a known state (all timers off, and timing reset)
441 writel_relaxed(0, imxtm->base + MXC_TCTL);
442 writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */
444 imxtm->gpt->gpt_setup_tctl(imxtm);
446 /* init and register the timer to the framework */
447 mxc_clocksource_init(imxtm);
448 mxc_clockevent_init(imxtm);
451 void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type)
453 struct imx_timer *imxtm;
455 imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
458 imxtm->clk_per = clk_get_sys("imx-gpt.0", "per");
459 imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg");
461 imxtm->base = ioremap(pbase, SZ_4K);
462 BUG_ON(!imxtm->base);
467 _mxc_timer_init(imxtm);
470 static void __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type type)
472 struct imx_timer *imxtm;
473 static int initialized;
475 /* Support one instance only */
479 imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
482 imxtm->base = of_iomap(np, 0);
483 WARN_ON(!imxtm->base);
484 imxtm->irq = irq_of_parse_and_map(np, 0);
486 imxtm->clk_ipg = of_clk_get_by_name(np, "ipg");
488 /* Try osc_per first, and fall back to per otherwise */
489 imxtm->clk_per = of_clk_get_by_name(np, "osc_per");
490 if (IS_ERR(imxtm->clk_per))
491 imxtm->clk_per = of_clk_get_by_name(np, "per");
495 _mxc_timer_init(imxtm);
500 static void __init imx1_timer_init_dt(struct device_node *np)
502 mxc_timer_init_dt(np, GPT_TYPE_IMX1);
505 static void __init imx21_timer_init_dt(struct device_node *np)
507 mxc_timer_init_dt(np, GPT_TYPE_IMX21);
510 static void __init imx31_timer_init_dt(struct device_node *np)
512 enum imx_gpt_type type = GPT_TYPE_IMX31;
515 * We were using the same compatible string for i.MX6Q/D and i.MX6DL/S
516 * GPT device, while they actually have different programming model.
517 * This is a workaround to keep the existing i.MX6DL/S DTBs continue
518 * working with the new kernel.
520 if (of_machine_is_compatible("fsl,imx6dl"))
521 type = GPT_TYPE_IMX6DL;
523 mxc_timer_init_dt(np, type);
526 static void __init imx6dl_timer_init_dt(struct device_node *np)
528 mxc_timer_init_dt(np, GPT_TYPE_IMX6DL);
531 CLOCKSOURCE_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
532 CLOCKSOURCE_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
533 CLOCKSOURCE_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt);
534 CLOCKSOURCE_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
535 CLOCKSOURCE_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
536 CLOCKSOURCE_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
537 CLOCKSOURCE_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
538 CLOCKSOURCE_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
539 CLOCKSOURCE_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
540 CLOCKSOURCE_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
541 CLOCKSOURCE_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
542 CLOCKSOURCE_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);