2 * Copyright (C) Maxime Coquelin 2015
3 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * License terms: GNU General Public License (GPL), version 2
6 * Inspired by time-efm32.c from Uwe Kleine-Koenig
9 #include <linux/kernel.h>
10 #include <linux/clocksource.h>
11 #include <linux/clockchips.h>
12 #include <linux/irq.h>
13 #include <linux/interrupt.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/clk.h>
18 #include <linux/reset.h>
27 #define TIM_CR1_CEN BIT(0)
28 #define TIM_CR1_OPM BIT(3)
29 #define TIM_CR1_ARPE BIT(7)
31 #define TIM_DIER_UIE BIT(0)
33 #define TIM_SR_UIF BIT(0)
35 #define TIM_EGR_UG BIT(0)
37 struct stm32_clock_event_ddata {
38 struct clock_event_device evtdev;
39 unsigned periodic_top;
43 static void stm32_clock_event_set_mode(enum clock_event_mode mode,
44 struct clock_event_device *evtdev)
46 struct stm32_clock_event_ddata *data =
47 container_of(evtdev, struct stm32_clock_event_ddata, evtdev);
48 void *base = data->base;
51 case CLOCK_EVT_MODE_PERIODIC:
52 writel_relaxed(data->periodic_top, base + TIM_ARR);
53 writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, base + TIM_CR1);
56 case CLOCK_EVT_MODE_ONESHOT:
58 writel_relaxed(0, base + TIM_CR1);
63 static int stm32_clock_event_set_next_event(unsigned long evt,
64 struct clock_event_device *evtdev)
66 struct stm32_clock_event_ddata *data =
67 container_of(evtdev, struct stm32_clock_event_ddata, evtdev);
69 writel_relaxed(evt, data->base + TIM_ARR);
70 writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN,
71 data->base + TIM_CR1);
76 static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id)
78 struct stm32_clock_event_ddata *data = dev_id;
80 writel_relaxed(0, data->base + TIM_SR);
82 data->evtdev.event_handler(&data->evtdev);
87 static struct stm32_clock_event_ddata clock_event_ddata = {
89 .name = "stm32 clockevent",
90 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
91 .set_mode = stm32_clock_event_set_mode,
92 .set_next_event = stm32_clock_event_set_next_event,
97 static void __init stm32_clockevent_init(struct device_node *np)
99 struct stm32_clock_event_ddata *data = &clock_event_ddata;
101 struct reset_control *rstc;
102 unsigned long rate, max_delta;
103 int irq, ret, bits, prescaler = 1;
105 clk = of_clk_get(np, 0);
108 pr_err("failed to get clock for clockevent (%d)\n", ret);
112 ret = clk_prepare_enable(clk);
114 pr_err("failed to enable timer clock for clockevent (%d)\n",
119 rate = clk_get_rate(clk);
121 rstc = of_reset_control_get(np, NULL);
123 reset_control_assert(rstc);
124 reset_control_deassert(rstc);
127 data->base = of_iomap(np, 0);
129 pr_err("failed to map registers for clockevent\n");
133 irq = irq_of_parse_and_map(np, 0);
135 pr_err("%s: failed to get irq.\n", np->full_name);
139 /* Detect whether the timer is 16 or 32 bits */
140 writel_relaxed(~0U, data->base + TIM_ARR);
141 max_delta = readl_relaxed(data->base + TIM_ARR);
142 if (max_delta == ~0U) {
149 writel_relaxed(0, data->base + TIM_ARR);
151 writel_relaxed(prescaler - 1, data->base + TIM_PSC);
152 writel_relaxed(TIM_EGR_UG, data->base + TIM_EGR);
153 writel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER);
154 writel_relaxed(0, data->base + TIM_SR);
156 data->periodic_top = DIV_ROUND_CLOSEST(rate, prescaler * HZ);
158 clockevents_config_and_register(&data->evtdev,
159 DIV_ROUND_CLOSEST(rate, prescaler),
162 ret = request_irq(irq, stm32_clock_event_handler, IRQF_TIMER,
163 "stm32 clockevent", data);
165 pr_err("%s: failed to request irq.\n", np->full_name);
169 pr_info("%s: STM32 clockevent driver initialized (%d bits)\n",
170 np->full_name, bits);
177 clk_disable_unprepare(clk);
184 CLOCKSOURCE_OF_DECLARE(stm32, "st,stm32-timer", stm32_clockevent_init);