1 /****************************************************************
3 Siano Mobile Silicon, Inc.
4 MDTV receiver kernel modules.
5 Copyright (C) 2006-2008, Uri Shkolnik
7 This program is free software: you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation, either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>.
20 ****************************************************************/
23 #include <linux/kernel.h>
25 #include <asm/hardware.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
30 #include <linux/interrupt.h>
31 #include <linux/irq.h>
32 #include <linux/dma-mapping.h>
34 #include <linux/module.h>
35 #include <linux/device.h>
36 #include <linux/delay.h>
38 #include "smsdbg_prn.h"
39 #include <linux/spi/spi.h>
40 #include <asm/arch/gpio.h>
41 #include "smscoreapi.h"
44 #define CMMB_1186_SPIIRQ GPIOPortE_Pin1//This Pin is SDK Board GPIOPortE_Pin1
48 #define SSP_CKEN CKEN_SSP1
49 #define SMS_IRQ_GPIO MFP_PIN_GPIO5
52 #define SDCMR_RX DRCMRRXSSDR
53 #define SDCMR_TX DRCMRTXSSDR
56 #define SDCMR_RX DRCMR15
57 #define SDCMR_TX DRCMR16
60 #define SDCMR_RX DRCMR66
61 #define SDCMR_TX DRCMR67
64 #define SDCMR_RX DRCMRRXSADR
65 #define SDCMR_TX DRCMRTXSADR
72 /* Macros defining physical layer behaviour*/
74 #define CLOCK_FACTOR 1
75 //#define CLOCK_FACTOR 2
77 #define CLOCK_FACTOR 2
78 #endif /*PXA_310_LV */
80 /* Macros for coding reuse */
82 /*! macro to align the divider to the proper offset in the register bits */
83 #define CLOCK_DIVIDER(i)((i-1)<<8) /* 1-4096 */
85 /*! DMA related macros */
86 #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
87 #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
89 #define SSP_TIMEOUT_SCALE (769)
90 #define SSP_TIMEOUT(x) ((x*10000)/SSP_TIMEOUT_SCALE)
92 #define SPI_PACKET_SIZE 256
96 // in android platform 2.6.25 , need to check the Reg bit by bit later
97 #define GSDR(x) __REG2(0x40e00400, ((x) & 0x60) >> 3)
98 #define GCDR(x) __REG2(0x40300420, ((x) & 0x60) >> 3)
100 #define GSRER(x) __REG2(0x40e00440, ((x) & 0x60) >> 3)
101 #define GCRER(x) __REG2(0x40e00460, ((x) & 0x60) >> 3)
104 #define GPIO_DIR_IN 0
106 #define SSCR0_P1 __REG(0x41000000) /* SSP Port 1 Control Register 0 */
107 #define SSCR1_P1 __REG(0x41000004) /* SSP Port 1 Control Register 1 */
108 #define SSSR_P1 __REG(0x41000008) /* SSP Port 1 Status Register */
109 #define SSITR_P1 __REG(0x4100000C) /* SSP Port 1 Interrupt Test Register */
110 #define SSDR_P1 __REG(0x41000010) /* (Write / Read) SSP Port 1 Data Write Register/SSP Data Read Register */
112 unsigned long u_irq_count =0;
115 /**********************************************************************/
116 //to support dma 16byte burst size
117 // change SPI TS according to marvel recomendations
119 #define DMA_BURST_SIZE DCMD_BURST16 //DCMD_BURST8
120 #define SPI_RX_FIFO_RFT SSCR1_RxTresh(4) //SSCR1_RxTresh(1)
121 #define SPI_TX_FIFO_TFT SSCR1_TxTresh(3) //SSCR1_TxTresh(1)
124 /**********************************************************************/
126 #include <linux/notifier.h>
128 static unsigned int dma_rxbuf_phy_addr ;
129 static unsigned int dma_txbuf_phy_addr ;
131 static int rx_dma_channel =0 ;
132 static int tx_dma_channel =0 ;
133 static volatile int dma_len = 0 ;
134 static volatile int tx_len = 0 ;
136 static struct ssp_dev* panic_sspdev = NULL ;
139 extern void smscore_panic_print(void);
140 extern void spilog_panic_print(void) ;
141 static void chip_powerdown();
142 extern void smschar_reset_device(void);
144 static int sms_panic_handler(struct notifier_block *this,
148 static int panic_event_handled = 0;
149 if(!panic_event_handled)
151 smscore_panic_print() ;
152 spilog_panic_print() ;
153 printk("last tx_len = %d\n",tx_len) ;
154 printk("last DMA len = %d\n",dma_len) ;
156 printk("rxbuf_addr=[0x%x],Rx DSADR=[0x%x] DTADR=[0x%x] DCSR=[0x%x] DCMD=[0x%x]\n",
157 dma_rxbuf_phy_addr, DSADR(rx_dma_channel),DTADR(rx_dma_channel),
158 DCSR(rx_dma_channel),DCMD(rx_dma_channel) );
160 printk("txbuf_addr=[0x%x],Tx DSADR=[0x%x] DTADR=[0x%x] DCSR[0x%x] DCMD=[0x%x]\n",
161 dma_txbuf_phy_addr, DSADR(tx_dma_channel),DTADR(tx_dma_channel),
162 DCSR(tx_dma_channel),DCMD(tx_dma_channel) );
165 printk("SSCR0 =[0x%x]\n",__raw_readl(panic_sspdev->ssp->mmio_base + SSCR0)) ;
166 printk("SSCR1 =[0x%x]\n",__raw_readl(panic_sspdev->ssp->mmio_base + SSCR1)) ;
167 printk("SSTO =[0x%x]\n",__raw_readl(panic_sspdev->ssp->mmio_base + SSTO)) ;
168 printk("SSPSP =[0x%x]\n",__raw_readl(panic_sspdev->ssp->mmio_base + SSPSP)) ;
169 printk("SSSR =[0x%x]\n",__raw_readl(panic_sspdev->ssp->mmio_base + SSSR)) ;
173 panic_event_handled =1 ;
178 static struct notifier_block sms_panic_notifier = {
179 .notifier_call = sms_panic_handler,
181 .priority = 150 /* priority: INT_MAX >= x >= 0 */
187 /*! GPIO functions for PXA3xx
190 void pxa3xx_gpio_set_rising_edge_detect (int gpio_id, int dir)
194 int gpio = mfp_to_gpio(gpio_id);
196 // if (gpio >= GPIO_EXP_START)
200 // spin_lock_irqsave(&gpio_spin_lock, flags);
201 local_irq_save(flags);
203 if ( dir == GPIO_DIR_IN)
204 GCRER(gpio) =1u << (gpio& 0x1f);
206 GSRER(gpio) =1u << (gpio& 0x1f);
207 local_irq_restore(flags);
211 void pxa3xx_gpio_set_direction(int gpio_id , int dir)
215 int gpio = mfp_to_gpio(gpio_id);
217 local_irq_save(flags);
219 if ( dir == GPIO_DIR_IN)
220 GCDR(gpio) =1u << (gpio& 0x1f);
222 GSDR(gpio) =1u << (gpio& 0x1f);
223 local_irq_restore(flags);
226 //////////////////////////////////////////////////////////
228 /* physical layer variables */
229 /*! global bus data */
230 struct spiphy_dev_s {
231 //struct ssp_dev sspdev; /*!< ssp port configuration */
232 struct completion transfer_in_process;
233 struct spi_device *Smsdevice;
234 void (*interruptHandler) (void *);
236 struct device *dev; /*!< device model stuff */
247 invert the endianness of a single 32it integer
249 \param[in] u: word to invert
251 \return the inverted word
253 static inline u32 invert_bo(u32 u)
255 return ((u & 0xff) << 24) | ((u & 0xff00) << 8) | ((u & 0xff0000) >> 8)
256 | ((u & 0xff000000) >> 24);
260 invert the endianness of a data buffer
262 \param[in] buf: buffer to invert
263 \param[in] len: buffer length
265 \return the inverted word
268 static int invert_endianness(char *buf, int len)
271 u32 *ptr = (u32 *) buf;
274 for (i = 0; i < len; i++, ptr++)
275 *ptr = invert_bo(*ptr);
277 return 4 * ((len + 3) & (~3));
280 /*! Map DMA buffers when request starts
284 static unsigned long dma_map_buf(struct spiphy_dev_s *spiphy_dev, char *buf,
285 int len, int direction)
287 unsigned long phyaddr;
288 /* map dma buffers */
290 PERROR(" NULL buffers to map\n");
294 phyaddr = dma_map_single(spiphy_dev->dev, buf, len, direction);
295 if (dma_mapping_error(phyaddr)) {
296 PERROR("exiting with error\n");
302 static irqreturn_t spibus_interrupt(int irq, void *context)
304 struct spiphy_dev_s *spiphy_dev = (struct spiphy_dev_s *) context;
308 PDEBUG("INT counter = %d\n", u_irq_count);
310 sms_debug("spibus_interrupt\n");
312 if (spiphy_dev->interruptHandler)
313 spiphy_dev->interruptHandler(spiphy_dev->intr_context);
319 /*! DMA controller callback - called only on BUS error condition
321 \param[in] channel: DMA channel with error
322 \param[in] data: Unused
323 \param[in] regs: Unused
327 //extern dma_addr_t common_buf_end ;
329 static void spibus_dma_handler(int channel, void *context)
332 struct spiphy_dev_s *spiphy_dev = (struct spiphy_dev_s *) context;
333 u32 irq_status = DCSR(channel) & DMA_INT_MASK;
335 // printk( "recieved interrupt from dma channel %d irq status %x.\n",
336 // channel, irq_status);
337 if (irq_status & DCSR_BUSERR) {
338 printk(KERN_EMERG "bus error!!! resetting channel %d\n", channel);
340 DCSR(spiphy_dev->rx_dma_channel) = RESET_DMA_CHANNEL;
341 DCSR(spiphy_dev->tx_dma_channel) = RESET_DMA_CHANNEL;
343 DCSR(spiphy_dev->rx_dma_channel) = RESET_DMA_CHANNEL;
344 complete(&spiphy_dev->transfer_in_process);
348 void smsspibus_xfer(void *context, unsigned char *txbuf,
349 unsigned long txbuf_phy_addr, unsigned char *rxbuf,
350 unsigned long rxbuf_phy_addr, int len)
352 struct spiphy_dev_s *spiphy_dev = (struct spiphy_dev_s *) context;
353 unsigned char *temp = NULL;
356 //printk(KERN_INFO "smsspibus_xfer \n");
357 //printk(KERN_INFO "smsspibus_xfer txbuf = 0x%x\n",txbuf);
358 //printk(KERN_INFO "smsspibus_xfer rxbuf = 0x%x\n",rxbuf);
359 //printk(KERN_INFO "smsspibus_xfer len=0x%x\n",len);
367 // sms_debug("spi write buf[4] = 0x%x buf[5] = 0x%x\n", txbuf[4],txbuf[5]);
368 ret = spi_write(spiphy_dev->Smsdevice, txbuf, len);
374 temp = kmalloc(len,GFP_KERNEL);
377 sms_err("sms spi write temp malloc fail");
380 memset(temp,0xFF,len);
381 sms_debug("sms spi write temp buf");
382 ret = spi_write(spiphy_dev->Smsdevice, temp, len);
386 // sms_err(KERN_INFO "smsspibus_xfer spi write ret=0x%x\n",ret);
388 // memset (rxbuf, 0xff, 256);
391 if ((rxbuf)&&(len != 16))
392 ret = spi_read(spiphy_dev->Smsdevice, rxbuf, len);
394 //sms_debug("sms spi read buf=0x%x\n",rxbuf[0]);
395 //sms_debug("sms spi read buf=0x%x\n",rxbuf[1]);
396 //sms_debug("sms spi read buf=0x%x\n",rxbuf[2]);
397 //sms_debug("sms spi read buf=0x%x\n",rxbuf[3]);
398 // printk(KERN_INFO "after sms spi read buf[0]=0x%x\n",rxbuf[0]);
400 // printk(KERN_INFO "sms spi read buf[8]=0x%x\n",rxbuf[8]);
401 // printk(KERN_INFO "sms spi read buf[9]=0x%x\n",rxbuf[9]);
404 spi_write_then_read(spiphy_dev->Smsdevice,txbuf,len,rxbuf,len);
406 //spi_write_then_read(struct spi_device *spi, const u8 *txbuf, unsigned n_tx, u8 *rxbuf, unsigned n_rx);
408 /* DMA burst is 8 bytes, therefore we need tmp buffer that size. */
409 // to support dma 16byte burst size
410 unsigned long tmp[4];
411 //unsigned long tmp[2];
414 struct spiphy_dev_s *spiphy_dev = (struct spiphy_dev_s *) context;
415 unsigned long expire;
418 expire = msecs_to_jiffies(200) ;
419 /* program the controller */
423 invert_endianness(txbuf, len);
437 dma_map_buf(spiphy_dev, (char *)tmp, sizeof(tmp),
443 txdma = txbuf_phy_addr;
447 init_completion(&spiphy_dev->transfer_in_process);
448 /* configure DMA Controller */
449 DCSR(spiphy_dev->rx_dma_channel) = RESET_DMA_CHANNEL;
450 DSADR(spiphy_dev->rx_dma_channel) = __PREG(SSDR_P(SSP_PORT));
451 DTADR(spiphy_dev->rx_dma_channel) = rxbuf_phy_addr;
454 // to support dma 16byte burst size
455 DCMD(spiphy_dev->rx_dma_channel) = DCMD_INCTRGADDR | DCMD_FLOWSRC
456 | DCMD_WIDTH4 | DCMD_ENDIRQEN | DMA_BURST_SIZE | len;
460 rx_dma_channel = spiphy_dev->rx_dma_channel ;
461 dma_rxbuf_phy_addr = (unsigned int) rxbuf_phy_addr ;
463 // PDEBUG("rx channel=%d, src=0x%x, dst=0x%x, cmd=0x%x\n",
464 // spiphy_dev->rx_dma_channel, __PREG(SSDR_P(SSP_PORT)),
465 // (unsigned int)rxbuf_phy_addr, DCMD(spiphy_dev->rx_dma_channel));
466 spiphy_dev->rx_buf_len = len;
468 DCSR(spiphy_dev->tx_dma_channel) = RESET_DMA_CHANNEL;
469 DTADR(spiphy_dev->tx_dma_channel) = __PREG(SSDR_P(SSP_PORT));
472 DSADR(spiphy_dev->tx_dma_channel) = txdma;
474 tx_dma_channel = spiphy_dev->tx_dma_channel;
475 dma_txbuf_phy_addr = (unsigned int) txdma ;
478 DCMD(spiphy_dev->tx_dma_channel) =
479 DCMD_INCSRCADDR | DCMD_FLOWTRG | DCMD_WIDTH4
480 /* | DCMD_ENDIRQEN */ | DMA_BURST_SIZE | len;
481 spiphy_dev->tx_buf_len = len;
483 DCMD(spiphy_dev->tx_dma_channel) = DCMD_FLOWTRG
484 | DCMD_WIDTH4 /* | DCMD_ENDIRQEN */ |DMA_BURST_SIZE | len;
485 spiphy_dev->tx_buf_len = 4;
489 printk("Tx DSADR=[0x%x],DTADR=[0x%x],DCMD=[0x%x],len =[0x%x]\n",
490 DSADR(spiphy_dev->tx_dma_channel),DTADR(spiphy_dev->tx_dma_channel),DCMD(spiphy_dev->tx_dma_channel),len) ;
492 // PDEBUG("tx channel=%d, src=0x%x, dst=0x%x, cmd=0x%x\n",
493 // spiphy_dev->tx_dma_channel, (unsigned int)txdma,
494 // __PREG(SSDR_P(SSP_PORT)), DCMD(spiphy_dev->tx_dma_channel));
495 /* DALGN - DMA ALIGNMENT REG. */
496 if (rxbuf_phy_addr & 0x7)
497 DALGN |= (1 << spiphy_dev->rx_dma_channel);
499 DALGN &= ~(1 << spiphy_dev->rx_dma_channel);
501 DALGN |= (1 << spiphy_dev->tx_dma_channel);
503 DALGN &= ~(1 << spiphy_dev->tx_dma_channel);
505 /* Start DMA controller */
506 //printk( "smsmdtv: Start DMA controller\n");
507 DCSR(spiphy_dev->rx_dma_channel) |= DCSR_RUN;
508 DCSR(spiphy_dev->tx_dma_channel) |= DCSR_RUN;
509 // printk( "DMA running. wait for completion.\n");
511 //printk( "smsmdtv: before wait_for_completion_timeout\n");
512 res = wait_for_completion_timeout(&spiphy_dev->transfer_in_process,expire);
515 printk( "smsmdtv DMA timeout, res=0x%x len =%d\n", res, len);
516 printk( "smsmdtv DMA reg, 0x%x %x \n",DCSR(spiphy_dev->rx_dma_channel), DCSR(spiphy_dev->tx_dma_channel) );
517 DCSR(spiphy_dev->rx_dma_channel) = RESET_DMA_CHANNEL;
518 DCSR(spiphy_dev->tx_dma_channel) = RESET_DMA_CHANNEL;
520 complete(&spiphy_dev->transfer_in_process);
524 //printk( "DMA complete.\n");
525 invert_endianness(rxbuf, len);
528 PDEBUG("rx[4]:0x%x;[6]:0x%x \n", rxbuf[4], rxbuf[6]);
530 //printk( "smsmdtv: Xfer end\n");
534 void smschipreset(void *context)
539 static struct ssp_state sms_ssp_state ;
541 void smsspibus_ssp_suspend(void* context )
543 struct spiphy_dev_s *spiphy_dev ;
544 printk("entering smsspibus_ssp_suspend\n");
547 PERROR("smsspibus_ssp_suspend context NULL \n") ;
550 spiphy_dev = (struct spiphy_dev_s *) context;
552 //ssp_flush(&(spiphy_dev->sspdev)) ;
553 //ssp_save_state(&(spiphy_dev->sspdev) , &sms_ssp_state) ;
554 //ssp_disable(&(spiphy_dev->sspdev));
555 //ssp_exit(&spiphy_dev->sspdev);
556 free_irq(CMMB_1186_SPIIRQ, spiphy_dev);
558 /* release DMA resources */
559 //if (spiphy_dev->rx_dma_channel >= 0)
560 //pxa_free_dma(spiphy_dev->rx_dma_channel);
562 //if (spiphy_dev->tx_dma_channel >= 0)
563 //pxa_free_dma(spiphy_dev->tx_dma_channel);
567 static void chip_poweron()
570 #ifdef CONFIG_MACH_LC6830_PHONE_BOARD_1_0
571 gpio_direction_output(mfp_to_gpio(MFP_PIN_GPIO4), 1);
573 gpio_direction_output(mfp_to_gpio(MFP_PIN_GPIO6), 1);
575 #elif defined CONFIG_MACH_LC6830_PHONE_BOARD_1_1
576 gpio_direction_output(mfp_to_gpio(MFP_PIN_GPIO6), 1);
578 gpio_direction_output(mfp_to_gpio(MFP_PIN_GPIO8), 1);
580 gpio_direction_output(mfp_to_gpio(MFP_PIN_GPIO4), 1);
586 static void chip_powerdown()
589 #ifdef CONFIG_MACH_LC6830_PHONE_BOARD_1_0
590 gpio_direction_output(mfp_to_gpio(MFP_PIN_GPIO4), 0);
592 gpio_direction_output(mfp_to_gpio(MFP_PIN_GPIO6), 0);
593 #elif defined CONFIG_MACH_LC6830_PHONE_BOARD_1_1
594 gpio_direction_output(mfp_to_gpio(MFP_PIN_GPIO4), 0);
596 gpio_direction_output(mfp_to_gpio(MFP_PIN_GPIO8), 0);
598 gpio_direction_output(mfp_to_gpio(MFP_PIN_GPIO6), 0);
604 int smsspibus_ssp_resume(void* context)
607 struct spiphy_dev_s *spiphy_dev ;
608 u32 mode = 0, flags = 0, psp_flags = 0, speed = 0;
609 printk("entering smsspibus_ssp_resume\n");
612 PERROR("smsspibus_ssp_resume context NULL \n");
615 spiphy_dev = (struct spiphy_dev_s *) context;
617 //ret = ssp_init(&spiphy_dev->sspdev, SSP_PORT, 0);
619 //PERROR("ssp_init failed. error %d", ret);
621 //GPIOPullUpDown(CMMB_1186_SPIIRQ, IRQT_FALLING);
622 //err = request_gpio_irq(PT2046_PENIRQ,xpt2046_ts_interrupt,GPIOEdgelFalling,ts_dev);
623 //ret = request_gpio_irq(CMMB_1186_SPIIRQ, (pFunc)spibus_interrupt, GPIOEdgelRising, spiphy_dev);
625 printk("siano1186 request irq failed !!\n");
631 free_irq(CMMB_1186_SPIIRQ,NULL);
636 void *smsspiphy_init(void *context, void (*smsspi_interruptHandler) (void *),
640 struct spiphy_dev_s *spiphy_dev;
641 u32 mode = 0, flags = 0, psp_flags = 0, speed = 0;
643 sms_debug("smsspiphy_init\n");
645 spiphy_dev = kmalloc(sizeof(struct spiphy_dev_s), GFP_KERNEL);
648 printk("spiphy_dev is null in smsspiphy_init\n") ;
652 spiphy_dev->interruptHandler = smsspi_interruptHandler;
653 spiphy_dev->intr_context = intr_context;
654 spiphy_dev->Smsdevice = (struct spi_device*)context;
656 GPIOPullUpDown(CMMB_1186_SPIIRQ, IRQT_FALLING);
658 ret = request_gpio_irq(CMMB_1186_SPIIRQ, spibus_interrupt, GPIOEdgelRising, spiphy_dev);//
661 printk("siano 1186 request irq failed !!\n");
666 atomic_notifier_chain_register(&panic_notifier_list,&sms_panic_notifier);
667 //panic_sspdev = &(spiphy_dev->sspdev) ;
674 //if (spiphy_dev->tx_dma_channel >= 0)
675 //pxa_free_dma(spiphy_dev->tx_dma_channel);
678 //if (spiphy_dev->rx_dma_channel >= 0)
679 //pxa_free_dma(spiphy_dev->rx_dma_channel);
682 // ssp_exit(&spiphy_dev->sspdev);
684 //PDEBUG("exiting on error\n");
685 printk("exiting on error\n");
687 free_irq(CMMB_1186_SPIIRQ,NULL);
691 int smsspiphy_deinit(void *context)
693 struct spiphy_dev_s *spiphy_dev = (struct spiphy_dev_s *) context;
694 PDEBUG("entering\n");
696 printk("entering smsspiphy_deinit\n");
699 atomic_notifier_chain_unregister(&panic_notifier_list,
700 &sms_panic_notifier);
706 void smsspiphy_set_config(struct spiphy_dev_s *spiphy_dev, int clock_divider)
708 //u32 mode, flags, speed, psp_flags = 0;
709 //ssp_disable(&spiphy_dev->sspdev);
710 /* clock divisor for this mode. */
711 //speed = CLOCK_DIVIDER(clock_divider);
712 /* 32bit words in the fifo */
713 //mode = SSCR0_Motorola | SSCR0_DataSize(16) | SSCR0_EDSS;
714 //flags = SPI_RX_FIFO_RFT |SPI_TX_FIFO_TFT | SSCR1_TSRE |
715 //SSCR1_RSRE | SSCR1_RIE | SSCR1_TRAIL; /* | SSCR1_TIE */
716 //ssp_config(&spiphy_dev->sspdev, mode, flags, psp_flags, speed);
717 //ssp_enable(&spiphy_dev->sspdev);
720 void prepareForFWDnl(void *context)
722 struct spiphy_dev_s *spiphy_dev = (struct spiphy_dev_s *) context;
723 smsspiphy_set_config(spiphy_dev, 3);
727 void fwDnlComplete(void *context, int App)
729 struct spiphy_dev_s *spiphy_dev = (struct spiphy_dev_s *) context;
730 smsspiphy_set_config(spiphy_dev, 1);