2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS4210 - CPU frequency scaling support
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/err.h>
15 #include <linux/clk.h>
17 #include <linux/slab.h>
18 #include <linux/cpufreq.h>
20 #include <mach/regs-clock.h>
21 #include <mach/cpufreq.h>
23 static struct clk *cpu_clk;
24 static struct clk *moutcore;
25 static struct clk *mout_mpll;
26 static struct clk *mout_apll;
28 static unsigned int exynos4210_volt_table[] = {
29 1250000, 1150000, 1050000, 975000, 950000,
32 static struct cpufreq_frequency_table exynos4210_freq_table[] = {
38 {0, CPUFREQ_TABLE_END},
41 static struct apll_freq apll_freq_4210[] = {
45 * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, RESERVED
46 * clock divider for COPY, HPM, RESERVED
49 APLL_FREQ(1200, 0, 3, 7, 3, 4, 1, 7, 0, 5, 0, 0, 150, 3, 1),
50 APLL_FREQ(1000, 0, 3, 7, 3, 4, 1, 7, 0, 4, 0, 0, 250, 6, 1),
51 APLL_FREQ(800, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 200, 6, 1),
52 APLL_FREQ(500, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 250, 6, 2),
53 APLL_FREQ(200, 0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3),
56 static void exynos4210_set_clkdiv(unsigned int div_index)
60 /* Change Divider - CPU0 */
62 tmp = apll_freq_4210[div_index].clk_div_cpu0;
64 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
67 tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
68 } while (tmp & 0x1111111);
70 /* Change Divider - CPU1 */
72 tmp = apll_freq_4210[div_index].clk_div_cpu1;
74 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
77 tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
81 static void exynos4210_set_apll(unsigned int index)
85 /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
86 clk_set_parent(moutcore, mout_mpll);
89 tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
90 >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
94 /* 2. Set APLL Lock time */
95 __raw_writel(EXYNOS4_APLL_LOCKTIME, EXYNOS4_APLL_LOCK);
97 /* 3. Change PLL PMS values */
98 tmp = __raw_readl(EXYNOS4_APLL_CON0);
99 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
100 tmp |= apll_freq_4210[index].mps;
101 __raw_writel(tmp, EXYNOS4_APLL_CON0);
103 /* 4. wait_lock_time */
105 tmp = __raw_readl(EXYNOS4_APLL_CON0);
106 } while (!(tmp & (0x1 << EXYNOS4_APLLCON0_LOCKED_SHIFT)));
108 /* 5. MUX_CORE_SEL = APLL */
109 clk_set_parent(moutcore, mout_apll);
112 tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
113 tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
114 } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
117 static bool exynos4210_pms_change(unsigned int old_index, unsigned int new_index)
119 unsigned int old_pm = apll_freq_4210[old_index].mps >> 8;
120 unsigned int new_pm = apll_freq_4210[new_index].mps >> 8;
122 return (old_pm == new_pm) ? 0 : 1;
125 static void exynos4210_set_frequency(unsigned int old_index,
126 unsigned int new_index)
130 if (old_index > new_index) {
131 if (!exynos4210_pms_change(old_index, new_index)) {
132 /* 1. Change the system clock divider values */
133 exynos4210_set_clkdiv(new_index);
135 /* 2. Change just s value in apll m,p,s value */
136 tmp = __raw_readl(EXYNOS4_APLL_CON0);
138 tmp |= apll_freq_4210[new_index].mps & 0x7;
139 __raw_writel(tmp, EXYNOS4_APLL_CON0);
141 /* Clock Configuration Procedure */
142 /* 1. Change the system clock divider values */
143 exynos4210_set_clkdiv(new_index);
144 /* 2. Change the apll m,p,s value */
145 exynos4210_set_apll(new_index);
147 } else if (old_index < new_index) {
148 if (!exynos4210_pms_change(old_index, new_index)) {
149 /* 1. Change just s value in apll m,p,s value */
150 tmp = __raw_readl(EXYNOS4_APLL_CON0);
152 tmp |= apll_freq_4210[new_index].mps & 0x7;
153 __raw_writel(tmp, EXYNOS4_APLL_CON0);
155 /* 2. Change the system clock divider values */
156 exynos4210_set_clkdiv(new_index);
158 /* Clock Configuration Procedure */
159 /* 1. Change the apll m,p,s value */
160 exynos4210_set_apll(new_index);
161 /* 2. Change the system clock divider values */
162 exynos4210_set_clkdiv(new_index);
167 int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
171 cpu_clk = clk_get(NULL, "armclk");
173 return PTR_ERR(cpu_clk);
175 moutcore = clk_get(NULL, "moutcore");
176 if (IS_ERR(moutcore))
179 mout_mpll = clk_get(NULL, "mout_mpll");
180 if (IS_ERR(mout_mpll))
183 rate = clk_get_rate(mout_mpll) / 1000;
185 mout_apll = clk_get(NULL, "mout_apll");
186 if (IS_ERR(mout_apll))
189 info->mpll_freq_khz = rate;
191 info->pll_safe_idx = L2;
192 info->cpu_clk = cpu_clk;
193 info->volt_table = exynos4210_volt_table;
194 info->freq_table = exynos4210_freq_table;
195 info->set_freq = exynos4210_set_frequency;
196 info->need_apll_change = exynos4210_pms_change;
207 pr_debug("%s: failed initialization\n", __func__);
210 EXPORT_SYMBOL(exynos4210_cpufreq_init);