2 * Copyright (c) 2010-20122Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS5250 - CPU frequency scaling support
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/err.h>
15 #include <linux/clk.h>
17 #include <linux/slab.h>
18 #include <linux/cpufreq.h>
22 #include "exynos-cpufreq.h"
24 static struct clk *cpu_clk;
25 static struct clk *moutcore;
26 static struct clk *mout_mpll;
27 static struct clk *mout_apll;
29 static unsigned int exynos5250_volt_table[] = {
30 1300000, 1250000, 1225000, 1200000, 1150000,
31 1125000, 1100000, 1075000, 1050000, 1025000,
32 1012500, 1000000, 975000, 950000, 937500,
36 static struct cpufreq_frequency_table exynos5250_freq_table[] = {
53 {0, CPUFREQ_TABLE_END},
56 static struct apll_freq apll_freq_5250[] = {
60 * clock divider for ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2
61 * clock divider for COPY, HPM, RESERVED
64 APLL_FREQ(1700, 0, 3, 7, 7, 7, 3, 5, 0, 0, 2, 0, 425, 6, 0),
65 APLL_FREQ(1600, 0, 3, 7, 7, 7, 1, 4, 0, 0, 2, 0, 200, 3, 0),
66 APLL_FREQ(1500, 0, 2, 7, 7, 7, 1, 4, 0, 0, 2, 0, 250, 4, 0),
67 APLL_FREQ(1400, 0, 2, 7, 7, 6, 1, 4, 0, 0, 2, 0, 175, 3, 0),
68 APLL_FREQ(1300, 0, 2, 7, 7, 6, 1, 3, 0, 0, 2, 0, 325, 6, 0),
69 APLL_FREQ(1200, 0, 2, 7, 7, 5, 1, 3, 0, 0, 2, 0, 200, 4, 0),
70 APLL_FREQ(1100, 0, 3, 7, 7, 5, 1, 3, 0, 0, 2, 0, 275, 6, 0),
71 APLL_FREQ(1000, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 125, 3, 0),
72 APLL_FREQ(900, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 150, 4, 0),
73 APLL_FREQ(800, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 100, 3, 0),
74 APLL_FREQ(700, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 175, 3, 1),
75 APLL_FREQ(600, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 200, 4, 1),
76 APLL_FREQ(500, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 125, 3, 1),
77 APLL_FREQ(400, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 100, 3, 1),
78 APLL_FREQ(300, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 200, 4, 2),
79 APLL_FREQ(200, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 100, 3, 2),
82 static void set_clkdiv(unsigned int div_index)
86 /* Change Divider - CPU0 */
88 tmp = apll_freq_5250[div_index].clk_div_cpu0;
90 __raw_writel(tmp, EXYNOS5_CLKDIV_CPU0);
92 while (__raw_readl(EXYNOS5_CLKDIV_STATCPU0) & 0x11111111)
95 /* Change Divider - CPU1 */
96 tmp = apll_freq_5250[div_index].clk_div_cpu1;
98 __raw_writel(tmp, EXYNOS5_CLKDIV_CPU1);
100 while (__raw_readl(EXYNOS5_CLKDIV_STATCPU1) & 0x11)
104 static void set_apll(unsigned int index)
107 unsigned int freq = apll_freq_5250[index].freq;
109 /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
110 clk_set_parent(moutcore, mout_mpll);
114 tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU) >> 16);
116 } while (tmp != 0x2);
118 clk_set_rate(mout_apll, freq * 1000);
120 /* MUX_CORE_SEL = APLL */
121 clk_set_parent(moutcore, mout_apll);
125 tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU);
127 } while (tmp != (0x1 << 16));
130 static void exynos5250_set_frequency(unsigned int old_index,
131 unsigned int new_index)
133 if (old_index > new_index) {
134 set_clkdiv(new_index);
136 } else if (old_index < new_index) {
138 set_clkdiv(new_index);
142 int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
146 cpu_clk = clk_get(NULL, "armclk");
148 return PTR_ERR(cpu_clk);
150 moutcore = clk_get(NULL, "mout_cpu");
151 if (IS_ERR(moutcore))
154 mout_mpll = clk_get(NULL, "mout_mpll");
155 if (IS_ERR(mout_mpll))
158 rate = clk_get_rate(mout_mpll) / 1000;
160 mout_apll = clk_get(NULL, "mout_apll");
161 if (IS_ERR(mout_apll))
164 info->mpll_freq_khz = rate;
166 info->pll_safe_idx = L9;
167 info->cpu_clk = cpu_clk;
168 info->volt_table = exynos5250_volt_table;
169 info->freq_table = exynos5250_freq_table;
170 info->set_freq = exynos5250_set_frequency;
181 pr_err("%s: failed initialization\n", __func__);