2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/cpu.h>
11 #include <linux/cpufreq.h>
12 #include <linux/delay.h>
13 #include <linux/err.h>
14 #include <linux/module.h>
16 #include <linux/opp.h>
17 #include <linux/platform_device.h>
18 #include <linux/regulator/consumer.h>
20 #define PU_SOC_VOLTAGE_NORMAL 1250000
21 #define PU_SOC_VOLTAGE_HIGH 1275000
22 #define FREQ_1P2_GHZ 1200000000
24 static struct regulator *arm_reg;
25 static struct regulator *pu_reg;
26 static struct regulator *soc_reg;
28 static struct clk *arm_clk;
29 static struct clk *pll1_sys_clk;
30 static struct clk *pll1_sw_clk;
31 static struct clk *step_clk;
32 static struct clk *pll2_pfd2_396m_clk;
34 static struct device *cpu_dev;
35 static struct cpufreq_frequency_table *freq_table;
36 static unsigned int transition_latency;
38 static int imx6q_verify_speed(struct cpufreq_policy *policy)
40 return cpufreq_frequency_table_verify(policy, freq_table);
43 static unsigned int imx6q_get_speed(unsigned int cpu)
45 return clk_get_rate(arm_clk) / 1000;
48 static int imx6q_set_target(struct cpufreq_policy *policy,
49 unsigned int target_freq, unsigned int relation)
51 struct cpufreq_freqs freqs;
53 unsigned long freq_hz, volt, volt_old;
57 ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
60 dev_err(cpu_dev, "failed to match target frequency %d: %d\n",
65 freqs.new = freq_table[index].frequency;
66 freq_hz = freqs.new * 1000;
67 freqs.old = clk_get_rate(arm_clk) / 1000;
69 if (freqs.old == freqs.new)
73 opp = opp_find_freq_ceil(cpu_dev, &freq_hz);
76 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
80 volt = opp_get_voltage(opp);
82 volt_old = regulator_get_voltage(arm_reg);
84 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
85 freqs.old / 1000, volt_old / 1000,
86 freqs.new / 1000, volt / 1000);
88 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
90 /* scaling up? scale voltage before frequency */
91 if (freqs.new > freqs.old) {
92 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
95 "failed to scale vddarm up: %d\n", ret);
96 freqs.new = freqs.old;
101 * Need to increase vddpu and vddsoc for safety
102 * if we are about to run at 1.2 GHz.
104 if (freqs.new == FREQ_1P2_GHZ / 1000) {
105 regulator_set_voltage_tol(pu_reg,
106 PU_SOC_VOLTAGE_HIGH, 0);
107 regulator_set_voltage_tol(soc_reg,
108 PU_SOC_VOLTAGE_HIGH, 0);
113 * The setpoints are selected per PLL/PDF frequencies, so we need to
114 * reprogram PLL for frequency scaling. The procedure of reprogramming
117 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
118 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
119 * - Disable pll2_pfd2_396m_clk
121 clk_set_parent(step_clk, pll2_pfd2_396m_clk);
122 clk_set_parent(pll1_sw_clk, step_clk);
123 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
124 clk_set_rate(pll1_sys_clk, freqs.new * 1000);
125 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
128 /* Ensure the arm clock divider is what we expect */
129 ret = clk_set_rate(arm_clk, freqs.new * 1000);
131 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
132 regulator_set_voltage_tol(arm_reg, volt_old, 0);
133 freqs.new = freqs.old;
137 /* scaling down? scale voltage after frequency */
138 if (freqs.new < freqs.old) {
139 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
142 "failed to scale vddarm down: %d\n", ret);
146 if (freqs.old == FREQ_1P2_GHZ / 1000) {
147 regulator_set_voltage_tol(pu_reg,
148 PU_SOC_VOLTAGE_NORMAL, 0);
149 regulator_set_voltage_tol(soc_reg,
150 PU_SOC_VOLTAGE_NORMAL, 0);
155 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
160 static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
164 ret = cpufreq_frequency_table_cpuinfo(policy, freq_table);
166 dev_err(cpu_dev, "invalid frequency table: %d\n", ret);
170 policy->cpuinfo.transition_latency = transition_latency;
171 policy->cur = clk_get_rate(arm_clk) / 1000;
172 cpumask_setall(policy->cpus);
173 cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
178 static int imx6q_cpufreq_exit(struct cpufreq_policy *policy)
180 cpufreq_frequency_table_put_attr(policy->cpu);
184 static struct freq_attr *imx6q_cpufreq_attr[] = {
185 &cpufreq_freq_attr_scaling_available_freqs,
189 static struct cpufreq_driver imx6q_cpufreq_driver = {
190 .verify = imx6q_verify_speed,
191 .target = imx6q_set_target,
192 .get = imx6q_get_speed,
193 .init = imx6q_cpufreq_init,
194 .exit = imx6q_cpufreq_exit,
195 .name = "imx6q-cpufreq",
196 .attr = imx6q_cpufreq_attr,
199 static int imx6q_cpufreq_probe(struct platform_device *pdev)
201 struct device_node *np;
203 unsigned long min_volt, max_volt;
206 cpu_dev = get_cpu_device(0);
208 pr_err("failed to get cpu0 device\n");
212 np = of_node_get(cpu_dev->of_node);
214 dev_err(cpu_dev, "failed to find cpu0 node\n");
218 arm_clk = devm_clk_get(cpu_dev, "arm");
219 pll1_sys_clk = devm_clk_get(cpu_dev, "pll1_sys");
220 pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw");
221 step_clk = devm_clk_get(cpu_dev, "step");
222 pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m");
223 if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
224 IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
225 dev_err(cpu_dev, "failed to get clocks\n");
230 arm_reg = devm_regulator_get(cpu_dev, "arm");
231 pu_reg = devm_regulator_get(cpu_dev, "pu");
232 soc_reg = devm_regulator_get(cpu_dev, "soc");
233 if (IS_ERR(arm_reg) || IS_ERR(pu_reg) || IS_ERR(soc_reg)) {
234 dev_err(cpu_dev, "failed to get regulators\n");
239 /* We expect an OPP table supplied by platform */
240 num = opp_get_opp_count(cpu_dev);
243 dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
247 ret = opp_init_cpufreq_table(cpu_dev, &freq_table);
249 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
253 if (of_property_read_u32(np, "clock-latency", &transition_latency))
254 transition_latency = CPUFREQ_ETERNAL;
257 * OPP is maintained in order of increasing frequency, and
258 * freq_table initialised from OPP is therefore sorted in the
262 opp = opp_find_freq_exact(cpu_dev,
263 freq_table[0].frequency * 1000, true);
264 min_volt = opp_get_voltage(opp);
265 opp = opp_find_freq_exact(cpu_dev,
266 freq_table[--num].frequency * 1000, true);
267 max_volt = opp_get_voltage(opp);
269 ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
271 transition_latency += ret * 1000;
273 /* Count vddpu and vddsoc latency in for 1.2 GHz support */
274 if (freq_table[num].frequency == FREQ_1P2_GHZ / 1000) {
275 ret = regulator_set_voltage_time(pu_reg, PU_SOC_VOLTAGE_NORMAL,
276 PU_SOC_VOLTAGE_HIGH);
278 transition_latency += ret * 1000;
279 ret = regulator_set_voltage_time(soc_reg, PU_SOC_VOLTAGE_NORMAL,
280 PU_SOC_VOLTAGE_HIGH);
282 transition_latency += ret * 1000;
285 ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
287 dev_err(cpu_dev, "failed register driver: %d\n", ret);
288 goto free_freq_table;
295 opp_free_cpufreq_table(cpu_dev, &freq_table);
301 static int imx6q_cpufreq_remove(struct platform_device *pdev)
303 cpufreq_unregister_driver(&imx6q_cpufreq_driver);
304 opp_free_cpufreq_table(cpu_dev, &freq_table);
309 static struct platform_driver imx6q_cpufreq_platdrv = {
311 .name = "imx6q-cpufreq",
312 .owner = THIS_MODULE,
314 .probe = imx6q_cpufreq_probe,
315 .remove = imx6q_cpufreq_remove,
317 module_platform_driver(imx6q_cpufreq_platdrv);
319 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
320 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
321 MODULE_LICENSE("GPL");