2 * intel_pstate.c: Native P state management for Intel processors
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #include <linux/kernel.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/module.h>
16 #include <linux/ktime.h>
17 #include <linux/hrtimer.h>
18 #include <linux/tick.h>
19 #include <linux/slab.h>
20 #include <linux/sched.h>
21 #include <linux/list.h>
22 #include <linux/cpu.h>
23 #include <linux/cpufreq.h>
24 #include <linux/sysfs.h>
25 #include <linux/types.h>
27 #include <linux/debugfs.h>
28 #include <linux/acpi.h>
29 #include <trace/events/power.h>
31 #include <asm/div64.h>
33 #include <asm/cpu_device_id.h>
35 #define BYT_RATIOS 0x66a
36 #define BYT_VIDS 0x66b
37 #define BYT_TURBO_RATIOS 0x66c
38 #define BYT_TURBO_VIDS 0x66d
41 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
42 #define fp_toint(X) ((X) >> FRAC_BITS)
45 static inline int32_t mul_fp(int32_t x, int32_t y)
47 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
50 static inline int32_t div_fp(int32_t x, int32_t y)
52 return div_s64((int64_t)x << FRAC_BITS, y);
55 static inline int ceiling_fp(int32_t x)
60 mask = (1 << FRAC_BITS) - 1;
67 int32_t core_pct_busy;
102 struct timer_list timer;
104 struct pstate_data pstate;
108 ktime_t last_sample_time;
111 struct sample sample;
114 static struct cpudata **all_cpu_data;
115 struct pstate_adjust_policy {
124 struct pstate_funcs {
125 int (*get_max)(void);
126 int (*get_min)(void);
127 int (*get_turbo)(void);
128 int (*get_scaling)(void);
129 void (*set)(struct cpudata*, int pstate);
130 void (*get_vid)(struct cpudata *);
133 struct cpu_defaults {
134 struct pstate_adjust_policy pid_policy;
135 struct pstate_funcs funcs;
138 static struct pstate_adjust_policy pid_params;
139 static struct pstate_funcs pstate_funcs;
140 static int hwp_active;
155 static struct perf_limits limits = {
159 .max_perf = int_tofp(1),
162 .max_policy_pct = 100,
163 .max_sysfs_pct = 100,
168 static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
169 int deadband, int integral) {
170 pid->setpoint = setpoint;
171 pid->deadband = deadband;
172 pid->integral = int_tofp(integral);
173 pid->last_err = int_tofp(setpoint) - int_tofp(busy);
176 static inline void pid_p_gain_set(struct _pid *pid, int percent)
178 pid->p_gain = div_fp(int_tofp(percent), int_tofp(100));
181 static inline void pid_i_gain_set(struct _pid *pid, int percent)
183 pid->i_gain = div_fp(int_tofp(percent), int_tofp(100));
186 static inline void pid_d_gain_set(struct _pid *pid, int percent)
188 pid->d_gain = div_fp(int_tofp(percent), int_tofp(100));
191 static signed int pid_calc(struct _pid *pid, int32_t busy)
194 int32_t pterm, dterm, fp_error;
195 int32_t integral_limit;
197 fp_error = int_tofp(pid->setpoint) - busy;
199 if (abs(fp_error) <= int_tofp(pid->deadband))
202 pterm = mul_fp(pid->p_gain, fp_error);
204 pid->integral += fp_error;
207 * We limit the integral here so that it will never
208 * get higher than 30. This prevents it from becoming
209 * too large an input over long periods of time and allows
210 * it to get factored out sooner.
212 * The value of 30 was chosen through experimentation.
214 integral_limit = int_tofp(30);
215 if (pid->integral > integral_limit)
216 pid->integral = integral_limit;
217 if (pid->integral < -integral_limit)
218 pid->integral = -integral_limit;
220 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
221 pid->last_err = fp_error;
223 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
224 result = result + (1 << (FRAC_BITS-1));
225 return (signed int)fp_toint(result);
228 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
230 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
231 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
232 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
234 pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
237 static inline void intel_pstate_reset_all_pid(void)
241 for_each_online_cpu(cpu) {
242 if (all_cpu_data[cpu])
243 intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
247 static inline void update_turbo_state(void)
252 cpu = all_cpu_data[0];
253 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
254 limits.turbo_disabled =
255 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
256 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
259 #define PCT_TO_HWP(x) (x * 255 / 100)
260 static void intel_pstate_hwp_set(void)
267 for_each_online_cpu(cpu) {
268 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
269 min = PCT_TO_HWP(limits.min_perf_pct);
270 value &= ~HWP_MIN_PERF(~0L);
271 value |= HWP_MIN_PERF(min);
273 max = PCT_TO_HWP(limits.max_perf_pct);
274 if (limits.no_turbo) {
275 rdmsrl( MSR_HWP_CAPABILITIES, freq);
276 max = HWP_GUARANTEED_PERF(freq);
279 value &= ~HWP_MAX_PERF(~0L);
280 value |= HWP_MAX_PERF(max);
281 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
287 /************************** debugfs begin ************************/
288 static int pid_param_set(void *data, u64 val)
291 intel_pstate_reset_all_pid();
295 static int pid_param_get(void *data, u64 *val)
300 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
307 static struct pid_param pid_files[] = {
308 {"sample_rate_ms", &pid_params.sample_rate_ms},
309 {"d_gain_pct", &pid_params.d_gain_pct},
310 {"i_gain_pct", &pid_params.i_gain_pct},
311 {"deadband", &pid_params.deadband},
312 {"setpoint", &pid_params.setpoint},
313 {"p_gain_pct", &pid_params.p_gain_pct},
317 static void __init intel_pstate_debug_expose_params(void)
319 struct dentry *debugfs_parent;
324 debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
325 if (IS_ERR_OR_NULL(debugfs_parent))
327 while (pid_files[i].name) {
328 debugfs_create_file(pid_files[i].name, 0660,
329 debugfs_parent, pid_files[i].value,
335 /************************** debugfs end ************************/
337 /************************** sysfs begin ************************/
338 #define show_one(file_name, object) \
339 static ssize_t show_##file_name \
340 (struct kobject *kobj, struct attribute *attr, char *buf) \
342 return sprintf(buf, "%u\n", limits.object); \
345 static ssize_t show_turbo_pct(struct kobject *kobj,
346 struct attribute *attr, char *buf)
349 int total, no_turbo, turbo_pct;
352 cpu = all_cpu_data[0];
354 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
355 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
356 turbo_fp = div_fp(int_tofp(no_turbo), int_tofp(total));
357 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
358 return sprintf(buf, "%u\n", turbo_pct);
361 static ssize_t show_num_pstates(struct kobject *kobj,
362 struct attribute *attr, char *buf)
367 cpu = all_cpu_data[0];
368 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
369 return sprintf(buf, "%u\n", total);
372 static ssize_t show_no_turbo(struct kobject *kobj,
373 struct attribute *attr, char *buf)
377 update_turbo_state();
378 if (limits.turbo_disabled)
379 ret = sprintf(buf, "%u\n", limits.turbo_disabled);
381 ret = sprintf(buf, "%u\n", limits.no_turbo);
386 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
387 const char *buf, size_t count)
392 ret = sscanf(buf, "%u", &input);
396 update_turbo_state();
397 if (limits.turbo_disabled) {
398 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
402 limits.no_turbo = clamp_t(int, input, 0, 1);
405 intel_pstate_hwp_set();
410 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
411 const char *buf, size_t count)
416 ret = sscanf(buf, "%u", &input);
420 limits.max_sysfs_pct = clamp_t(int, input, 0 , 100);
421 limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct);
422 limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100));
425 intel_pstate_hwp_set();
429 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
430 const char *buf, size_t count)
435 ret = sscanf(buf, "%u", &input);
439 limits.min_sysfs_pct = clamp_t(int, input, 0 , 100);
440 limits.min_perf_pct = max(limits.min_policy_pct, limits.min_sysfs_pct);
441 limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100));
444 intel_pstate_hwp_set();
448 show_one(max_perf_pct, max_perf_pct);
449 show_one(min_perf_pct, min_perf_pct);
451 define_one_global_rw(no_turbo);
452 define_one_global_rw(max_perf_pct);
453 define_one_global_rw(min_perf_pct);
454 define_one_global_ro(turbo_pct);
455 define_one_global_ro(num_pstates);
457 static struct attribute *intel_pstate_attributes[] = {
466 static struct attribute_group intel_pstate_attr_group = {
467 .attrs = intel_pstate_attributes,
470 static void __init intel_pstate_sysfs_expose_params(void)
472 struct kobject *intel_pstate_kobject;
475 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
476 &cpu_subsys.dev_root->kobj);
477 BUG_ON(!intel_pstate_kobject);
478 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
481 /************************** sysfs end ************************/
483 static void intel_pstate_hwp_enable(void)
486 pr_info("intel_pstate HWP enabled\n");
488 wrmsrl( MSR_PM_ENABLE, 0x1);
491 static int byt_get_min_pstate(void)
495 rdmsrl(BYT_RATIOS, value);
496 return (value >> 8) & 0x7F;
499 static int byt_get_max_pstate(void)
503 rdmsrl(BYT_RATIOS, value);
504 return (value >> 16) & 0x7F;
507 static int byt_get_turbo_pstate(void)
511 rdmsrl(BYT_TURBO_RATIOS, value);
515 static void byt_set_pstate(struct cpudata *cpudata, int pstate)
522 if (limits.no_turbo && !limits.turbo_disabled)
525 vid_fp = cpudata->vid.min + mul_fp(
526 int_tofp(pstate - cpudata->pstate.min_pstate),
529 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
530 vid = ceiling_fp(vid_fp);
532 if (pstate > cpudata->pstate.max_pstate)
533 vid = cpudata->vid.turbo;
537 wrmsrl(MSR_IA32_PERF_CTL, val);
540 #define BYT_BCLK_FREQS 5
541 static int byt_freq_table[BYT_BCLK_FREQS] = { 833, 1000, 1333, 1167, 800};
543 static int byt_get_scaling(void)
548 rdmsrl(MSR_FSB_FREQ, value);
551 BUG_ON(i > BYT_BCLK_FREQS);
553 return byt_freq_table[i] * 100;
556 static void byt_get_vid(struct cpudata *cpudata)
560 rdmsrl(BYT_VIDS, value);
561 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
562 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
563 cpudata->vid.ratio = div_fp(
564 cpudata->vid.max - cpudata->vid.min,
565 int_tofp(cpudata->pstate.max_pstate -
566 cpudata->pstate.min_pstate));
568 rdmsrl(BYT_TURBO_VIDS, value);
569 cpudata->vid.turbo = value & 0x7f;
572 static int core_get_min_pstate(void)
576 rdmsrl(MSR_PLATFORM_INFO, value);
577 return (value >> 40) & 0xFF;
580 static int core_get_max_pstate(void)
584 rdmsrl(MSR_PLATFORM_INFO, value);
585 return (value >> 8) & 0xFF;
588 static int core_get_turbo_pstate(void)
593 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value);
594 nont = core_get_max_pstate();
601 static inline int core_get_scaling(void)
606 static void core_set_pstate(struct cpudata *cpudata, int pstate)
611 if (limits.no_turbo && !limits.turbo_disabled)
614 wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val);
617 static struct cpu_defaults core_params = {
619 .sample_rate_ms = 10,
627 .get_max = core_get_max_pstate,
628 .get_min = core_get_min_pstate,
629 .get_turbo = core_get_turbo_pstate,
630 .get_scaling = core_get_scaling,
631 .set = core_set_pstate,
635 static struct cpu_defaults byt_params = {
637 .sample_rate_ms = 10,
645 .get_max = byt_get_max_pstate,
646 .get_min = byt_get_min_pstate,
647 .get_turbo = byt_get_turbo_pstate,
648 .set = byt_set_pstate,
649 .get_scaling = byt_get_scaling,
650 .get_vid = byt_get_vid,
654 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
656 int max_perf = cpu->pstate.turbo_pstate;
660 if (limits.no_turbo || limits.turbo_disabled)
661 max_perf = cpu->pstate.max_pstate;
664 * performance can be limited by user through sysfs, by cpufreq
665 * policy, or by cpu specific default values determined through
668 max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf));
669 *max = clamp_t(int, max_perf_adj,
670 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
672 min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.min_perf));
673 *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
676 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
678 int max_perf, min_perf;
680 update_turbo_state();
682 intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
684 pstate = clamp_t(int, pstate, min_perf, max_perf);
686 if (pstate == cpu->pstate.current_pstate)
689 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
691 cpu->pstate.current_pstate = pstate;
693 pstate_funcs.set(cpu, pstate);
696 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
698 cpu->pstate.min_pstate = pstate_funcs.get_min();
699 cpu->pstate.max_pstate = pstate_funcs.get_max();
700 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
701 cpu->pstate.scaling = pstate_funcs.get_scaling();
703 if (pstate_funcs.get_vid)
704 pstate_funcs.get_vid(cpu);
705 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
708 static inline void intel_pstate_calc_busy(struct cpudata *cpu)
710 struct sample *sample = &cpu->sample;
713 core_pct = int_tofp(sample->aperf) * int_tofp(100);
714 core_pct = div64_u64(core_pct, int_tofp(sample->mperf));
716 sample->freq = fp_toint(
718 cpu->pstate.max_pstate * cpu->pstate.scaling / 100),
721 sample->core_pct_busy = (int32_t)core_pct;
724 static inline void intel_pstate_sample(struct cpudata *cpu)
729 local_irq_save(flags);
730 rdmsrl(MSR_IA32_APERF, aperf);
731 rdmsrl(MSR_IA32_MPERF, mperf);
732 local_irq_restore(flags);
734 cpu->last_sample_time = cpu->sample.time;
735 cpu->sample.time = ktime_get();
736 cpu->sample.aperf = aperf;
737 cpu->sample.mperf = mperf;
738 cpu->sample.aperf -= cpu->prev_aperf;
739 cpu->sample.mperf -= cpu->prev_mperf;
741 intel_pstate_calc_busy(cpu);
743 cpu->prev_aperf = aperf;
744 cpu->prev_mperf = mperf;
747 static inline void intel_hwp_set_sample_time(struct cpudata *cpu)
751 delay = msecs_to_jiffies(50);
752 mod_timer_pinned(&cpu->timer, jiffies + delay);
755 static inline void intel_pstate_set_sample_time(struct cpudata *cpu)
759 delay = msecs_to_jiffies(pid_params.sample_rate_ms);
760 mod_timer_pinned(&cpu->timer, jiffies + delay);
763 static inline int32_t intel_pstate_get_scaled_busy(struct cpudata *cpu)
765 int32_t core_busy, max_pstate, current_pstate, sample_ratio;
770 * core_busy is the ratio of actual performance to max
771 * max_pstate is the max non turbo pstate available
772 * current_pstate was the pstate that was requested during
773 * the last sample period.
775 * We normalize core_busy, which was our actual percent
776 * performance to what we requested during the last sample
777 * period. The result will be a percentage of busy at a
780 core_busy = cpu->sample.core_pct_busy;
781 max_pstate = int_tofp(cpu->pstate.max_pstate);
782 current_pstate = int_tofp(cpu->pstate.current_pstate);
783 core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate));
786 * Since we have a deferred timer, it will not fire unless
787 * we are in C0. So, determine if the actual elapsed time
788 * is significantly greater (3x) than our sample interval. If it
789 * is, then we were idle for a long enough period of time
790 * to adjust our busyness.
792 sample_time = pid_params.sample_rate_ms * USEC_PER_MSEC;
793 duration_us = (u32) ktime_us_delta(cpu->sample.time,
794 cpu->last_sample_time);
795 if (duration_us > sample_time * 3) {
796 sample_ratio = div_fp(int_tofp(sample_time),
797 int_tofp(duration_us));
798 core_busy = mul_fp(core_busy, sample_ratio);
804 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
811 busy_scaled = intel_pstate_get_scaled_busy(cpu);
813 ctl = pid_calc(pid, busy_scaled);
815 /* Negative values of ctl increase the pstate and vice versa */
816 intel_pstate_set_pstate(cpu, cpu->pstate.current_pstate - ctl);
819 static void intel_hwp_timer_func(unsigned long __data)
821 struct cpudata *cpu = (struct cpudata *) __data;
823 intel_pstate_sample(cpu);
824 intel_hwp_set_sample_time(cpu);
827 static void intel_pstate_timer_func(unsigned long __data)
829 struct cpudata *cpu = (struct cpudata *) __data;
830 struct sample *sample;
832 intel_pstate_sample(cpu);
834 sample = &cpu->sample;
836 intel_pstate_adjust_busy_pstate(cpu);
838 trace_pstate_sample(fp_toint(sample->core_pct_busy),
839 fp_toint(intel_pstate_get_scaled_busy(cpu)),
840 cpu->pstate.current_pstate,
845 intel_pstate_set_sample_time(cpu);
848 #define ICPU(model, policy) \
849 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
850 (unsigned long)&policy }
852 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
853 ICPU(0x2a, core_params),
854 ICPU(0x2d, core_params),
855 ICPU(0x37, byt_params),
856 ICPU(0x3a, core_params),
857 ICPU(0x3c, core_params),
858 ICPU(0x3d, core_params),
859 ICPU(0x3e, core_params),
860 ICPU(0x3f, core_params),
861 ICPU(0x45, core_params),
862 ICPU(0x46, core_params),
863 ICPU(0x47, core_params),
864 ICPU(0x4c, byt_params),
865 ICPU(0x4e, core_params),
866 ICPU(0x4f, core_params),
867 ICPU(0x56, core_params),
870 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
872 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] = {
873 ICPU(0x56, core_params),
877 static int intel_pstate_init_cpu(unsigned int cpunum)
881 if (!all_cpu_data[cpunum])
882 all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata),
884 if (!all_cpu_data[cpunum])
887 cpu = all_cpu_data[cpunum];
890 intel_pstate_get_cpu_pstates(cpu);
892 init_timer_deferrable(&cpu->timer);
893 cpu->timer.data = (unsigned long)cpu;
894 cpu->timer.expires = jiffies + HZ/100;
897 cpu->timer.function = intel_pstate_timer_func;
899 cpu->timer.function = intel_hwp_timer_func;
901 intel_pstate_busy_pid_reset(cpu);
902 intel_pstate_sample(cpu);
904 add_timer_on(&cpu->timer, cpunum);
906 pr_debug("Intel pstate controlling: cpu %d\n", cpunum);
911 static unsigned int intel_pstate_get(unsigned int cpu_num)
913 struct sample *sample;
916 cpu = all_cpu_data[cpu_num];
919 sample = &cpu->sample;
923 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
925 if (!policy->cpuinfo.max_freq)
928 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE &&
929 policy->max >= policy->cpuinfo.max_freq) {
930 limits.min_policy_pct = 100;
931 limits.min_perf_pct = 100;
932 limits.min_perf = int_tofp(1);
933 limits.max_policy_pct = 100;
934 limits.max_perf_pct = 100;
935 limits.max_perf = int_tofp(1);
940 limits.min_policy_pct = (policy->min * 100) / policy->cpuinfo.max_freq;
941 limits.min_policy_pct = clamp_t(int, limits.min_policy_pct, 0 , 100);
942 limits.min_perf_pct = max(limits.min_policy_pct, limits.min_sysfs_pct);
943 limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100));
945 limits.max_policy_pct = (policy->max * 100) / policy->cpuinfo.max_freq;
946 limits.max_policy_pct = clamp_t(int, limits.max_policy_pct, 0 , 100);
947 limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct);
948 limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100));
951 intel_pstate_hwp_set();
956 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
958 cpufreq_verify_within_cpu_limits(policy);
960 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
961 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
967 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
969 int cpu_num = policy->cpu;
970 struct cpudata *cpu = all_cpu_data[cpu_num];
972 pr_info("intel_pstate CPU %d exiting\n", cpu_num);
974 del_timer_sync(&all_cpu_data[cpu_num]->timer);
978 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
981 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
986 rc = intel_pstate_init_cpu(policy->cpu);
990 cpu = all_cpu_data[policy->cpu];
992 if (limits.min_perf_pct == 100 && limits.max_perf_pct == 100)
993 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
995 policy->policy = CPUFREQ_POLICY_POWERSAVE;
997 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
998 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1000 /* cpuinfo and default policy values */
1001 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
1002 policy->cpuinfo.max_freq =
1003 cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1004 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
1005 cpumask_set_cpu(policy->cpu, policy->cpus);
1010 static struct cpufreq_driver intel_pstate_driver = {
1011 .flags = CPUFREQ_CONST_LOOPS,
1012 .verify = intel_pstate_verify_policy,
1013 .setpolicy = intel_pstate_set_policy,
1014 .get = intel_pstate_get,
1015 .init = intel_pstate_cpu_init,
1016 .stop_cpu = intel_pstate_stop_cpu,
1017 .name = "intel_pstate",
1020 static int __initdata no_load;
1021 static int __initdata no_hwp;
1022 static int __initdata hwp_only;
1023 static unsigned int force_load;
1025 static int intel_pstate_msrs_not_valid(void)
1027 /* Check that all the msr's we are using are valid. */
1028 u64 aperf, mperf, tmp;
1030 rdmsrl(MSR_IA32_APERF, aperf);
1031 rdmsrl(MSR_IA32_MPERF, mperf);
1033 if (!pstate_funcs.get_max() ||
1034 !pstate_funcs.get_min() ||
1035 !pstate_funcs.get_turbo())
1038 rdmsrl(MSR_IA32_APERF, tmp);
1042 rdmsrl(MSR_IA32_MPERF, tmp);
1049 static void copy_pid_params(struct pstate_adjust_policy *policy)
1051 pid_params.sample_rate_ms = policy->sample_rate_ms;
1052 pid_params.p_gain_pct = policy->p_gain_pct;
1053 pid_params.i_gain_pct = policy->i_gain_pct;
1054 pid_params.d_gain_pct = policy->d_gain_pct;
1055 pid_params.deadband = policy->deadband;
1056 pid_params.setpoint = policy->setpoint;
1059 static void copy_cpu_funcs(struct pstate_funcs *funcs)
1061 pstate_funcs.get_max = funcs->get_max;
1062 pstate_funcs.get_min = funcs->get_min;
1063 pstate_funcs.get_turbo = funcs->get_turbo;
1064 pstate_funcs.get_scaling = funcs->get_scaling;
1065 pstate_funcs.set = funcs->set;
1066 pstate_funcs.get_vid = funcs->get_vid;
1069 #if IS_ENABLED(CONFIG_ACPI)
1070 #include <acpi/processor.h>
1072 static bool intel_pstate_no_acpi_pss(void)
1076 for_each_possible_cpu(i) {
1078 union acpi_object *pss;
1079 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1080 struct acpi_processor *pr = per_cpu(processors, i);
1085 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
1086 if (ACPI_FAILURE(status))
1089 pss = buffer.pointer;
1090 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
1101 static bool intel_pstate_has_acpi_ppc(void)
1105 for_each_possible_cpu(i) {
1106 struct acpi_processor *pr = per_cpu(processors, i);
1110 if (acpi_has_method(pr->handle, "_PPC"))
1121 struct hw_vendor_info {
1123 char oem_id[ACPI_OEM_ID_SIZE];
1124 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
1128 /* Hardware vendor-specific info that has its own power management modes */
1129 static struct hw_vendor_info vendor_info[] = {
1130 {1, "HP ", "ProLiant", PSS},
1131 {1, "ORACLE", "X4-2 ", PPC},
1132 {1, "ORACLE", "X4-2L ", PPC},
1133 {1, "ORACLE", "X4-2B ", PPC},
1134 {1, "ORACLE", "X3-2 ", PPC},
1135 {1, "ORACLE", "X3-2L ", PPC},
1136 {1, "ORACLE", "X3-2B ", PPC},
1137 {1, "ORACLE", "X4470M2 ", PPC},
1138 {1, "ORACLE", "X4270M3 ", PPC},
1139 {1, "ORACLE", "X4270M2 ", PPC},
1140 {1, "ORACLE", "X4170M2 ", PPC},
1144 static bool intel_pstate_platform_pwr_mgmt_exists(void)
1146 struct acpi_table_header hdr;
1147 struct hw_vendor_info *v_info;
1148 const struct x86_cpu_id *id;
1151 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
1153 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
1154 if ( misc_pwr & (1 << 8))
1158 if (acpi_disabled ||
1159 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
1162 for (v_info = vendor_info; v_info->valid; v_info++) {
1163 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
1164 !strncmp(hdr.oem_table_id, v_info->oem_table_id,
1165 ACPI_OEM_TABLE_ID_SIZE))
1166 switch (v_info->oem_pwr_table) {
1168 return intel_pstate_no_acpi_pss();
1170 return intel_pstate_has_acpi_ppc() &&
1177 #else /* CONFIG_ACPI not enabled */
1178 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
1179 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
1180 #endif /* CONFIG_ACPI */
1182 static int __init intel_pstate_init(void)
1185 const struct x86_cpu_id *id;
1186 struct cpu_defaults *cpu_info;
1187 struct cpuinfo_x86 *c = &boot_cpu_data;
1192 id = x86_match_cpu(intel_pstate_cpu_ids);
1197 * The Intel pstate driver will be ignored if the platform
1198 * firmware has its own power management modes.
1200 if (intel_pstate_platform_pwr_mgmt_exists())
1203 cpu_info = (struct cpu_defaults *)id->driver_data;
1205 copy_pid_params(&cpu_info->pid_policy);
1206 copy_cpu_funcs(&cpu_info->funcs);
1208 if (intel_pstate_msrs_not_valid())
1211 pr_info("Intel P-state driver initializing.\n");
1213 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
1217 if (cpu_has(c,X86_FEATURE_HWP) && !no_hwp)
1218 intel_pstate_hwp_enable();
1220 if (!hwp_active && hwp_only)
1223 rc = cpufreq_register_driver(&intel_pstate_driver);
1227 intel_pstate_debug_expose_params();
1228 intel_pstate_sysfs_expose_params();
1233 for_each_online_cpu(cpu) {
1234 if (all_cpu_data[cpu]) {
1235 del_timer_sync(&all_cpu_data[cpu]->timer);
1236 kfree(all_cpu_data[cpu]);
1241 vfree(all_cpu_data);
1244 device_initcall(intel_pstate_init);
1246 static int __init intel_pstate_setup(char *str)
1251 if (!strcmp(str, "disable"))
1253 if (!strcmp(str, "no_hwp"))
1255 if (!strcmp(str, "force"))
1257 if (!strcmp(str, "hwp_only"))
1261 early_param("intel_pstate", intel_pstate_setup);
1263 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
1264 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
1265 MODULE_LICENSE("GPL");