2 * Copyright (C) 2010 Google, Inc.
5 * Colin Cross <ccross@google.com>
6 * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/types.h>
22 #include <linux/sched.h>
23 #include <linux/cpufreq.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/err.h>
27 #include <linux/clk.h>
29 #include <linux/suspend.h>
31 static struct cpufreq_frequency_table freq_table[] = {
32 { .frequency = 216000 },
33 { .frequency = 312000 },
34 { .frequency = 456000 },
35 { .frequency = 608000 },
36 { .frequency = 760000 },
37 { .frequency = 816000 },
38 { .frequency = 912000 },
39 { .frequency = 1000000 },
40 { .frequency = CPUFREQ_TABLE_END },
45 static struct clk *cpu_clk;
46 static struct clk *pll_x_clk;
47 static struct clk *pll_p_clk;
48 static struct clk *emc_clk;
50 static unsigned long target_cpu_speed[NUM_CPUS];
51 static DEFINE_MUTEX(tegra_cpu_lock);
52 static bool is_suspended;
54 static unsigned int tegra_getspeed(unsigned int cpu)
61 rate = clk_get_rate(cpu_clk) / 1000;
65 static int tegra_cpu_clk_set_rate(unsigned long rate)
70 * Take an extra reference to the main pll so it doesn't turn
71 * off when we move the cpu off of it
73 clk_prepare_enable(pll_x_clk);
75 ret = clk_set_parent(cpu_clk, pll_p_clk);
77 pr_err("Failed to switch cpu to clock pll_p\n");
81 if (rate == clk_get_rate(pll_p_clk))
84 ret = clk_set_rate(pll_x_clk, rate);
86 pr_err("Failed to change pll_x to %lu\n", rate);
90 ret = clk_set_parent(cpu_clk, pll_x_clk);
92 pr_err("Failed to switch cpu to clock pll_x\n");
97 clk_disable_unprepare(pll_x_clk);
101 static int tegra_update_cpu_speed(struct cpufreq_policy *policy,
105 struct cpufreq_freqs freqs;
107 freqs.old = tegra_getspeed(0);
110 if (freqs.old == freqs.new)
114 * Vote on memory bus frequency based on cpu frequency
115 * This sets the minimum frequency, display or avp may request higher
118 clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
119 else if (rate >= 456000)
120 clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
122 clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */
124 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
126 #ifdef CONFIG_CPU_FREQ_DEBUG
127 printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n",
128 freqs.old, freqs.new);
131 ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
133 pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
135 freqs.new = freqs.old;
138 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
143 static unsigned long tegra_cpu_highest_speed(void)
145 unsigned long rate = 0;
148 for_each_online_cpu(i)
149 rate = max(rate, target_cpu_speed[i]);
153 static int tegra_target(struct cpufreq_policy *policy,
154 unsigned int target_freq,
155 unsigned int relation)
161 mutex_lock(&tegra_cpu_lock);
168 cpufreq_frequency_table_target(policy, freq_table, target_freq,
171 freq = freq_table[idx].frequency;
173 target_cpu_speed[policy->cpu] = freq;
175 ret = tegra_update_cpu_speed(policy, tegra_cpu_highest_speed());
178 mutex_unlock(&tegra_cpu_lock);
182 static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
185 mutex_lock(&tegra_cpu_lock);
186 if (event == PM_SUSPEND_PREPARE) {
187 struct cpufreq_policy *policy = cpufreq_cpu_get(0);
189 pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n",
190 freq_table[0].frequency);
191 tegra_update_cpu_speed(policy, freq_table[0].frequency);
192 cpufreq_cpu_put(policy);
193 } else if (event == PM_POST_SUSPEND) {
194 is_suspended = false;
196 mutex_unlock(&tegra_cpu_lock);
201 static struct notifier_block tegra_cpu_pm_notifier = {
202 .notifier_call = tegra_pm_notify,
205 static int tegra_cpu_init(struct cpufreq_policy *policy)
209 if (policy->cpu >= NUM_CPUS)
212 clk_prepare_enable(emc_clk);
213 clk_prepare_enable(cpu_clk);
215 target_cpu_speed[policy->cpu] = tegra_getspeed(policy->cpu);
217 /* FIXME: what's the actual transition time? */
218 ret = cpufreq_generic_init(policy, freq_table, 300 * 1000);
220 clk_disable_unprepare(cpu_clk);
221 clk_disable_unprepare(emc_clk);
225 if (policy->cpu == 0)
226 register_pm_notifier(&tegra_cpu_pm_notifier);
231 static int tegra_cpu_exit(struct cpufreq_policy *policy)
233 cpufreq_frequency_table_put_attr(policy->cpu);
234 clk_disable_unprepare(cpu_clk);
235 clk_disable_unprepare(emc_clk);
239 static struct cpufreq_driver tegra_cpufreq_driver = {
240 .verify = cpufreq_generic_frequency_table_verify,
241 .target = tegra_target,
242 .get = tegra_getspeed,
243 .init = tegra_cpu_init,
244 .exit = tegra_cpu_exit,
246 .attr = cpufreq_generic_attr,
249 static int __init tegra_cpufreq_init(void)
251 cpu_clk = clk_get_sys(NULL, "cclk");
253 return PTR_ERR(cpu_clk);
255 pll_x_clk = clk_get_sys(NULL, "pll_x");
256 if (IS_ERR(pll_x_clk))
257 return PTR_ERR(pll_x_clk);
259 pll_p_clk = clk_get_sys(NULL, "pll_p");
260 if (IS_ERR(pll_p_clk))
261 return PTR_ERR(pll_p_clk);
263 emc_clk = clk_get_sys("cpu", "emc");
264 if (IS_ERR(emc_clk)) {
266 return PTR_ERR(emc_clk);
269 return cpufreq_register_driver(&tegra_cpufreq_driver);
272 static void __exit tegra_cpufreq_exit(void)
274 cpufreq_unregister_driver(&tegra_cpufreq_driver);
280 MODULE_AUTHOR("Colin Cross <ccross@android.com>");
281 MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
282 MODULE_LICENSE("GPL");
283 module_init(tegra_cpufreq_init);
284 module_exit(tegra_cpufreq_exit);