2 * Copyright (C) 2010 Google, Inc.
5 * Colin Cross <ccross@google.com>
6 * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/types.h>
22 #include <linux/sched.h>
23 #include <linux/cpufreq.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/err.h>
27 #include <linux/clk.h>
30 static struct cpufreq_frequency_table freq_table[] = {
31 { .frequency = 216000 },
32 { .frequency = 312000 },
33 { .frequency = 456000 },
34 { .frequency = 608000 },
35 { .frequency = 760000 },
36 { .frequency = 816000 },
37 { .frequency = 912000 },
38 { .frequency = 1000000 },
39 { .frequency = CPUFREQ_TABLE_END },
44 static struct clk *cpu_clk;
45 static struct clk *pll_x_clk;
46 static struct clk *pll_p_clk;
47 static struct clk *emc_clk;
48 static bool pll_x_prepared;
50 static unsigned int tegra_get_intermediate(struct cpufreq_policy *policy,
53 unsigned int ifreq = clk_get_rate(pll_p_clk) / 1000;
56 * Don't switch to intermediate freq if:
57 * - we are already at it, i.e. policy->cur == ifreq
58 * - index corresponds to ifreq
60 if ((freq_table[index].frequency == ifreq) || (policy->cur == ifreq))
66 static int tegra_target_intermediate(struct cpufreq_policy *policy,
72 * Take an extra reference to the main pll so it doesn't turn
73 * off when we move the cpu off of it as enabling it again while we
74 * switch to it from tegra_target() would take additional time. Though
75 * when target-freq is intermediate freq, we don't need to take this
78 clk_prepare_enable(pll_x_clk);
80 ret = clk_set_parent(cpu_clk, pll_p_clk);
82 clk_disable_unprepare(pll_x_clk);
84 pll_x_prepared = true;
89 static int tegra_target(struct cpufreq_policy *policy, unsigned int index)
91 unsigned long rate = freq_table[index].frequency;
92 unsigned int ifreq = clk_get_rate(pll_p_clk) / 1000;
96 * Vote on memory bus frequency based on cpu frequency
97 * This sets the minimum frequency, display or avp may request higher
100 clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
101 else if (rate >= 456000)
102 clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
104 clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */
107 * target freq == pll_p, don't need to take extra reference to pll_x_clk
108 * as it isn't used anymore.
111 return clk_set_parent(cpu_clk, pll_p_clk);
113 ret = clk_set_rate(pll_x_clk, rate * 1000);
114 /* Restore to earlier frequency on error, i.e. pll_x */
116 pr_err("Failed to change pll_x to %lu\n", rate);
118 ret = clk_set_parent(cpu_clk, pll_x_clk);
119 /* This shouldn't fail while changing or restoring */
123 * Drop count to pll_x clock only if we switched to intermediate freq
124 * earlier while transitioning to a target frequency.
126 if (pll_x_prepared) {
127 clk_disable_unprepare(pll_x_clk);
128 pll_x_prepared = false;
134 static int tegra_cpu_init(struct cpufreq_policy *policy)
138 if (policy->cpu >= NUM_CPUS)
141 clk_prepare_enable(emc_clk);
142 clk_prepare_enable(cpu_clk);
144 /* FIXME: what's the actual transition time? */
145 ret = cpufreq_generic_init(policy, freq_table, 300 * 1000);
147 clk_disable_unprepare(cpu_clk);
148 clk_disable_unprepare(emc_clk);
152 policy->clk = cpu_clk;
153 policy->suspend_freq = freq_table[0].frequency;
157 static int tegra_cpu_exit(struct cpufreq_policy *policy)
159 clk_disable_unprepare(cpu_clk);
160 clk_disable_unprepare(emc_clk);
164 static struct cpufreq_driver tegra_cpufreq_driver = {
165 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
166 .verify = cpufreq_generic_frequency_table_verify,
167 .get_intermediate = tegra_get_intermediate,
168 .target_intermediate = tegra_target_intermediate,
169 .target_index = tegra_target,
170 .get = cpufreq_generic_get,
171 .init = tegra_cpu_init,
172 .exit = tegra_cpu_exit,
174 .attr = cpufreq_generic_attr,
176 .suspend = cpufreq_generic_suspend,
180 static int __init tegra_cpufreq_init(void)
182 cpu_clk = clk_get_sys(NULL, "cclk");
184 return PTR_ERR(cpu_clk);
186 pll_x_clk = clk_get_sys(NULL, "pll_x");
187 if (IS_ERR(pll_x_clk))
188 return PTR_ERR(pll_x_clk);
190 pll_p_clk = clk_get_sys(NULL, "pll_p");
191 if (IS_ERR(pll_p_clk))
192 return PTR_ERR(pll_p_clk);
194 emc_clk = clk_get_sys("cpu", "emc");
195 if (IS_ERR(emc_clk)) {
197 return PTR_ERR(emc_clk);
200 return cpufreq_register_driver(&tegra_cpufreq_driver);
203 static void __exit tegra_cpufreq_exit(void)
205 cpufreq_unregister_driver(&tegra_cpufreq_driver);
211 MODULE_AUTHOR("Colin Cross <ccross@android.com>");
212 MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
213 MODULE_LICENSE("GPL");
214 module_init(tegra_cpufreq_init);
215 module_exit(tegra_cpufreq_exit);