1 /* * CAAM control-plane driver backend
2 * Controller-level driver, kernel property detection, initialization
4 * Copyright 2008-2012 Freescale Semiconductor, Inc.
7 #include <linux/device.h>
8 #include <linux/of_address.h>
9 #include <linux/of_irq.h>
15 #include "desc_constr.h"
19 * Descriptor to instantiate RNG State Handle 0 in normal mode and
20 * load the JDKEK, TDKEK and TDSK registers
22 static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
24 u32 *jump_cmd, op_flags;
26 init_job_desc(desc, 0);
28 op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
29 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT;
31 /* INIT RNG in non-test mode */
32 append_operation(desc, op_flags);
34 if (!handle && do_sk) {
36 * For SH0, Secure Keys must be generated as well
40 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
41 set_jump_tgt_here(desc, jump_cmd);
44 * load 1 to clear written reg:
45 * resets the done interrrupt and returns the RNG to idle.
47 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
49 /* Initialize State Handle */
50 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
54 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
57 /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
58 static void build_deinstantiation_desc(u32 *desc, int handle)
60 init_job_desc(desc, 0);
62 /* Uninstantiate State Handle 0 */
63 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
64 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
66 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
70 * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
71 * the software (no JR/QI used).
72 * @ctrldev - pointer to device
73 * @status - descriptor status, after being run
75 * Return: - 0 if no error occurred
76 * - -ENODEV if the DECO couldn't be acquired
77 * - -EAGAIN if an error occurred while executing the descriptor
79 static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
82 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
83 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
84 struct caam_deco __iomem *deco = ctrlpriv->deco;
85 unsigned int timeout = 100000;
86 u32 deco_dbg_reg, flags;
90 if (ctrlpriv->virt_en == 1) {
91 setbits32(&ctrl->deco_rsr, DECORSR_JR0);
93 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
100 setbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
102 while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
107 dev_err(ctrldev, "failed to acquire DECO 0\n");
108 clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
112 for (i = 0; i < desc_len(desc); i++)
113 wr_reg32(&deco->descbuf[i], *(desc + i));
115 flags = DECO_JQCR_WHL;
117 * If the descriptor length is longer than 4 words, then the
118 * FOUR bit in JRCTRL register must be set.
120 if (desc_len(desc) >= 4)
121 flags |= DECO_JQCR_FOUR;
123 /* Instruct the DECO to execute it */
124 wr_reg32(&deco->jr_ctl_hi, flags);
128 deco_dbg_reg = rd_reg32(&deco->desc_dbg);
130 * If an error occured in the descriptor, then
131 * the DECO status field will be set to 0x0D
133 if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) ==
134 DESC_DBG_DECO_STAT_HOST_ERR)
137 } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
139 *status = rd_reg32(&deco->op_status_hi) &
140 DECO_OP_STATUS_HI_ERR_MASK;
142 if (ctrlpriv->virt_en == 1)
143 clrbits32(&ctrl->deco_rsr, DECORSR_JR0);
145 /* Mark the DECO as free */
146 clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
155 * instantiate_rng - builds and executes a descriptor on DECO0,
156 * which initializes the RNG block.
157 * @ctrldev - pointer to device
158 * @state_handle_mask - bitmask containing the instantiation status
159 * for the RNG4 state handles which exist in
160 * the RNG4 block: 1 if it's been instantiated
161 * by an external entry, 0 otherwise.
162 * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK;
163 * Caution: this can be done only once; if the keys need to be
164 * regenerated, a POR is required
166 * Return: - 0 if no error occurred
167 * - -ENOMEM if there isn't enough memory to allocate the descriptor
168 * - -ENODEV if DECO0 couldn't be acquired
169 * - -EAGAIN if an error occurred when executing the descriptor
170 * f.i. there was a RNG hardware error due to not "good enough"
171 * entropy being aquired.
173 static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
176 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
177 struct caam_ctrl __iomem *ctrl;
178 struct rng4tst __iomem *r4tst;
179 u32 *desc, status, rdsta_val;
182 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
183 r4tst = &ctrl->r4tst[0];
185 desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
189 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
191 * If the corresponding bit is set, this state handle
192 * was initialized by somebody else, so it's left alone.
194 if ((1 << sh_idx) & state_handle_mask)
197 /* Create the descriptor for instantiating RNG State Handle */
198 build_instantiation_desc(desc, sh_idx, gen_sk);
200 /* Try to run it through DECO0 */
201 ret = run_descriptor_deco0(ctrldev, desc, &status);
204 * If ret is not 0, or descriptor status is not 0, then
205 * something went wrong. No need to try the next state
206 * handle (if available), bail out here.
207 * Also, if for some reason, the State Handle didn't get
208 * instantiated although the descriptor has finished
209 * without any error (HW optimizations for later
210 * CAAM eras), then try again.
213 rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
214 if (status || !(rdsta_val & (1 << sh_idx)))
218 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
219 /* Clear the contents before recreating the descriptor */
220 memset(desc, 0x00, CAAM_CMD_SZ * 7);
229 * deinstantiate_rng - builds and executes a descriptor on DECO0,
230 * which deinitializes the RNG block.
231 * @ctrldev - pointer to device
232 * @state_handle_mask - bitmask containing the instantiation status
233 * for the RNG4 state handles which exist in
234 * the RNG4 block: 1 if it's been instantiated
236 * Return: - 0 if no error occurred
237 * - -ENOMEM if there isn't enough memory to allocate the descriptor
238 * - -ENODEV if DECO0 couldn't be acquired
239 * - -EAGAIN if an error occurred when executing the descriptor
241 static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
246 desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);
250 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
252 * If the corresponding bit is set, then it means the state
253 * handle was initialized by us, and thus it needs to be
254 * deintialized as well
256 if ((1 << sh_idx) & state_handle_mask) {
258 * Create the descriptor for deinstantating this state
261 build_deinstantiation_desc(desc, sh_idx);
263 /* Try to run it through DECO0 */
264 ret = run_descriptor_deco0(ctrldev, desc, &status);
268 "Failed to deinstantiate RNG4 SH%d\n",
272 dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
281 static int caam_remove(struct platform_device *pdev)
283 struct device *ctrldev;
284 struct caam_drv_private *ctrlpriv;
285 struct caam_ctrl __iomem *ctrl;
288 ctrldev = &pdev->dev;
289 ctrlpriv = dev_get_drvdata(ctrldev);
290 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
292 /* Remove platform devices for JobRs */
293 for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) {
294 if (ctrlpriv->jrpdev[ring])
295 of_device_unregister(ctrlpriv->jrpdev[ring]);
298 /* De-initialize RNG state handles initialized by this driver. */
299 if (ctrlpriv->rng4_sh_init)
300 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
302 /* Shut down debug views */
303 #ifdef CONFIG_DEBUG_FS
304 debugfs_remove_recursive(ctrlpriv->dfs_root);
307 /* Unmap controller region */
314 * kick_trng - sets the various parameters for enabling the initialization
315 * of the RNG4 block in CAAM
316 * @pdev - pointer to the platform device
317 * @ent_delay - Defines the length (in system clocks) of each entropy sample.
319 static void kick_trng(struct platform_device *pdev, int ent_delay)
321 struct device *ctrldev = &pdev->dev;
322 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
323 struct caam_ctrl __iomem *ctrl;
324 struct rng4tst __iomem *r4tst;
327 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
328 r4tst = &ctrl->r4tst[0];
330 /* put RNG4 into program mode */
331 setbits32(&r4tst->rtmctl, RTMCTL_PRGM);
334 * Performance-wise, it does not make sense to
335 * set the delay to a value that is lower
336 * than the last one that worked (i.e. the state handles
337 * were instantiated properly. Thus, instead of wasting
338 * time trying to set the values controlling the sample
339 * frequency, the function simply returns.
341 val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
342 >> RTSDCTL_ENT_DLY_SHIFT;
343 if (ent_delay <= val) {
344 /* put RNG4 into run mode */
345 clrbits32(&r4tst->rtmctl, RTMCTL_PRGM);
349 val = rd_reg32(&r4tst->rtsdctl);
350 val = (val & ~RTSDCTL_ENT_DLY_MASK) |
351 (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
352 wr_reg32(&r4tst->rtsdctl, val);
353 /* min. freq. count, equal to 1/4 of the entropy sample length */
354 wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
355 /* disable maximum frequency count */
356 wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
357 /* read the control register */
358 val = rd_reg32(&r4tst->rtmctl);
360 * select raw sampling in both entropy shifter
361 * and statistical checker
363 setbits32(&val, RTMCTL_SAMP_MODE_RAW_ES_SC);
364 /* put RNG4 into run mode */
365 clrbits32(&val, RTMCTL_PRGM);
366 /* write back the control register */
367 wr_reg32(&r4tst->rtmctl, val);
371 * caam_get_era() - Return the ERA of the SEC on SoC, based
372 * on "sec-era" propery in the DTS. This property is updated by u-boot.
374 int caam_get_era(void)
376 struct device_node *caam_node;
377 for_each_compatible_node(caam_node, NULL, "fsl,sec-v4.0") {
378 const uint32_t *prop = (uint32_t *)of_get_property(caam_node,
381 return prop ? *prop : -ENOTSUPP;
386 EXPORT_SYMBOL(caam_get_era);
388 /* Probe routine for CAAM top (controller) level */
389 static int caam_probe(struct platform_device *pdev)
391 int ret, ring, rspec, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
394 struct device_node *nprop, *np;
395 struct caam_ctrl __iomem *ctrl;
396 struct caam_drv_private *ctrlpriv;
397 #ifdef CONFIG_DEBUG_FS
398 struct caam_perfmon *perfmon;
400 u32 scfgr, comp_params;
403 int BLOCK_OFFSET = 0;
405 ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(struct caam_drv_private),
411 dev_set_drvdata(dev, ctrlpriv);
412 ctrlpriv->pdev = pdev;
413 nprop = pdev->dev.of_node;
415 /* Get configuration properties from device tree */
416 /* First, get register page */
417 ctrl = of_iomap(nprop, 0);
419 dev_err(dev, "caam: of_iomap() failed\n");
422 /* Finding the page size for using the CTPR_MS register */
423 comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
424 pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
426 /* Allocating the BLOCK_OFFSET based on the supported page size on
430 BLOCK_OFFSET = PG_SIZE_4K;
432 BLOCK_OFFSET = PG_SIZE_64K;
434 ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl;
435 ctrlpriv->assure = (struct caam_assurance __force *)
437 BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
439 ctrlpriv->deco = (struct caam_deco __force *)
441 BLOCK_OFFSET * DECO_BLOCK_NUMBER
444 /* Get the IRQ of the controller (for security violations only) */
445 ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
448 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
449 * long pointers in master configuration register
451 setbits32(&ctrl->mcr, MCFGR_WDENABLE |
452 (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
455 * Read the Compile Time paramters and SCFGR to determine
456 * if Virtualization is enabled for this platform
458 scfgr = rd_reg32(&ctrl->scfgr);
460 ctrlpriv->virt_en = 0;
461 if (comp_params & CTPR_MS_VIRT_EN_INCL) {
462 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
463 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
465 if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
466 (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
467 (scfgr & SCFGR_VIRT_EN)))
468 ctrlpriv->virt_en = 1;
470 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
471 if (comp_params & CTPR_MS_VIRT_EN_POR)
472 ctrlpriv->virt_en = 1;
475 if (ctrlpriv->virt_en == 1)
476 setbits32(&ctrl->jrstart, JRSTART_JR0_START |
477 JRSTART_JR1_START | JRSTART_JR2_START |
480 if (sizeof(dma_addr_t) == sizeof(u64))
481 if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
482 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
484 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
486 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
489 * Detect and enable JobRs
490 * First, find out how many ring spec'ed, allocate references
491 * for all, then go probe each one.
494 for_each_available_child_of_node(nprop, np)
495 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
496 of_device_is_compatible(np, "fsl,sec4.0-job-ring"))
499 ctrlpriv->jrpdev = devm_kzalloc(&pdev->dev,
500 sizeof(struct platform_device *) * rspec,
502 if (ctrlpriv->jrpdev == NULL) {
508 ctrlpriv->total_jobrs = 0;
509 for_each_available_child_of_node(nprop, np)
510 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
511 of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
512 ctrlpriv->jrpdev[ring] =
513 of_platform_device_create(np, NULL, dev);
514 if (!ctrlpriv->jrpdev[ring]) {
515 pr_warn("JR%d Platform device creation error\n",
519 ctrlpriv->jr[ring] = (struct caam_job_ring __force *)
521 (ring + JR_BLOCK_NUMBER) *
524 ctrlpriv->total_jobrs++;
528 /* Check to see if QI present. If so, enable */
529 ctrlpriv->qi_present =
530 !!(rd_reg32(&ctrl->perfmon.comp_parms_ms) &
532 if (ctrlpriv->qi_present) {
533 ctrlpriv->qi = (struct caam_queue_if __force *)
535 BLOCK_OFFSET * QI_BLOCK_NUMBER
537 /* This is all that's required to physically enable QI */
538 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
541 /* If no QI and no rings specified, quit and go home */
542 if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
543 dev_err(dev, "no queues configured, terminating\n");
548 cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls);
551 * If SEC has RNG version >= 4 and RNG state handle has not been
552 * already instantiated, do RNG instantiation
554 if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
555 ctrlpriv->rng4_sh_init =
556 rd_reg32(&ctrl->r4tst[0].rdsta);
558 * If the secure keys (TDKEK, JDKEK, TDSK), were already
559 * generated, signal this to the function that is instantiating
560 * the state handles. An error would occur if RNG4 attempts
561 * to regenerate these keys before the next POR.
563 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
564 ctrlpriv->rng4_sh_init &= RDSTA_IFMASK;
567 rd_reg32(&ctrl->r4tst[0].rdsta) &
570 * If either SH were instantiated by somebody else
571 * (e.g. u-boot) then it is assumed that the entropy
572 * parameters are properly set and thus the function
573 * setting these (kick_trng(...)) is skipped.
574 * Also, if a handle was instantiated, do not change
575 * the TRNG parameters.
577 if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
579 "Entropy delay = %u\n",
581 kick_trng(pdev, ent_delay);
585 * if instantiate_rng(...) fails, the loop will rerun
586 * and the kick_trng(...) function will modfiy the
587 * upper and lower limits of the entropy sampling
588 * interval, leading to a sucessful initialization of
591 ret = instantiate_rng(dev, inst_handles,
595 * if here, the loop will rerun,
596 * so don't hog the CPU
599 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
601 dev_err(dev, "failed to instantiate RNG");
606 * Set handles init'ed by this module as the complement of the
607 * already initialized ones
609 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK;
611 /* Enable RDB bit so that RNG works faster */
612 setbits32(&ctrl->scfgr, SCFGR_RDBENABLE);
615 /* NOTE: RTIC detection ought to go here, around Si time */
617 caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
618 (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
620 /* Report "alive" for developer to see */
621 dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
623 dev_info(dev, "job rings = %d, qi = %d\n",
624 ctrlpriv->total_jobrs, ctrlpriv->qi_present);
626 #ifdef CONFIG_DEBUG_FS
628 * FIXME: needs better naming distinction, as some amalgamation of
629 * "caam" and nprop->full_name. The OF name isn't distinctive,
630 * but does separate instances
632 perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
634 ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL);
635 ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root);
637 /* Controller-level - performance monitor counters */
638 ctrlpriv->ctl_rq_dequeued =
639 debugfs_create_u64("rq_dequeued",
640 S_IRUSR | S_IRGRP | S_IROTH,
641 ctrlpriv->ctl, &perfmon->req_dequeued);
642 ctrlpriv->ctl_ob_enc_req =
643 debugfs_create_u64("ob_rq_encrypted",
644 S_IRUSR | S_IRGRP | S_IROTH,
645 ctrlpriv->ctl, &perfmon->ob_enc_req);
646 ctrlpriv->ctl_ib_dec_req =
647 debugfs_create_u64("ib_rq_decrypted",
648 S_IRUSR | S_IRGRP | S_IROTH,
649 ctrlpriv->ctl, &perfmon->ib_dec_req);
650 ctrlpriv->ctl_ob_enc_bytes =
651 debugfs_create_u64("ob_bytes_encrypted",
652 S_IRUSR | S_IRGRP | S_IROTH,
653 ctrlpriv->ctl, &perfmon->ob_enc_bytes);
654 ctrlpriv->ctl_ob_prot_bytes =
655 debugfs_create_u64("ob_bytes_protected",
656 S_IRUSR | S_IRGRP | S_IROTH,
657 ctrlpriv->ctl, &perfmon->ob_prot_bytes);
658 ctrlpriv->ctl_ib_dec_bytes =
659 debugfs_create_u64("ib_bytes_decrypted",
660 S_IRUSR | S_IRGRP | S_IROTH,
661 ctrlpriv->ctl, &perfmon->ib_dec_bytes);
662 ctrlpriv->ctl_ib_valid_bytes =
663 debugfs_create_u64("ib_bytes_validated",
664 S_IRUSR | S_IRGRP | S_IROTH,
665 ctrlpriv->ctl, &perfmon->ib_valid_bytes);
667 /* Controller level - global status values */
668 ctrlpriv->ctl_faultaddr =
669 debugfs_create_u64("fault_addr",
670 S_IRUSR | S_IRGRP | S_IROTH,
671 ctrlpriv->ctl, &perfmon->faultaddr);
672 ctrlpriv->ctl_faultdetail =
673 debugfs_create_u32("fault_detail",
674 S_IRUSR | S_IRGRP | S_IROTH,
675 ctrlpriv->ctl, &perfmon->faultdetail);
676 ctrlpriv->ctl_faultstatus =
677 debugfs_create_u32("fault_status",
678 S_IRUSR | S_IRGRP | S_IROTH,
679 ctrlpriv->ctl, &perfmon->status);
681 /* Internal covering keys (useful in non-secure mode only) */
682 ctrlpriv->ctl_kek_wrap.data = &ctrlpriv->ctrl->kek[0];
683 ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
684 ctrlpriv->ctl_kek = debugfs_create_blob("kek",
688 &ctrlpriv->ctl_kek_wrap);
690 ctrlpriv->ctl_tkek_wrap.data = &ctrlpriv->ctrl->tkek[0];
691 ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
692 ctrlpriv->ctl_tkek = debugfs_create_blob("tkek",
696 &ctrlpriv->ctl_tkek_wrap);
698 ctrlpriv->ctl_tdsk_wrap.data = &ctrlpriv->ctrl->tdsk[0];
699 ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32);
700 ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk",
704 &ctrlpriv->ctl_tdsk_wrap);
709 static struct of_device_id caam_match[] = {
711 .compatible = "fsl,sec-v4.0",
714 .compatible = "fsl,sec4.0",
718 MODULE_DEVICE_TABLE(of, caam_match);
720 static struct platform_driver caam_driver = {
723 .owner = THIS_MODULE,
724 .of_match_table = caam_match,
727 .remove = caam_remove,
730 module_platform_driver(caam_driver);
732 MODULE_LICENSE("GPL");
733 MODULE_DESCRIPTION("FSL CAAM request backend");
734 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");