2 * CAAM hardware register-level view
4 * Copyright 2008-2011 Freescale Semiconductor, Inc.
10 #include <linux/types.h>
14 * Architecture-specific register access methods
16 * CAAM's bus-addressable registers are 64 bits internally.
17 * They have been wired to be safely accessible on 32-bit
18 * architectures, however. Registers were organized such
19 * that (a) they can be contained in 32 bits, (b) if not, then they
20 * can be treated as two 32-bit entities, or finally (c) if they
21 * must be treated as a single 64-bit value, then this can safely
22 * be done with two 32-bit cycles.
24 * For 32-bit operations on 64-bit values, CAAM follows the same
25 * 64-bit register access conventions as it's predecessors, in that
26 * writes are "triggered" by a write to the register at the numerically
27 * higher address, thus, a full 64-bit write cycle requires a write
28 * to the lower address, followed by a write to the higher address,
29 * which will latch/execute the write cycle.
31 * For example, let's assume a SW reset of CAAM through the master
32 * configuration register.
33 * - SWRST is in bit 31 of MCFG.
34 * - MCFG begins at base+0x0000.
35 * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower)
36 * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher)
38 * (and on Power, the convention is 0-31, 32-63, I know...)
40 * Assuming a 64-bit write to this MCFG to perform a software reset
41 * would then require a write of 0 to base+0x0000, followed by a
42 * write of 0x80000000 to base+0x0004, which would "execute" the
45 * Of course, since MCFG 63-32 is all zero, we could cheat and simply
46 * write 0x8000000 to base+0x0004, and the reset would work fine.
47 * However, since CAAM does contain some write-and-read-intended
48 * 64-bit registers, this code defines 64-bit access methods for
49 * the sake of internal consistency and simplicity, and so that a
50 * clean transition to 64-bit is possible when it becomes necessary.
52 * There are limitations to this that the developer must recognize.
53 * 32-bit architectures cannot enforce an atomic-64 operation,
56 * - On writes, since the HW is assumed to latch the cycle on the
57 * write of the higher-numeric-address word, then ordered
60 * - For reads, where a register contains a relevant value of more
61 * that 32 bits, the hardware employs logic to latch the other
62 * "half" of the data until read, ensuring an accurate value.
63 * This is of particular relevance when dealing with CAAM's
64 * performance counters.
69 #define wr_reg32(reg, data) out_be32(reg, data)
70 #define rd_reg32(reg) in_be32(reg)
72 #define wr_reg64(reg, data) out_be64(reg, data)
73 #define rd_reg64(reg) in_be64(reg)
76 #ifdef __LITTLE_ENDIAN
77 #define wr_reg32(reg, data) __raw_writel(reg, data)
78 #define rd_reg32(reg) __raw_readl(reg)
80 #define wr_reg64(reg, data) __raw_writeq(reg, data)
81 #define rd_reg64(reg) __raw_readq(reg)
87 static inline void wr_reg64(u64 __iomem *reg, u64 data)
89 wr_reg32((u32 __iomem *)reg, (data & 0xffffffff00000000ull) >> 32);
90 wr_reg32((u32 __iomem *)reg + 1, data & 0x00000000ffffffffull);
93 static inline u64 rd_reg64(u64 __iomem *reg)
95 return (((u64)rd_reg32((u32 __iomem *)reg)) << 32) |
96 ((u64)rd_reg32((u32 __iomem *)reg + 1));
102 * Represents each entry in a JobR output ring
105 dma_addr_t desc;/* Pointer to completed descriptor */
106 u32 jrstatus; /* Status for completed descriptor */
110 * caam_perfmon - Performance Monitor/Secure Memory Status/
111 * CAAM Global Status/Component Version IDs
113 * Spans f00-fff wherever instantiated
116 /* Number of DECOs */
117 #define CHA_NUM_DECONUM_SHIFT 56
118 #define CHA_NUM_DECONUM_MASK (0xfull << CHA_NUM_DECONUM_SHIFT)
126 struct caam_perfmon {
127 /* Performance Monitor Registers f00-f9f */
128 u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */
129 u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */
130 u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests */
131 u64 ob_enc_bytes; /* PC_OB_ENCRYPT - Outbound Bytes Encrypted */
132 u64 ob_prot_bytes; /* PC_OB_PROTECT - Outbound Bytes Protected */
133 u64 ib_dec_bytes; /* PC_IB_DECRYPT - Inbound Bytes Decrypted */
134 u64 ib_valid_bytes; /* PC_IB_VALIDATED Inbound Bytes Validated */
137 /* CAAM Hardware Instantiation Parameters fa0-fbf */
138 u64 cha_rev; /* CRNR - CHA Revision Number */
139 #define CTPR_QI_SHIFT 57
140 #define CTPR_QI_MASK (0x1ull << CTPR_QI_SHIFT)
141 u64 comp_parms; /* CTPR - Compile Parameters Register */
144 /* CAAM Global Status fc0-fdf */
145 u64 faultaddr; /* FAR - Fault Address */
146 u32 faultliodn; /* FALR - Fault Address LIODN */
147 u32 faultdetail; /* FADR - Fault Addr Detail */
149 u32 status; /* CSTA - CAAM Status */
152 /* Component Instantiation Parameters fe0-fff */
153 u32 rtic_id; /* RVID - RTIC Version ID */
154 u32 ccb_id; /* CCBVID - CCB Version ID */
155 u64 cha_id; /* CHAVID - CHA Version ID */
156 u64 cha_num; /* CHANUM - CHA Number */
157 u64 caam_id; /* CAAMVID - CAAM Version ID */
160 /* LIODN programming for DMA configuration */
161 #define MSTRID_LOCK_LIODN 0x80000000
162 #define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */
164 #define MSTRID_LIODN_MASK 0x0fff
166 u32 liodn_ms; /* lock and make-trusted control bits */
167 u32 liodn_ls; /* LIODN for non-sequence and seq access */
170 /* Partition ID for DMA configuration */
173 u32 pidr; /* partition ID, DECO */
176 /* RNGB test mode (replicated twice in some configurations) */
177 /* Padded out to 0x100 */
179 u32 mode; /* RTSTMODEx - Test mode */
181 u32 reset; /* RTSTRESETx - Test reset control */
183 u32 status; /* RTSTSSTATUSx - Test status */
185 u32 errstat; /* RTSTERRSTATx - Test error status */
187 u32 errctl; /* RTSTERRCTLx - Test error control */
189 u32 entropy; /* RTSTENTROPYx - Test entropy */
191 u32 verifctl; /* RTSTVERIFCTLx - Test verification control */
193 u32 verifstat; /* RTSTVERIFSTATx - Test verification status */
195 u32 verifdata; /* RTSTVERIFDx - Test verification data */
197 u32 xkey; /* RTSTXKEYx - Test XKEY */
199 u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */
201 u32 oscct; /* RTSTOSCCTx - Test oscillator counter */
203 u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */
205 u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */
209 /* RNG4 TRNG test registers */
211 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
212 u32 rtmctl; /* misc. control register */
213 u32 rtscmisc; /* statistical check misc. register */
214 u32 rtpkrrng; /* poker range register */
216 u32 rtpkrmax; /* PRGM=1: poker max. limit register */
217 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
219 #define RTSDCTL_ENT_DLY_SHIFT 16
220 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
221 u32 rtsdctl; /* seed control register */
223 u32 rtsblim; /* PRGM=1: sparse bit limit register */
224 u32 rttotsam; /* PRGM=0: total samples register */
226 u32 rtfrqmin; /* frequency count min. limit register */
228 u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */
229 u32 rtfrqcnt; /* PRGM=0: freq. count register */
235 * caam_ctrl - basic core configuration
236 * starts base + 0x0000 padded out to 0x1000
239 #define KEK_KEY_SIZE 8
240 #define TKEK_KEY_SIZE 8
241 #define TDSK_KEY_SIZE 8
243 #define DECO_RESET 1 /* Use with DECO reset/availability regs */
244 #define DECO_RESET_0 (DECO_RESET << 0)
245 #define DECO_RESET_1 (DECO_RESET << 1)
246 #define DECO_RESET_2 (DECO_RESET << 2)
247 #define DECO_RESET_3 (DECO_RESET << 3)
248 #define DECO_RESET_4 (DECO_RESET << 4)
251 /* Basic Configuration Section 000-01f */
254 u32 mcr; /* MCFG Master Config Register */
256 u32 scfgr; /* SCFGR, Security Config Register */
258 /* Bus Access Configuration Section 010-11f */
260 struct masterid jr_mid[4]; /* JRxLIODNR - JobR LIODN setup */
262 struct masterid rtic_mid[4]; /* RTICxLIODNR - RTIC LIODN setup */
264 u32 deco_rq; /* DECORR - DECO Request */
265 struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */
268 /* DECO Availability/Reset Section 120-3ff */
269 u32 deco_avail; /* DAR - DECO availability */
270 u32 deco_reset; /* DRR - DECO reset */
273 /* Key Encryption/Decryption Configuration 400-5ff */
274 /* Read/Writable only while in Non-secure mode */
275 u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */
276 u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */
277 u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */
279 u64 sknonce; /* SKNR - Secure Key Nonce */
282 /* RNG Test/Verification/Debug Access 600-7ff */
283 /* (Useful in Test/Debug modes only...) */
285 struct rngtst rtst[2];
286 struct rng4tst r4tst[2];
291 /* Performance Monitor f00-fff */
292 struct caam_perfmon perfmon;
296 * Controller master config register defs
298 #define MCFGR_SWRESET 0x80000000 /* software reset */
299 #define MCFGR_WDENABLE 0x40000000 /* DECO watchdog enable */
300 #define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */
301 #define MCFGR_DMA_RESET 0x10000000
302 #define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */
303 #define SCFGR_RDBENABLE 0x00000400
305 /* AXI read cache control */
306 #define MCFGR_ARCACHE_SHIFT 12
307 #define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT)
309 /* AXI write cache control */
310 #define MCFGR_AWCACHE_SHIFT 8
311 #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT)
313 /* AXI pipeline depth */
314 #define MCFGR_AXIPIPE_SHIFT 4
315 #define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT)
317 #define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */
318 #define MCFGR_BURST_64 0x00000001 /* Max burst size */
321 * caam_job_ring - direct job ring setup
322 * 1-4 possible per instantiation, base + 1000/2000/3000/4000
323 * Padded out to 0x1000
325 struct caam_job_ring {
327 u64 inpring_base; /* IRBAx - Input desc ring baseaddr */
329 u32 inpring_size; /* IRSx - Input ring size */
331 u32 inpring_avail; /* IRSAx - Input ring room remaining */
333 u32 inpring_jobadd; /* IRJAx - Input ring jobs added */
336 u64 outring_base; /* ORBAx - Output status ring base addr */
338 u32 outring_size; /* ORSx - Output ring size */
340 u32 outring_rmvd; /* ORJRx - Output ring jobs removed */
342 u32 outring_used; /* ORSFx - Output ring slots full */
344 /* Status/Configuration */
346 u32 jroutstatus; /* JRSTAx - JobR output status */
348 u32 jrintstatus; /* JRINTx - JobR interrupt status */
349 u32 rconfig_hi; /* JRxCFG - Ring configuration */
352 /* Indices. CAAM maintains as "heads" of each queue */
354 u32 inp_rdidx; /* IRRIx - Input ring read index */
356 u32 out_wtidx; /* ORWIx - Output ring write index */
358 /* Command/control */
360 u32 jrcommand; /* JRCRx - JobR command */
364 /* Performance Monitor f00-fff */
365 struct caam_perfmon perfmon;
368 #define JR_RINGSIZE_MASK 0x03ff
370 * jrstatus - Job Ring Output Status
371 * All values in lo word
372 * Also note, same values written out as status through QI
373 * in the command/status field of a frame descriptor
375 #define JRSTA_SSRC_SHIFT 28
376 #define JRSTA_SSRC_MASK 0xf0000000
378 #define JRSTA_SSRC_NONE 0x00000000
379 #define JRSTA_SSRC_CCB_ERROR 0x20000000
380 #define JRSTA_SSRC_JUMP_HALT_USER 0x30000000
381 #define JRSTA_SSRC_DECO 0x40000000
382 #define JRSTA_SSRC_JRERROR 0x60000000
383 #define JRSTA_SSRC_JUMP_HALT_CC 0x70000000
385 #define JRSTA_DECOERR_JUMP 0x08000000
386 #define JRSTA_DECOERR_INDEX_SHIFT 8
387 #define JRSTA_DECOERR_INDEX_MASK 0xff00
388 #define JRSTA_DECOERR_ERROR_MASK 0x00ff
390 #define JRSTA_DECOERR_NONE 0x00
391 #define JRSTA_DECOERR_LINKLEN 0x01
392 #define JRSTA_DECOERR_LINKPTR 0x02
393 #define JRSTA_DECOERR_JRCTRL 0x03
394 #define JRSTA_DECOERR_DESCCMD 0x04
395 #define JRSTA_DECOERR_ORDER 0x05
396 #define JRSTA_DECOERR_KEYCMD 0x06
397 #define JRSTA_DECOERR_LOADCMD 0x07
398 #define JRSTA_DECOERR_STORECMD 0x08
399 #define JRSTA_DECOERR_OPCMD 0x09
400 #define JRSTA_DECOERR_FIFOLDCMD 0x0a
401 #define JRSTA_DECOERR_FIFOSTCMD 0x0b
402 #define JRSTA_DECOERR_MOVECMD 0x0c
403 #define JRSTA_DECOERR_JUMPCMD 0x0d
404 #define JRSTA_DECOERR_MATHCMD 0x0e
405 #define JRSTA_DECOERR_SHASHCMD 0x0f
406 #define JRSTA_DECOERR_SEQCMD 0x10
407 #define JRSTA_DECOERR_DECOINTERNAL 0x11
408 #define JRSTA_DECOERR_SHDESCHDR 0x12
409 #define JRSTA_DECOERR_HDRLEN 0x13
410 #define JRSTA_DECOERR_BURSTER 0x14
411 #define JRSTA_DECOERR_DESCSIGNATURE 0x15
412 #define JRSTA_DECOERR_DMA 0x16
413 #define JRSTA_DECOERR_BURSTFIFO 0x17
414 #define JRSTA_DECOERR_JRRESET 0x1a
415 #define JRSTA_DECOERR_JOBFAIL 0x1b
416 #define JRSTA_DECOERR_DNRERR 0x80
417 #define JRSTA_DECOERR_UNDEFPCL 0x81
418 #define JRSTA_DECOERR_PDBERR 0x82
419 #define JRSTA_DECOERR_ANRPLY_LATE 0x83
420 #define JRSTA_DECOERR_ANRPLY_REPLAY 0x84
421 #define JRSTA_DECOERR_SEQOVF 0x85
422 #define JRSTA_DECOERR_INVSIGN 0x86
423 #define JRSTA_DECOERR_DSASIGN 0x87
425 #define JRSTA_CCBERR_JUMP 0x08000000
426 #define JRSTA_CCBERR_INDEX_MASK 0xff00
427 #define JRSTA_CCBERR_INDEX_SHIFT 8
428 #define JRSTA_CCBERR_CHAID_MASK 0x00f0
429 #define JRSTA_CCBERR_CHAID_SHIFT 4
430 #define JRSTA_CCBERR_ERRID_MASK 0x000f
432 #define JRSTA_CCBERR_CHAID_AES (0x01 << JRSTA_CCBERR_CHAID_SHIFT)
433 #define JRSTA_CCBERR_CHAID_DES (0x02 << JRSTA_CCBERR_CHAID_SHIFT)
434 #define JRSTA_CCBERR_CHAID_ARC4 (0x03 << JRSTA_CCBERR_CHAID_SHIFT)
435 #define JRSTA_CCBERR_CHAID_MD (0x04 << JRSTA_CCBERR_CHAID_SHIFT)
436 #define JRSTA_CCBERR_CHAID_RNG (0x05 << JRSTA_CCBERR_CHAID_SHIFT)
437 #define JRSTA_CCBERR_CHAID_SNOW (0x06 << JRSTA_CCBERR_CHAID_SHIFT)
438 #define JRSTA_CCBERR_CHAID_KASUMI (0x07 << JRSTA_CCBERR_CHAID_SHIFT)
439 #define JRSTA_CCBERR_CHAID_PK (0x08 << JRSTA_CCBERR_CHAID_SHIFT)
440 #define JRSTA_CCBERR_CHAID_CRC (0x09 << JRSTA_CCBERR_CHAID_SHIFT)
442 #define JRSTA_CCBERR_ERRID_NONE 0x00
443 #define JRSTA_CCBERR_ERRID_MODE 0x01
444 #define JRSTA_CCBERR_ERRID_DATASIZ 0x02
445 #define JRSTA_CCBERR_ERRID_KEYSIZ 0x03
446 #define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04
447 #define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05
448 #define JRSTA_CCBERR_ERRID_SEQUENCE 0x06
449 #define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07
450 #define JRSTA_CCBERR_ERRID_PKMODEVN 0x08
451 #define JRSTA_CCBERR_ERRID_KEYPARIT 0x09
452 #define JRSTA_CCBERR_ERRID_ICVCHK 0x0a
453 #define JRSTA_CCBERR_ERRID_HARDWARE 0x0b
454 #define JRSTA_CCBERR_ERRID_CCMAAD 0x0c
455 #define JRSTA_CCBERR_ERRID_INVCHA 0x0f
457 #define JRINT_ERR_INDEX_MASK 0x3fff0000
458 #define JRINT_ERR_INDEX_SHIFT 16
459 #define JRINT_ERR_TYPE_MASK 0xf00
460 #define JRINT_ERR_TYPE_SHIFT 8
461 #define JRINT_ERR_HALT_MASK 0xc
462 #define JRINT_ERR_HALT_SHIFT 2
463 #define JRINT_ERR_HALT_INPROGRESS 0x4
464 #define JRINT_ERR_HALT_COMPLETE 0x8
465 #define JRINT_JR_ERROR 0x02
466 #define JRINT_JR_INT 0x01
468 #define JRINT_ERR_TYPE_WRITE 1
469 #define JRINT_ERR_TYPE_BAD_INPADDR 3
470 #define JRINT_ERR_TYPE_BAD_OUTADDR 4
471 #define JRINT_ERR_TYPE_INV_INPWRT 5
472 #define JRINT_ERR_TYPE_INV_OUTWRT 6
473 #define JRINT_ERR_TYPE_RESET 7
474 #define JRINT_ERR_TYPE_REMOVE_OFL 8
475 #define JRINT_ERR_TYPE_ADD_OFL 9
477 #define JRCFG_SOE 0x04
478 #define JRCFG_ICEN 0x02
479 #define JRCFG_IMSK 0x01
480 #define JRCFG_ICDCT_SHIFT 8
481 #define JRCFG_ICTT_SHIFT 16
483 #define JRCR_RESET 0x01
486 * caam_assurance - Assurance Controller View
487 * base + 0x6000 padded out to 0x1000
490 struct rtic_element {
497 struct rtic_element element[2];
500 struct rtic_memhash {
505 struct caam_assurance {
506 /* Status/Command/Watchdog */
508 u32 status; /* RSTA - Status */
510 u32 cmd; /* RCMD - Command */
512 u32 ctrl; /* RCTL - Control */
514 u32 throttle; /* RTHR - Throttle */
516 u64 watchdog; /* RWDOG - Watchdog Timer */
518 u32 rend; /* REND - Endian corrections */
521 /* Block access/configuration @ 100/110/120/130 */
522 struct rtic_block memblk[4]; /* Memory Blocks A-D */
525 /* Block hashes @ 200/300/400/500 */
526 struct rtic_memhash hash[4]; /* Block hash values A-D */
531 * caam_queue_if - QI configuration and control
532 * starts base + 0x7000, padded out to 0x1000 long
535 struct caam_queue_if {
536 u32 qi_control_hi; /* QICTL - QI Control */
539 u32 qi_status; /* QISTA - QI Status */
540 u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */
542 u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */
547 /* QI control bits - low word */
548 #define QICTL_DQEN 0x01 /* Enable frame pop */
549 #define QICTL_STOP 0x02 /* Stop dequeue/enqueue */
550 #define QICTL_SOE 0x04 /* Stop on error */
552 /* QI control bits - high word */
553 #define QICTL_MBSI 0x01
554 #define QICTL_MHWSI 0x02
555 #define QICTL_MWSI 0x04
556 #define QICTL_MDWSI 0x08
557 #define QICTL_CBSI 0x10 /* CtrlDataByteSwapInput */
558 #define QICTL_CHWSI 0x20 /* CtrlDataHalfSwapInput */
559 #define QICTL_CWSI 0x40 /* CtrlDataWordSwapInput */
560 #define QICTL_CDWSI 0x80 /* CtrlDataDWordSwapInput */
561 #define QICTL_MBSO 0x0100
562 #define QICTL_MHWSO 0x0200
563 #define QICTL_MWSO 0x0400
564 #define QICTL_MDWSO 0x0800
565 #define QICTL_CBSO 0x1000 /* CtrlDataByteSwapOutput */
566 #define QICTL_CHWSO 0x2000 /* CtrlDataHalfSwapOutput */
567 #define QICTL_CWSO 0x4000 /* CtrlDataWordSwapOutput */
568 #define QICTL_CDWSO 0x8000 /* CtrlDataDWordSwapOutput */
569 #define QICTL_DMBS 0x010000
570 #define QICTL_EPO 0x020000
573 #define QISTA_PHRDERR 0x01 /* PreHeader Read Error */
574 #define QISTA_CFRDERR 0x02 /* Compound Frame Read Error */
575 #define QISTA_OFWRERR 0x04 /* Output Frame Read Error */
576 #define QISTA_BPDERR 0x08 /* Buffer Pool Depleted */
577 #define QISTA_BTSERR 0x10 /* Buffer Undersize */
578 #define QISTA_CFWRERR 0x20 /* Compound Frame Write Err */
579 #define QISTA_STOPD 0x80000000 /* QI Stopped (see QICTL) */
581 /* deco_sg_table - DECO view of scatter/gather table */
582 struct deco_sg_table {
583 u64 addr; /* Segment Address */
584 u32 elen; /* E, F bits + 30-bit length */
585 u32 bpid_offset; /* Buffer Pool ID + 16-bit length */
589 * caam_deco - descriptor controller - CHA cluster block
591 * Only accessible when direct DECO access is turned on
592 * (done in DECORR, via MID programmed in DECOxMID
594 * 5 typical, base + 0x8000/9000/a000/b000
595 * Padded out to 0x1000 long
599 u32 cls1_mode; /* CxC1MR - Class 1 Mode */
601 u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */
602 u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */
603 u32 cls1_datasize_lo;
605 u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */
607 u32 cha_ctrl; /* CCTLR - CHA control */
609 u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */
611 u32 clr_written; /* CxCWR - Clear-Written */
612 u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */
615 u32 aad_size; /* CxAADSZR - Current AAD Size */
617 u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */
619 u32 pkha_a_size; /* PKASZRx - Size of PKHA A */
621 u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */
623 u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */
625 u32 pkha_e_size; /* PKESZRx - Size of PKHA E */
627 u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */
629 u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */
631 u32 cls2_mode; /* CxC2MR - Class 2 Mode */
633 u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */
634 u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */
635 u32 cls2_datasize_lo;
637 u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */
639 u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */
641 u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */
643 u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */
646 u64 inp_datafifo; /* CxDFIFO - Input Data FIFO */
648 u64 out_datafifo; /* CxOFIFO - Output Data FIFO */
650 u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */
652 u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */
653 u32 op_status_hi; /* DxOPSTA - DECO Operation Status */
656 u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */
657 u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */
659 u64 math[4]; /* DxMTH - Math register */
661 struct deco_sg_table gthr_tbl[4]; /* DxGTR - Gather Tables */
663 struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */
665 u32 descbuf[64]; /* DxDESB - Descriptor buffer */
670 * Current top-level view of memory map is:
672 * 0x0000 - 0x0fff - CAAM Top-Level Control
673 * 0x1000 - 0x1fff - Job Ring 0
674 * 0x2000 - 0x2fff - Job Ring 1
675 * 0x3000 - 0x3fff - Job Ring 2
676 * 0x4000 - 0x4fff - Job Ring 3
677 * 0x5000 - 0x5fff - (unused)
678 * 0x6000 - 0x6fff - Assurance Controller
679 * 0x7000 - 0x7fff - Queue Interface
680 * 0x8000 - 0x8fff - DECO-CCB 0
681 * 0x9000 - 0x9fff - DECO-CCB 1
682 * 0xa000 - 0xafff - DECO-CCB 2
683 * 0xb000 - 0xbfff - DECO-CCB 3
684 * 0xc000 - 0xcfff - DECO-CCB 4
686 * caam_full describes the full register view of CAAM if useful,
687 * although many configurations may choose to implement parts of
688 * the register map separately, in differing privilege regions
691 struct caam_ctrl __iomem ctrl;
692 struct caam_job_ring jr[4];
694 struct caam_assurance assure;
695 struct caam_queue_if qi;