2 * CAAM hardware register-level view
4 * Copyright 2008-2011 Freescale Semiconductor, Inc.
10 #include <linux/types.h>
14 * Architecture-specific register access methods
16 * CAAM's bus-addressable registers are 64 bits internally.
17 * They have been wired to be safely accessible on 32-bit
18 * architectures, however. Registers were organized such
19 * that (a) they can be contained in 32 bits, (b) if not, then they
20 * can be treated as two 32-bit entities, or finally (c) if they
21 * must be treated as a single 64-bit value, then this can safely
22 * be done with two 32-bit cycles.
24 * For 32-bit operations on 64-bit values, CAAM follows the same
25 * 64-bit register access conventions as it's predecessors, in that
26 * writes are "triggered" by a write to the register at the numerically
27 * higher address, thus, a full 64-bit write cycle requires a write
28 * to the lower address, followed by a write to the higher address,
29 * which will latch/execute the write cycle.
31 * For example, let's assume a SW reset of CAAM through the master
32 * configuration register.
33 * - SWRST is in bit 31 of MCFG.
34 * - MCFG begins at base+0x0000.
35 * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower)
36 * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher)
38 * (and on Power, the convention is 0-31, 32-63, I know...)
40 * Assuming a 64-bit write to this MCFG to perform a software reset
41 * would then require a write of 0 to base+0x0000, followed by a
42 * write of 0x80000000 to base+0x0004, which would "execute" the
45 * Of course, since MCFG 63-32 is all zero, we could cheat and simply
46 * write 0x8000000 to base+0x0004, and the reset would work fine.
47 * However, since CAAM does contain some write-and-read-intended
48 * 64-bit registers, this code defines 64-bit access methods for
49 * the sake of internal consistency and simplicity, and so that a
50 * clean transition to 64-bit is possible when it becomes necessary.
52 * There are limitations to this that the developer must recognize.
53 * 32-bit architectures cannot enforce an atomic-64 operation,
56 * - On writes, since the HW is assumed to latch the cycle on the
57 * write of the higher-numeric-address word, then ordered
60 * - For reads, where a register contains a relevant value of more
61 * that 32 bits, the hardware employs logic to latch the other
62 * "half" of the data until read, ensuring an accurate value.
63 * This is of particular relevance when dealing with CAAM's
64 * performance counters.
69 #define wr_reg32(reg, data) out_be32(reg, data)
70 #define rd_reg32(reg) in_be32(reg)
72 #define wr_reg64(reg, data) out_be64(reg, data)
73 #define rd_reg64(reg) in_be64(reg)
76 #ifdef __LITTLE_ENDIAN
77 #define wr_reg32(reg, data) __raw_writel(data, reg)
78 #define rd_reg32(reg) __raw_readl(reg)
80 #define wr_reg64(reg, data) __raw_writeq(data, reg)
81 #define rd_reg64(reg) __raw_readq(reg)
88 static inline void wr_reg64(u64 __iomem *reg, u64 data)
90 wr_reg32((u32 __iomem *)reg, (data & 0xffffffff00000000ull) >> 32);
91 wr_reg32((u32 __iomem *)reg + 1, data & 0x00000000ffffffffull);
94 static inline u64 rd_reg64(u64 __iomem *reg)
96 return (((u64)rd_reg32((u32 __iomem *)reg)) << 32) |
97 ((u64)rd_reg32((u32 __iomem *)reg + 1));
100 #ifdef __LITTLE_ENDIAN
101 static inline void wr_reg64(u64 __iomem *reg, u64 data)
103 wr_reg32((u32 __iomem *)reg + 1, (data & 0xffffffff00000000ull) >> 32);
104 wr_reg32((u32 __iomem *)reg, data & 0x00000000ffffffffull);
107 static inline u64 rd_reg64(u64 __iomem *reg)
109 return (((u64)rd_reg32((u32 __iomem *)reg + 1)) << 32) |
110 ((u64)rd_reg32((u32 __iomem *)reg));
118 * Represents each entry in a JobR output ring
121 dma_addr_t desc;/* Pointer to completed descriptor */
122 u32 jrstatus; /* Status for completed descriptor */
126 * caam_perfmon - Performance Monitor/Secure Memory Status/
127 * CAAM Global Status/Component Version IDs
129 * Spans f00-fff wherever instantiated
132 /* Number of DECOs */
133 #define CHA_NUM_MS_DECONUM_SHIFT 24
134 #define CHA_NUM_MS_DECONUM_MASK (0xfull << CHA_NUM_MS_DECONUM_SHIFT)
136 /* CHA Version IDs */
137 #define CHA_ID_LS_AES_SHIFT 0
138 #define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT)
140 #define CHA_ID_LS_DES_SHIFT 4
141 #define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT)
143 #define CHA_ID_LS_ARC4_SHIFT 8
144 #define CHA_ID_LS_ARC4_MASK (0xfull << CHA_ID_LS_ARC4_SHIFT)
146 #define CHA_ID_LS_MD_SHIFT 12
147 #define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT)
149 #define CHA_ID_LS_RNG_SHIFT 16
150 #define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT)
152 #define CHA_ID_LS_SNW8_SHIFT 20
153 #define CHA_ID_LS_SNW8_MASK (0xfull << CHA_ID_LS_SNW8_SHIFT)
155 #define CHA_ID_LS_KAS_SHIFT 24
156 #define CHA_ID_LS_KAS_MASK (0xfull << CHA_ID_LS_KAS_SHIFT)
158 #define CHA_ID_LS_PK_SHIFT 28
159 #define CHA_ID_LS_PK_MASK (0xfull << CHA_ID_LS_PK_SHIFT)
161 #define CHA_ID_MS_CRC_SHIFT 0
162 #define CHA_ID_MS_CRC_MASK (0xfull << CHA_ID_MS_CRC_SHIFT)
164 #define CHA_ID_MS_SNW9_SHIFT 4
165 #define CHA_ID_MS_SNW9_MASK (0xfull << CHA_ID_MS_SNW9_SHIFT)
167 #define CHA_ID_MS_DECO_SHIFT 24
168 #define CHA_ID_MS_DECO_MASK (0xfull << CHA_ID_MS_DECO_SHIFT)
170 #define CHA_ID_MS_JR_SHIFT 28
171 #define CHA_ID_MS_JR_MASK (0xfull << CHA_ID_MS_JR_SHIFT)
179 struct caam_perfmon {
180 /* Performance Monitor Registers f00-f9f */
181 u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */
182 u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */
183 u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests */
184 u64 ob_enc_bytes; /* PC_OB_ENCRYPT - Outbound Bytes Encrypted */
185 u64 ob_prot_bytes; /* PC_OB_PROTECT - Outbound Bytes Protected */
186 u64 ib_dec_bytes; /* PC_IB_DECRYPT - Inbound Bytes Decrypted */
187 u64 ib_valid_bytes; /* PC_IB_VALIDATED Inbound Bytes Validated */
190 /* CAAM Hardware Instantiation Parameters fa0-fbf */
191 u32 cha_rev_ms; /* CRNR - CHA Rev No. Most significant half*/
192 u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/
193 #define CTPR_MS_QI_SHIFT 25
194 #define CTPR_MS_QI_MASK (0x1ull << CTPR_MS_QI_SHIFT)
195 #define CTPR_MS_VIRT_EN_INCL 0x00000001
196 #define CTPR_MS_VIRT_EN_POR 0x00000002
197 u32 comp_parms_ms; /* CTPR - Compile Parameters Register */
198 u32 comp_parms_ls; /* CTPR - Compile Parameters Register */
201 /* CAAM Global Status fc0-fdf */
202 u64 faultaddr; /* FAR - Fault Address */
203 u32 faultliodn; /* FALR - Fault Address LIODN */
204 u32 faultdetail; /* FADR - Fault Addr Detail */
206 u32 status; /* CSTA - CAAM Status */
209 /* Component Instantiation Parameters fe0-fff */
210 u32 rtic_id; /* RVID - RTIC Version ID */
211 u32 ccb_id; /* CCBVID - CCB Version ID */
212 u32 cha_id_ms; /* CHAVID - CHA Version ID Most Significant*/
213 u32 cha_id_ls; /* CHAVID - CHA Version ID Least Significant*/
214 u32 cha_num_ms; /* CHANUM - CHA Number Most Significant */
215 u32 cha_num_ls; /* CHANUM - CHA Number Least Significant*/
216 u32 caam_id_ms; /* CAAMVID - CAAM Version ID MS */
217 u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */
220 /* LIODN programming for DMA configuration */
221 #define MSTRID_LOCK_LIODN 0x80000000
222 #define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */
224 #define MSTRID_LIODN_MASK 0x0fff
226 u32 liodn_ms; /* lock and make-trusted control bits */
227 u32 liodn_ls; /* LIODN for non-sequence and seq access */
230 /* Partition ID for DMA configuration */
233 u32 pidr; /* partition ID, DECO */
236 /* RNGB test mode (replicated twice in some configurations) */
237 /* Padded out to 0x100 */
239 u32 mode; /* RTSTMODEx - Test mode */
241 u32 reset; /* RTSTRESETx - Test reset control */
243 u32 status; /* RTSTSSTATUSx - Test status */
245 u32 errstat; /* RTSTERRSTATx - Test error status */
247 u32 errctl; /* RTSTERRCTLx - Test error control */
249 u32 entropy; /* RTSTENTROPYx - Test entropy */
251 u32 verifctl; /* RTSTVERIFCTLx - Test verification control */
253 u32 verifstat; /* RTSTVERIFSTATx - Test verification status */
255 u32 verifdata; /* RTSTVERIFDx - Test verification data */
257 u32 xkey; /* RTSTXKEYx - Test XKEY */
259 u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */
261 u32 oscct; /* RTSTOSCCTx - Test oscillator counter */
263 u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */
265 u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */
269 /* RNG4 TRNG test registers */
271 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
272 u32 rtmctl; /* misc. control register */
273 u32 rtscmisc; /* statistical check misc. register */
274 u32 rtpkrrng; /* poker range register */
276 u32 rtpkrmax; /* PRGM=1: poker max. limit register */
277 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
279 #define RTSDCTL_ENT_DLY_SHIFT 16
280 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
281 #define RTSDCTL_ENT_DLY_MIN 1200
282 #define RTSDCTL_ENT_DLY_MAX 12800
283 u32 rtsdctl; /* seed control register */
285 u32 rtsblim; /* PRGM=1: sparse bit limit register */
286 u32 rttotsam; /* PRGM=0: total samples register */
288 u32 rtfrqmin; /* frequency count min. limit register */
290 u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */
291 u32 rtfrqcnt; /* PRGM=0: freq. count register */
294 #define RDSTA_SKVT 0x80000000
295 #define RDSTA_SKVN 0x40000000
296 #define RDSTA_IF0 0x00000001
297 #define RDSTA_IF1 0x00000002
298 #define RDSTA_IFMASK (RDSTA_IF1 | RDSTA_IF0)
304 * caam_ctrl - basic core configuration
305 * starts base + 0x0000 padded out to 0x1000
308 #define KEK_KEY_SIZE 8
309 #define TKEK_KEY_SIZE 8
310 #define TDSK_KEY_SIZE 8
312 #define DECO_RESET 1 /* Use with DECO reset/availability regs */
313 #define DECO_RESET_0 (DECO_RESET << 0)
314 #define DECO_RESET_1 (DECO_RESET << 1)
315 #define DECO_RESET_2 (DECO_RESET << 2)
316 #define DECO_RESET_3 (DECO_RESET << 3)
317 #define DECO_RESET_4 (DECO_RESET << 4)
320 /* Basic Configuration Section 000-01f */
323 u32 mcr; /* MCFG Master Config Register */
325 u32 scfgr; /* SCFGR, Security Config Register */
327 /* Bus Access Configuration Section 010-11f */
329 struct masterid jr_mid[4]; /* JRxLIODNR - JobR LIODN setup */
331 u32 jrstart; /* JRSTART - Job Ring Start Register */
332 struct masterid rtic_mid[4]; /* RTICxLIODNR - RTIC LIODN setup */
334 u32 deco_rsr; /* DECORSR - Deco Request Source */
336 u32 deco_rq; /* DECORR - DECO Request */
337 struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */
340 /* DECO Availability/Reset Section 120-3ff */
341 u32 deco_avail; /* DAR - DECO availability */
342 u32 deco_reset; /* DRR - DECO reset */
345 /* Key Encryption/Decryption Configuration 400-5ff */
346 /* Read/Writable only while in Non-secure mode */
347 u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */
348 u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */
349 u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */
351 u64 sknonce; /* SKNR - Secure Key Nonce */
354 /* RNG Test/Verification/Debug Access 600-7ff */
355 /* (Useful in Test/Debug modes only...) */
357 struct rngtst rtst[2];
358 struct rng4tst r4tst[2];
363 /* Performance Monitor f00-fff */
364 struct caam_perfmon perfmon;
368 * Controller master config register defs
370 #define MCFGR_SWRESET 0x80000000 /* software reset */
371 #define MCFGR_WDENABLE 0x40000000 /* DECO watchdog enable */
372 #define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */
373 #define MCFGR_DMA_RESET 0x10000000
374 #define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */
375 #define SCFGR_RDBENABLE 0x00000400
376 #define SCFGR_VIRT_EN 0x00008000
377 #define DECORR_RQD0ENABLE 0x00000001 /* Enable DECO0 for direct access */
378 #define DECORSR_JR0 0x00000001 /* JR to supply TZ, SDID, ICID */
379 #define DECORSR_VALID 0x80000000
380 #define DECORR_DEN0 0x00010000 /* DECO0 available for access*/
382 /* AXI read cache control */
383 #define MCFGR_ARCACHE_SHIFT 12
384 #define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT)
386 /* AXI write cache control */
387 #define MCFGR_AWCACHE_SHIFT 8
388 #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT)
390 /* AXI pipeline depth */
391 #define MCFGR_AXIPIPE_SHIFT 4
392 #define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT)
394 #define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */
395 #define MCFGR_BURST_64 0x00000001 /* Max burst size */
397 /* JRSTART register offsets */
398 #define JRSTART_JR0_START 0x00000001 /* Start Job ring 0 */
399 #define JRSTART_JR1_START 0x00000002 /* Start Job ring 1 */
400 #define JRSTART_JR2_START 0x00000004 /* Start Job ring 2 */
401 #define JRSTART_JR3_START 0x00000008 /* Start Job ring 3 */
404 * caam_job_ring - direct job ring setup
405 * 1-4 possible per instantiation, base + 1000/2000/3000/4000
406 * Padded out to 0x1000
408 struct caam_job_ring {
410 u64 inpring_base; /* IRBAx - Input desc ring baseaddr */
412 u32 inpring_size; /* IRSx - Input ring size */
414 u32 inpring_avail; /* IRSAx - Input ring room remaining */
416 u32 inpring_jobadd; /* IRJAx - Input ring jobs added */
419 u64 outring_base; /* ORBAx - Output status ring base addr */
421 u32 outring_size; /* ORSx - Output ring size */
423 u32 outring_rmvd; /* ORJRx - Output ring jobs removed */
425 u32 outring_used; /* ORSFx - Output ring slots full */
427 /* Status/Configuration */
429 u32 jroutstatus; /* JRSTAx - JobR output status */
431 u32 jrintstatus; /* JRINTx - JobR interrupt status */
432 u32 rconfig_hi; /* JRxCFG - Ring configuration */
435 /* Indices. CAAM maintains as "heads" of each queue */
437 u32 inp_rdidx; /* IRRIx - Input ring read index */
439 u32 out_wtidx; /* ORWIx - Output ring write index */
441 /* Command/control */
443 u32 jrcommand; /* JRCRx - JobR command */
447 /* Performance Monitor f00-fff */
448 struct caam_perfmon perfmon;
451 #define JR_RINGSIZE_MASK 0x03ff
453 * jrstatus - Job Ring Output Status
454 * All values in lo word
455 * Also note, same values written out as status through QI
456 * in the command/status field of a frame descriptor
458 #define JRSTA_SSRC_SHIFT 28
459 #define JRSTA_SSRC_MASK 0xf0000000
461 #define JRSTA_SSRC_NONE 0x00000000
462 #define JRSTA_SSRC_CCB_ERROR 0x20000000
463 #define JRSTA_SSRC_JUMP_HALT_USER 0x30000000
464 #define JRSTA_SSRC_DECO 0x40000000
465 #define JRSTA_SSRC_JRERROR 0x60000000
466 #define JRSTA_SSRC_JUMP_HALT_CC 0x70000000
468 #define JRSTA_DECOERR_JUMP 0x08000000
469 #define JRSTA_DECOERR_INDEX_SHIFT 8
470 #define JRSTA_DECOERR_INDEX_MASK 0xff00
471 #define JRSTA_DECOERR_ERROR_MASK 0x00ff
473 #define JRSTA_DECOERR_NONE 0x00
474 #define JRSTA_DECOERR_LINKLEN 0x01
475 #define JRSTA_DECOERR_LINKPTR 0x02
476 #define JRSTA_DECOERR_JRCTRL 0x03
477 #define JRSTA_DECOERR_DESCCMD 0x04
478 #define JRSTA_DECOERR_ORDER 0x05
479 #define JRSTA_DECOERR_KEYCMD 0x06
480 #define JRSTA_DECOERR_LOADCMD 0x07
481 #define JRSTA_DECOERR_STORECMD 0x08
482 #define JRSTA_DECOERR_OPCMD 0x09
483 #define JRSTA_DECOERR_FIFOLDCMD 0x0a
484 #define JRSTA_DECOERR_FIFOSTCMD 0x0b
485 #define JRSTA_DECOERR_MOVECMD 0x0c
486 #define JRSTA_DECOERR_JUMPCMD 0x0d
487 #define JRSTA_DECOERR_MATHCMD 0x0e
488 #define JRSTA_DECOERR_SHASHCMD 0x0f
489 #define JRSTA_DECOERR_SEQCMD 0x10
490 #define JRSTA_DECOERR_DECOINTERNAL 0x11
491 #define JRSTA_DECOERR_SHDESCHDR 0x12
492 #define JRSTA_DECOERR_HDRLEN 0x13
493 #define JRSTA_DECOERR_BURSTER 0x14
494 #define JRSTA_DECOERR_DESCSIGNATURE 0x15
495 #define JRSTA_DECOERR_DMA 0x16
496 #define JRSTA_DECOERR_BURSTFIFO 0x17
497 #define JRSTA_DECOERR_JRRESET 0x1a
498 #define JRSTA_DECOERR_JOBFAIL 0x1b
499 #define JRSTA_DECOERR_DNRERR 0x80
500 #define JRSTA_DECOERR_UNDEFPCL 0x81
501 #define JRSTA_DECOERR_PDBERR 0x82
502 #define JRSTA_DECOERR_ANRPLY_LATE 0x83
503 #define JRSTA_DECOERR_ANRPLY_REPLAY 0x84
504 #define JRSTA_DECOERR_SEQOVF 0x85
505 #define JRSTA_DECOERR_INVSIGN 0x86
506 #define JRSTA_DECOERR_DSASIGN 0x87
508 #define JRSTA_CCBERR_JUMP 0x08000000
509 #define JRSTA_CCBERR_INDEX_MASK 0xff00
510 #define JRSTA_CCBERR_INDEX_SHIFT 8
511 #define JRSTA_CCBERR_CHAID_MASK 0x00f0
512 #define JRSTA_CCBERR_CHAID_SHIFT 4
513 #define JRSTA_CCBERR_ERRID_MASK 0x000f
515 #define JRSTA_CCBERR_CHAID_AES (0x01 << JRSTA_CCBERR_CHAID_SHIFT)
516 #define JRSTA_CCBERR_CHAID_DES (0x02 << JRSTA_CCBERR_CHAID_SHIFT)
517 #define JRSTA_CCBERR_CHAID_ARC4 (0x03 << JRSTA_CCBERR_CHAID_SHIFT)
518 #define JRSTA_CCBERR_CHAID_MD (0x04 << JRSTA_CCBERR_CHAID_SHIFT)
519 #define JRSTA_CCBERR_CHAID_RNG (0x05 << JRSTA_CCBERR_CHAID_SHIFT)
520 #define JRSTA_CCBERR_CHAID_SNOW (0x06 << JRSTA_CCBERR_CHAID_SHIFT)
521 #define JRSTA_CCBERR_CHAID_KASUMI (0x07 << JRSTA_CCBERR_CHAID_SHIFT)
522 #define JRSTA_CCBERR_CHAID_PK (0x08 << JRSTA_CCBERR_CHAID_SHIFT)
523 #define JRSTA_CCBERR_CHAID_CRC (0x09 << JRSTA_CCBERR_CHAID_SHIFT)
525 #define JRSTA_CCBERR_ERRID_NONE 0x00
526 #define JRSTA_CCBERR_ERRID_MODE 0x01
527 #define JRSTA_CCBERR_ERRID_DATASIZ 0x02
528 #define JRSTA_CCBERR_ERRID_KEYSIZ 0x03
529 #define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04
530 #define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05
531 #define JRSTA_CCBERR_ERRID_SEQUENCE 0x06
532 #define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07
533 #define JRSTA_CCBERR_ERRID_PKMODEVN 0x08
534 #define JRSTA_CCBERR_ERRID_KEYPARIT 0x09
535 #define JRSTA_CCBERR_ERRID_ICVCHK 0x0a
536 #define JRSTA_CCBERR_ERRID_HARDWARE 0x0b
537 #define JRSTA_CCBERR_ERRID_CCMAAD 0x0c
538 #define JRSTA_CCBERR_ERRID_INVCHA 0x0f
540 #define JRINT_ERR_INDEX_MASK 0x3fff0000
541 #define JRINT_ERR_INDEX_SHIFT 16
542 #define JRINT_ERR_TYPE_MASK 0xf00
543 #define JRINT_ERR_TYPE_SHIFT 8
544 #define JRINT_ERR_HALT_MASK 0xc
545 #define JRINT_ERR_HALT_SHIFT 2
546 #define JRINT_ERR_HALT_INPROGRESS 0x4
547 #define JRINT_ERR_HALT_COMPLETE 0x8
548 #define JRINT_JR_ERROR 0x02
549 #define JRINT_JR_INT 0x01
551 #define JRINT_ERR_TYPE_WRITE 1
552 #define JRINT_ERR_TYPE_BAD_INPADDR 3
553 #define JRINT_ERR_TYPE_BAD_OUTADDR 4
554 #define JRINT_ERR_TYPE_INV_INPWRT 5
555 #define JRINT_ERR_TYPE_INV_OUTWRT 6
556 #define JRINT_ERR_TYPE_RESET 7
557 #define JRINT_ERR_TYPE_REMOVE_OFL 8
558 #define JRINT_ERR_TYPE_ADD_OFL 9
560 #define JRCFG_SOE 0x04
561 #define JRCFG_ICEN 0x02
562 #define JRCFG_IMSK 0x01
563 #define JRCFG_ICDCT_SHIFT 8
564 #define JRCFG_ICTT_SHIFT 16
566 #define JRCR_RESET 0x01
569 * caam_assurance - Assurance Controller View
570 * base + 0x6000 padded out to 0x1000
573 struct rtic_element {
580 struct rtic_element element[2];
583 struct rtic_memhash {
588 struct caam_assurance {
589 /* Status/Command/Watchdog */
591 u32 status; /* RSTA - Status */
593 u32 cmd; /* RCMD - Command */
595 u32 ctrl; /* RCTL - Control */
597 u32 throttle; /* RTHR - Throttle */
599 u64 watchdog; /* RWDOG - Watchdog Timer */
601 u32 rend; /* REND - Endian corrections */
604 /* Block access/configuration @ 100/110/120/130 */
605 struct rtic_block memblk[4]; /* Memory Blocks A-D */
608 /* Block hashes @ 200/300/400/500 */
609 struct rtic_memhash hash[4]; /* Block hash values A-D */
614 * caam_queue_if - QI configuration and control
615 * starts base + 0x7000, padded out to 0x1000 long
618 struct caam_queue_if {
619 u32 qi_control_hi; /* QICTL - QI Control */
622 u32 qi_status; /* QISTA - QI Status */
623 u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */
625 u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */
630 /* QI control bits - low word */
631 #define QICTL_DQEN 0x01 /* Enable frame pop */
632 #define QICTL_STOP 0x02 /* Stop dequeue/enqueue */
633 #define QICTL_SOE 0x04 /* Stop on error */
635 /* QI control bits - high word */
636 #define QICTL_MBSI 0x01
637 #define QICTL_MHWSI 0x02
638 #define QICTL_MWSI 0x04
639 #define QICTL_MDWSI 0x08
640 #define QICTL_CBSI 0x10 /* CtrlDataByteSwapInput */
641 #define QICTL_CHWSI 0x20 /* CtrlDataHalfSwapInput */
642 #define QICTL_CWSI 0x40 /* CtrlDataWordSwapInput */
643 #define QICTL_CDWSI 0x80 /* CtrlDataDWordSwapInput */
644 #define QICTL_MBSO 0x0100
645 #define QICTL_MHWSO 0x0200
646 #define QICTL_MWSO 0x0400
647 #define QICTL_MDWSO 0x0800
648 #define QICTL_CBSO 0x1000 /* CtrlDataByteSwapOutput */
649 #define QICTL_CHWSO 0x2000 /* CtrlDataHalfSwapOutput */
650 #define QICTL_CWSO 0x4000 /* CtrlDataWordSwapOutput */
651 #define QICTL_CDWSO 0x8000 /* CtrlDataDWordSwapOutput */
652 #define QICTL_DMBS 0x010000
653 #define QICTL_EPO 0x020000
656 #define QISTA_PHRDERR 0x01 /* PreHeader Read Error */
657 #define QISTA_CFRDERR 0x02 /* Compound Frame Read Error */
658 #define QISTA_OFWRERR 0x04 /* Output Frame Read Error */
659 #define QISTA_BPDERR 0x08 /* Buffer Pool Depleted */
660 #define QISTA_BTSERR 0x10 /* Buffer Undersize */
661 #define QISTA_CFWRERR 0x20 /* Compound Frame Write Err */
662 #define QISTA_STOPD 0x80000000 /* QI Stopped (see QICTL) */
664 /* deco_sg_table - DECO view of scatter/gather table */
665 struct deco_sg_table {
666 u64 addr; /* Segment Address */
667 u32 elen; /* E, F bits + 30-bit length */
668 u32 bpid_offset; /* Buffer Pool ID + 16-bit length */
672 * caam_deco - descriptor controller - CHA cluster block
674 * Only accessible when direct DECO access is turned on
675 * (done in DECORR, via MID programmed in DECOxMID
677 * 5 typical, base + 0x8000/9000/a000/b000
678 * Padded out to 0x1000 long
682 u32 cls1_mode; /* CxC1MR - Class 1 Mode */
684 u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */
685 u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */
686 u32 cls1_datasize_lo;
688 u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */
690 u32 cha_ctrl; /* CCTLR - CHA control */
692 u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */
694 u32 clr_written; /* CxCWR - Clear-Written */
695 u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */
698 u32 aad_size; /* CxAADSZR - Current AAD Size */
700 u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */
702 u32 pkha_a_size; /* PKASZRx - Size of PKHA A */
704 u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */
706 u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */
708 u32 pkha_e_size; /* PKESZRx - Size of PKHA E */
710 u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */
712 u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */
714 u32 cls2_mode; /* CxC2MR - Class 2 Mode */
716 u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */
717 u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */
718 u32 cls2_datasize_lo;
720 u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */
722 u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */
724 u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */
726 u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */
729 u64 inp_datafifo; /* CxDFIFO - Input Data FIFO */
731 u64 out_datafifo; /* CxOFIFO - Output Data FIFO */
733 u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */
735 u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */
736 #define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF
737 u32 op_status_hi; /* DxOPSTA - DECO Operation Status */
740 u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */
741 u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */
743 u64 math[4]; /* DxMTH - Math register */
745 struct deco_sg_table gthr_tbl[4]; /* DxGTR - Gather Tables */
747 struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */
749 u32 descbuf[64]; /* DxDESB - Descriptor buffer */
751 #define DESC_DBG_DECO_STAT_HOST_ERR 0x00D00000
752 #define DESC_DBG_DECO_STAT_VALID 0x80000000
753 #define DESC_DBG_DECO_STAT_MASK 0x00F00000
754 u32 desc_dbg; /* DxDDR - DECO Debug Register */
758 #define DECO_JQCR_WHL 0x20000000
759 #define DECO_JQCR_FOUR 0x10000000
762 * Current top-level view of memory map is:
764 * 0x0000 - 0x0fff - CAAM Top-Level Control
765 * 0x1000 - 0x1fff - Job Ring 0
766 * 0x2000 - 0x2fff - Job Ring 1
767 * 0x3000 - 0x3fff - Job Ring 2
768 * 0x4000 - 0x4fff - Job Ring 3
769 * 0x5000 - 0x5fff - (unused)
770 * 0x6000 - 0x6fff - Assurance Controller
771 * 0x7000 - 0x7fff - Queue Interface
772 * 0x8000 - 0x8fff - DECO-CCB 0
773 * 0x9000 - 0x9fff - DECO-CCB 1
774 * 0xa000 - 0xafff - DECO-CCB 2
775 * 0xb000 - 0xbfff - DECO-CCB 3
776 * 0xc000 - 0xcfff - DECO-CCB 4
778 * caam_full describes the full register view of CAAM if useful,
779 * although many configurations may choose to implement parts of
780 * the register map separately, in differing privilege regions
783 struct caam_ctrl __iomem ctrl;
784 struct caam_job_ring jr[4];
786 struct caam_assurance assure;
787 struct caam_queue_if qi;
788 struct caam_deco deco;