2 * Support for Marvell's crypto engine which can be found on some Orion5X
5 * Author: Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
9 #include <crypto/aes.h>
10 #include <crypto/algapi.h>
11 #include <linux/crypto.h>
12 #include <linux/interrupt.h>
14 #include <linux/kthread.h>
15 #include <linux/platform_device.h>
16 #include <linux/scatterlist.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/clk.h>
20 #include <crypto/internal/hash.h>
21 #include <crypto/sha.h>
25 #define MV_CESA "MV-CESA:"
26 #define MAX_HW_HASH_SIZE 0xFFFF
27 #define MV_CESA_EXPIRE 500 /* msec */
31 * /---------------------------------------\
32 * | | request complete
34 * IDLE -> new request -> BUSY -> done -> DEQUEUE
36 * | | more scatter entries
46 * struct req_progress - used for every crypt request
47 * @src_sg_it: sg iterator for src
48 * @dst_sg_it: sg iterator for dst
49 * @sg_src_left: bytes left in src to process (scatter list)
50 * @src_start: offset to add to src start position (scatter list)
51 * @crypt_len: length of current hw crypt/hash process
52 * @hw_nbytes: total bytes to process in hw for this request
53 * @copy_back: whether to copy data back (crypt) or not (hash)
54 * @sg_dst_left: bytes left dst to process in this scatter list
55 * @dst_start: offset to add to dst start position (scatter list)
56 * @hw_processed_bytes: number of bytes processed by hw (request).
58 * sg helper are used to iterate over the scatterlist. Since the size of the
59 * SRAM may be less than the scatter size, this struct struct is used to keep
60 * track of progress within current scatterlist.
63 struct sg_mapping_iter src_sg_it;
64 struct sg_mapping_iter dst_sg_it;
65 void (*complete) (void);
66 void (*process) (int is_first);
77 int hw_processed_bytes;
85 struct task_struct *queue_th;
87 /* the lock protects queue and eng_st */
89 struct crypto_queue queue;
90 enum engine_status eng_st;
91 struct timer_list completion_timer;
92 struct crypto_async_request *cur_req;
93 struct req_progress p;
100 static struct crypto_priv *cpg;
103 u8 aes_enc_key[AES_KEY_LEN];
106 u32 need_calc_aes_dkey;
124 struct mv_tfm_hash_ctx {
125 struct crypto_shash *fallback;
126 struct crypto_shash *base_hash;
127 u32 ivs[2 * SHA1_DIGEST_SIZE / 4];
132 struct mv_req_hash_ctx {
134 u32 state[SHA1_DIGEST_SIZE / 4];
135 u8 buffer[SHA1_BLOCK_SIZE];
136 int first_hash; /* marks that we don't have previous state */
137 int last_chunk; /* marks that this is the 'final' request */
138 int extra_bytes; /* unprocessed bytes in buffer */
143 static void mv_completion_timer_callback(unsigned long unused)
145 int active = readl(cpg->reg + SEC_ACCEL_CMD) & SEC_CMD_EN_SEC_ACCL0;
147 printk(KERN_ERR MV_CESA
148 "completion timer expired (CESA %sactive), cleaning up.\n",
151 del_timer(&cpg->completion_timer);
152 writel(SEC_CMD_DISABLE_SEC, cpg->reg + SEC_ACCEL_CMD);
153 while(readl(cpg->reg + SEC_ACCEL_CMD) & SEC_CMD_DISABLE_SEC)
154 printk(KERN_INFO MV_CESA "%s: waiting for engine finishing\n", __func__);
155 cpg->eng_st = ENGINE_W_DEQUEUE;
156 wake_up_process(cpg->queue_th);
159 static void mv_setup_timer(void)
161 setup_timer(&cpg->completion_timer, &mv_completion_timer_callback, 0);
162 mod_timer(&cpg->completion_timer,
163 jiffies + msecs_to_jiffies(MV_CESA_EXPIRE));
166 static void compute_aes_dec_key(struct mv_ctx *ctx)
168 struct crypto_aes_ctx gen_aes_key;
171 if (!ctx->need_calc_aes_dkey)
174 crypto_aes_expand_key(&gen_aes_key, ctx->aes_enc_key, ctx->key_len);
176 key_pos = ctx->key_len + 24;
177 memcpy(ctx->aes_dec_key, &gen_aes_key.key_enc[key_pos], 4 * 4);
178 switch (ctx->key_len) {
179 case AES_KEYSIZE_256:
182 case AES_KEYSIZE_192:
184 memcpy(&ctx->aes_dec_key[4], &gen_aes_key.key_enc[key_pos],
188 ctx->need_calc_aes_dkey = 0;
191 static int mv_setkey_aes(struct crypto_ablkcipher *cipher, const u8 *key,
194 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
195 struct mv_ctx *ctx = crypto_tfm_ctx(tfm);
198 case AES_KEYSIZE_128:
199 case AES_KEYSIZE_192:
200 case AES_KEYSIZE_256:
203 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
207 ctx->need_calc_aes_dkey = 1;
209 memcpy(ctx->aes_enc_key, key, AES_KEY_LEN);
213 static void copy_src_to_buf(struct req_progress *p, char *dbuf, int len)
220 if (!p->sg_src_left) {
221 ret = sg_miter_next(&p->src_sg_it);
223 p->sg_src_left = p->src_sg_it.length;
227 sbuf = p->src_sg_it.addr + p->src_start;
229 copy_len = min(p->sg_src_left, len);
230 memcpy(dbuf, sbuf, copy_len);
232 p->src_start += copy_len;
233 p->sg_src_left -= copy_len;
240 static void setup_data_in(void)
242 struct req_progress *p = &cpg->p;
244 min(p->hw_nbytes - p->hw_processed_bytes, cpg->max_req_size);
245 copy_src_to_buf(p, cpg->sram + SRAM_DATA_IN_START + p->crypt_len,
246 data_in_sram - p->crypt_len);
247 p->crypt_len = data_in_sram;
250 static void mv_process_current_q(int first_block)
252 struct ablkcipher_request *req = ablkcipher_request_cast(cpg->cur_req);
253 struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
254 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
255 struct sec_accel_config op;
257 switch (req_ctx->op) {
259 op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_ECB;
263 op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_CBC;
264 op.enc_iv = ENC_IV_POINT(SRAM_DATA_IV) |
265 ENC_IV_BUF_POINT(SRAM_DATA_IV_BUF);
267 memcpy(cpg->sram + SRAM_DATA_IV, req->info, 16);
270 if (req_ctx->decrypt) {
271 op.config |= CFG_DIR_DEC;
272 memcpy(cpg->sram + SRAM_DATA_KEY_P, ctx->aes_dec_key,
275 op.config |= CFG_DIR_ENC;
276 memcpy(cpg->sram + SRAM_DATA_KEY_P, ctx->aes_enc_key,
280 switch (ctx->key_len) {
281 case AES_KEYSIZE_128:
282 op.config |= CFG_AES_LEN_128;
284 case AES_KEYSIZE_192:
285 op.config |= CFG_AES_LEN_192;
287 case AES_KEYSIZE_256:
288 op.config |= CFG_AES_LEN_256;
291 op.enc_p = ENC_P_SRC(SRAM_DATA_IN_START) |
292 ENC_P_DST(SRAM_DATA_OUT_START);
293 op.enc_key_p = SRAM_DATA_KEY_P;
296 op.enc_len = cpg->p.crypt_len;
297 memcpy(cpg->sram + SRAM_CONFIG, &op,
298 sizeof(struct sec_accel_config));
302 writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD);
305 static void mv_crypto_algo_completion(void)
307 struct ablkcipher_request *req = ablkcipher_request_cast(cpg->cur_req);
308 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
310 sg_miter_stop(&cpg->p.src_sg_it);
311 sg_miter_stop(&cpg->p.dst_sg_it);
313 if (req_ctx->op != COP_AES_CBC)
316 memcpy(req->info, cpg->sram + SRAM_DATA_IV_BUF, 16);
319 static void mv_process_hash_current(int first_block)
321 struct ahash_request *req = ahash_request_cast(cpg->cur_req);
322 const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
323 struct mv_req_hash_ctx *req_ctx = ahash_request_ctx(req);
324 struct req_progress *p = &cpg->p;
325 struct sec_accel_config op = { 0 };
328 switch (req_ctx->op) {
331 op.config = CFG_OP_MAC_ONLY | CFG_MACM_SHA1;
334 op.config = CFG_OP_MAC_ONLY | CFG_MACM_HMAC_SHA1;
335 memcpy(cpg->sram + SRAM_HMAC_IV_IN,
336 tfm_ctx->ivs, sizeof(tfm_ctx->ivs));
341 MAC_SRC_DATA_P(SRAM_DATA_IN_START) | MAC_SRC_TOTAL_LEN((u32)
348 MAC_DIGEST_P(SRAM_DIGEST_BUF) | MAC_FRAG_LEN(p->crypt_len);
350 MAC_INNER_IV_P(SRAM_HMAC_IV_IN) |
351 MAC_OUTER_IV_P(SRAM_HMAC_IV_OUT);
353 is_last = req_ctx->last_chunk
354 && (p->hw_processed_bytes + p->crypt_len >= p->hw_nbytes)
355 && (req_ctx->count <= MAX_HW_HASH_SIZE);
356 if (req_ctx->first_hash) {
358 op.config |= CFG_NOT_FRAG;
360 op.config |= CFG_FIRST_FRAG;
362 req_ctx->first_hash = 0;
365 op.config |= CFG_LAST_FRAG;
367 op.config |= CFG_MID_FRAG;
370 writel(req_ctx->state[0], cpg->reg + DIGEST_INITIAL_VAL_A);
371 writel(req_ctx->state[1], cpg->reg + DIGEST_INITIAL_VAL_B);
372 writel(req_ctx->state[2], cpg->reg + DIGEST_INITIAL_VAL_C);
373 writel(req_ctx->state[3], cpg->reg + DIGEST_INITIAL_VAL_D);
374 writel(req_ctx->state[4], cpg->reg + DIGEST_INITIAL_VAL_E);
378 memcpy(cpg->sram + SRAM_CONFIG, &op, sizeof(struct sec_accel_config));
382 writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD);
385 static inline int mv_hash_import_sha1_ctx(const struct mv_req_hash_ctx *ctx,
386 struct shash_desc *desc)
389 struct sha1_state shash_state;
391 shash_state.count = ctx->count + ctx->count_add;
392 for (i = 0; i < 5; i++)
393 shash_state.state[i] = ctx->state[i];
394 memcpy(shash_state.buffer, ctx->buffer, sizeof(shash_state.buffer));
395 return crypto_shash_import(desc, &shash_state);
398 static int mv_hash_final_fallback(struct ahash_request *req)
400 const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
401 struct mv_req_hash_ctx *req_ctx = ahash_request_ctx(req);
403 struct shash_desc shash;
404 char ctx[crypto_shash_descsize(tfm_ctx->fallback)];
408 desc.shash.tfm = tfm_ctx->fallback;
409 desc.shash.flags = CRYPTO_TFM_REQ_MAY_SLEEP;
410 if (unlikely(req_ctx->first_hash)) {
411 crypto_shash_init(&desc.shash);
412 crypto_shash_update(&desc.shash, req_ctx->buffer,
413 req_ctx->extra_bytes);
415 /* only SHA1 for now....
417 rc = mv_hash_import_sha1_ctx(req_ctx, &desc.shash);
421 rc = crypto_shash_final(&desc.shash, req->result);
426 static void mv_hash_algo_completion(void)
428 struct ahash_request *req = ahash_request_cast(cpg->cur_req);
429 struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
431 if (ctx->extra_bytes)
432 copy_src_to_buf(&cpg->p, ctx->buffer, ctx->extra_bytes);
433 sg_miter_stop(&cpg->p.src_sg_it);
435 if (likely(ctx->last_chunk)) {
436 if (likely(ctx->count <= MAX_HW_HASH_SIZE)) {
437 memcpy(req->result, cpg->sram + SRAM_DIGEST_BUF,
438 crypto_ahash_digestsize(crypto_ahash_reqtfm
441 mv_hash_final_fallback(req);
443 ctx->state[0] = readl(cpg->reg + DIGEST_INITIAL_VAL_A);
444 ctx->state[1] = readl(cpg->reg + DIGEST_INITIAL_VAL_B);
445 ctx->state[2] = readl(cpg->reg + DIGEST_INITIAL_VAL_C);
446 ctx->state[3] = readl(cpg->reg + DIGEST_INITIAL_VAL_D);
447 ctx->state[4] = readl(cpg->reg + DIGEST_INITIAL_VAL_E);
451 static void dequeue_complete_req(void)
453 struct crypto_async_request *req = cpg->cur_req;
456 cpg->p.hw_processed_bytes += cpg->p.crypt_len;
457 if (cpg->p.copy_back) {
458 int need_copy_len = cpg->p.crypt_len;
463 if (!cpg->p.sg_dst_left) {
464 ret = sg_miter_next(&cpg->p.dst_sg_it);
466 cpg->p.sg_dst_left = cpg->p.dst_sg_it.length;
467 cpg->p.dst_start = 0;
470 buf = cpg->p.dst_sg_it.addr;
471 buf += cpg->p.dst_start;
473 dst_copy = min(need_copy_len, cpg->p.sg_dst_left);
476 cpg->sram + SRAM_DATA_OUT_START + sram_offset,
478 sram_offset += dst_copy;
479 cpg->p.sg_dst_left -= dst_copy;
480 need_copy_len -= dst_copy;
481 cpg->p.dst_start += dst_copy;
482 } while (need_copy_len > 0);
485 cpg->p.crypt_len = 0;
487 BUG_ON(cpg->eng_st != ENGINE_W_DEQUEUE);
488 if (cpg->p.hw_processed_bytes < cpg->p.hw_nbytes) {
489 /* process next scatter list entry */
490 cpg->eng_st = ENGINE_BUSY;
494 cpg->eng_st = ENGINE_IDLE;
496 req->complete(req, 0);
501 static int count_sgs(struct scatterlist *sl, unsigned int total_bytes)
507 cur_len = sl[i].length;
509 if (total_bytes > cur_len)
510 total_bytes -= cur_len;
518 static void mv_start_new_crypt_req(struct ablkcipher_request *req)
520 struct req_progress *p = &cpg->p;
523 cpg->cur_req = &req->base;
524 memset(p, 0, sizeof(struct req_progress));
525 p->hw_nbytes = req->nbytes;
526 p->complete = mv_crypto_algo_completion;
527 p->process = mv_process_current_q;
530 num_sgs = count_sgs(req->src, req->nbytes);
531 sg_miter_start(&p->src_sg_it, req->src, num_sgs, SG_MITER_FROM_SG);
533 num_sgs = count_sgs(req->dst, req->nbytes);
534 sg_miter_start(&p->dst_sg_it, req->dst, num_sgs, SG_MITER_TO_SG);
536 mv_process_current_q(1);
539 static void mv_start_new_hash_req(struct ahash_request *req)
541 struct req_progress *p = &cpg->p;
542 struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
543 int num_sgs, hw_bytes, old_extra_bytes, rc;
544 cpg->cur_req = &req->base;
545 memset(p, 0, sizeof(struct req_progress));
546 hw_bytes = req->nbytes + ctx->extra_bytes;
547 old_extra_bytes = ctx->extra_bytes;
549 ctx->extra_bytes = hw_bytes % SHA1_BLOCK_SIZE;
550 if (ctx->extra_bytes != 0
551 && (!ctx->last_chunk || ctx->count > MAX_HW_HASH_SIZE))
552 hw_bytes -= ctx->extra_bytes;
554 ctx->extra_bytes = 0;
556 num_sgs = count_sgs(req->src, req->nbytes);
557 sg_miter_start(&p->src_sg_it, req->src, num_sgs, SG_MITER_FROM_SG);
560 p->hw_nbytes = hw_bytes;
561 p->complete = mv_hash_algo_completion;
562 p->process = mv_process_hash_current;
564 if (unlikely(old_extra_bytes)) {
565 memcpy(cpg->sram + SRAM_DATA_IN_START, ctx->buffer,
567 p->crypt_len = old_extra_bytes;
570 mv_process_hash_current(1);
572 copy_src_to_buf(p, ctx->buffer + old_extra_bytes,
573 ctx->extra_bytes - old_extra_bytes);
574 sg_miter_stop(&p->src_sg_it);
576 rc = mv_hash_final_fallback(req);
579 cpg->eng_st = ENGINE_IDLE;
581 req->base.complete(&req->base, rc);
586 static int queue_manag(void *data)
588 cpg->eng_st = ENGINE_IDLE;
590 struct crypto_async_request *async_req = NULL;
591 struct crypto_async_request *backlog;
593 __set_current_state(TASK_INTERRUPTIBLE);
595 if (cpg->eng_st == ENGINE_W_DEQUEUE)
596 dequeue_complete_req();
598 spin_lock_irq(&cpg->lock);
599 if (cpg->eng_st == ENGINE_IDLE) {
600 backlog = crypto_get_backlog(&cpg->queue);
601 async_req = crypto_dequeue_request(&cpg->queue);
603 BUG_ON(cpg->eng_st != ENGINE_IDLE);
604 cpg->eng_st = ENGINE_BUSY;
607 spin_unlock_irq(&cpg->lock);
610 backlog->complete(backlog, -EINPROGRESS);
615 if (async_req->tfm->__crt_alg->cra_type !=
616 &crypto_ahash_type) {
617 struct ablkcipher_request *req =
618 ablkcipher_request_cast(async_req);
619 mv_start_new_crypt_req(req);
621 struct ahash_request *req =
622 ahash_request_cast(async_req);
623 mv_start_new_hash_req(req);
630 } while (!kthread_should_stop());
634 static int mv_handle_req(struct crypto_async_request *req)
639 spin_lock_irqsave(&cpg->lock, flags);
640 ret = crypto_enqueue_request(&cpg->queue, req);
641 spin_unlock_irqrestore(&cpg->lock, flags);
642 wake_up_process(cpg->queue_th);
646 static int mv_enc_aes_ecb(struct ablkcipher_request *req)
648 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
650 req_ctx->op = COP_AES_ECB;
651 req_ctx->decrypt = 0;
653 return mv_handle_req(&req->base);
656 static int mv_dec_aes_ecb(struct ablkcipher_request *req)
658 struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
659 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
661 req_ctx->op = COP_AES_ECB;
662 req_ctx->decrypt = 1;
664 compute_aes_dec_key(ctx);
665 return mv_handle_req(&req->base);
668 static int mv_enc_aes_cbc(struct ablkcipher_request *req)
670 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
672 req_ctx->op = COP_AES_CBC;
673 req_ctx->decrypt = 0;
675 return mv_handle_req(&req->base);
678 static int mv_dec_aes_cbc(struct ablkcipher_request *req)
680 struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
681 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
683 req_ctx->op = COP_AES_CBC;
684 req_ctx->decrypt = 1;
686 compute_aes_dec_key(ctx);
687 return mv_handle_req(&req->base);
690 static int mv_cra_init(struct crypto_tfm *tfm)
692 tfm->crt_ablkcipher.reqsize = sizeof(struct mv_req_ctx);
696 static void mv_init_hash_req_ctx(struct mv_req_hash_ctx *ctx, int op,
697 int is_last, unsigned int req_len,
700 memset(ctx, 0, sizeof(*ctx));
702 ctx->count = req_len;
704 ctx->last_chunk = is_last;
705 ctx->count_add = count_add;
708 static void mv_update_hash_req_ctx(struct mv_req_hash_ctx *ctx, int is_last,
711 ctx->last_chunk = is_last;
712 ctx->count += req_len;
715 static int mv_hash_init(struct ahash_request *req)
717 const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
718 mv_init_hash_req_ctx(ahash_request_ctx(req), tfm_ctx->op, 0, 0,
723 static int mv_hash_update(struct ahash_request *req)
728 mv_update_hash_req_ctx(ahash_request_ctx(req), 0, req->nbytes);
729 return mv_handle_req(&req->base);
732 static int mv_hash_final(struct ahash_request *req)
734 struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
736 ahash_request_set_crypt(req, NULL, req->result, 0);
737 mv_update_hash_req_ctx(ctx, 1, 0);
738 return mv_handle_req(&req->base);
741 static int mv_hash_finup(struct ahash_request *req)
743 mv_update_hash_req_ctx(ahash_request_ctx(req), 1, req->nbytes);
744 return mv_handle_req(&req->base);
747 static int mv_hash_digest(struct ahash_request *req)
749 const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
750 mv_init_hash_req_ctx(ahash_request_ctx(req), tfm_ctx->op, 1,
751 req->nbytes, tfm_ctx->count_add);
752 return mv_handle_req(&req->base);
755 static void mv_hash_init_ivs(struct mv_tfm_hash_ctx *ctx, const void *istate,
758 const struct sha1_state *isha1_state = istate, *osha1_state = ostate;
760 for (i = 0; i < 5; i++) {
761 ctx->ivs[i] = cpu_to_be32(isha1_state->state[i]);
762 ctx->ivs[i + 5] = cpu_to_be32(osha1_state->state[i]);
766 static int mv_hash_setkey(struct crypto_ahash *tfm, const u8 * key,
770 struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(&tfm->base);
776 rc = crypto_shash_setkey(ctx->fallback, key, keylen);
780 /* Can't see a way to extract the ipad/opad from the fallback tfm
781 so I'm basically copying code from the hmac module */
782 bs = crypto_shash_blocksize(ctx->base_hash);
783 ds = crypto_shash_digestsize(ctx->base_hash);
784 ss = crypto_shash_statesize(ctx->base_hash);
788 struct shash_desc shash;
789 char ctx[crypto_shash_descsize(ctx->base_hash)];
795 desc.shash.tfm = ctx->base_hash;
796 desc.shash.flags = crypto_shash_get_flags(ctx->base_hash) &
797 CRYPTO_TFM_REQ_MAY_SLEEP;
803 crypto_shash_digest(&desc.shash, key, keylen, ipad);
809 memcpy(ipad, key, keylen);
811 memset(ipad + keylen, 0, bs - keylen);
812 memcpy(opad, ipad, bs);
814 for (i = 0; i < bs; i++) {
819 rc = crypto_shash_init(&desc.shash) ? :
820 crypto_shash_update(&desc.shash, ipad, bs) ? :
821 crypto_shash_export(&desc.shash, ipad) ? :
822 crypto_shash_init(&desc.shash) ? :
823 crypto_shash_update(&desc.shash, opad, bs) ? :
824 crypto_shash_export(&desc.shash, opad);
827 mv_hash_init_ivs(ctx, ipad, opad);
833 static int mv_cra_hash_init(struct crypto_tfm *tfm, const char *base_hash_name,
834 enum hash_op op, int count_add)
836 const char *fallback_driver_name = tfm->__crt_alg->cra_name;
837 struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(tfm);
838 struct crypto_shash *fallback_tfm = NULL;
839 struct crypto_shash *base_hash = NULL;
843 ctx->count_add = count_add;
845 /* Allocate a fallback and abort if it failed. */
846 fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
847 CRYPTO_ALG_NEED_FALLBACK);
848 if (IS_ERR(fallback_tfm)) {
849 printk(KERN_WARNING MV_CESA
850 "Fallback driver '%s' could not be loaded!\n",
851 fallback_driver_name);
852 err = PTR_ERR(fallback_tfm);
855 ctx->fallback = fallback_tfm;
857 if (base_hash_name) {
858 /* Allocate a hash to compute the ipad/opad of hmac. */
859 base_hash = crypto_alloc_shash(base_hash_name, 0,
860 CRYPTO_ALG_NEED_FALLBACK);
861 if (IS_ERR(base_hash)) {
862 printk(KERN_WARNING MV_CESA
863 "Base driver '%s' could not be loaded!\n",
865 err = PTR_ERR(base_hash);
869 ctx->base_hash = base_hash;
871 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
872 sizeof(struct mv_req_hash_ctx) +
873 crypto_shash_descsize(ctx->fallback));
876 crypto_free_shash(fallback_tfm);
881 static void mv_cra_hash_exit(struct crypto_tfm *tfm)
883 struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(tfm);
885 crypto_free_shash(ctx->fallback);
887 crypto_free_shash(ctx->base_hash);
890 static int mv_cra_hash_sha1_init(struct crypto_tfm *tfm)
892 return mv_cra_hash_init(tfm, NULL, COP_SHA1, 0);
895 static int mv_cra_hash_hmac_sha1_init(struct crypto_tfm *tfm)
897 return mv_cra_hash_init(tfm, "sha1", COP_HMAC_SHA1, SHA1_BLOCK_SIZE);
900 irqreturn_t crypto_int(int irq, void *priv)
904 val = readl(cpg->reg + SEC_ACCEL_INT_STATUS);
905 if (!(val & SEC_INT_ACCEL0_DONE))
908 if (!del_timer(&cpg->completion_timer)) {
909 printk(KERN_WARNING MV_CESA
910 "got an interrupt but no pending timer?\n");
912 val &= ~SEC_INT_ACCEL0_DONE;
913 writel(val, cpg->reg + FPGA_INT_STATUS);
914 writel(val, cpg->reg + SEC_ACCEL_INT_STATUS);
915 BUG_ON(cpg->eng_st != ENGINE_BUSY);
916 cpg->eng_st = ENGINE_W_DEQUEUE;
917 wake_up_process(cpg->queue_th);
921 struct crypto_alg mv_aes_alg_ecb = {
922 .cra_name = "ecb(aes)",
923 .cra_driver_name = "mv-ecb-aes",
925 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
926 CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC,
928 .cra_ctxsize = sizeof(struct mv_ctx),
930 .cra_type = &crypto_ablkcipher_type,
931 .cra_module = THIS_MODULE,
932 .cra_init = mv_cra_init,
935 .min_keysize = AES_MIN_KEY_SIZE,
936 .max_keysize = AES_MAX_KEY_SIZE,
937 .setkey = mv_setkey_aes,
938 .encrypt = mv_enc_aes_ecb,
939 .decrypt = mv_dec_aes_ecb,
944 struct crypto_alg mv_aes_alg_cbc = {
945 .cra_name = "cbc(aes)",
946 .cra_driver_name = "mv-cbc-aes",
948 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
949 CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC,
950 .cra_blocksize = AES_BLOCK_SIZE,
951 .cra_ctxsize = sizeof(struct mv_ctx),
953 .cra_type = &crypto_ablkcipher_type,
954 .cra_module = THIS_MODULE,
955 .cra_init = mv_cra_init,
958 .ivsize = AES_BLOCK_SIZE,
959 .min_keysize = AES_MIN_KEY_SIZE,
960 .max_keysize = AES_MAX_KEY_SIZE,
961 .setkey = mv_setkey_aes,
962 .encrypt = mv_enc_aes_cbc,
963 .decrypt = mv_dec_aes_cbc,
968 struct ahash_alg mv_sha1_alg = {
969 .init = mv_hash_init,
970 .update = mv_hash_update,
971 .final = mv_hash_final,
972 .finup = mv_hash_finup,
973 .digest = mv_hash_digest,
975 .digestsize = SHA1_DIGEST_SIZE,
978 .cra_driver_name = "mv-sha1",
981 CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY |
982 CRYPTO_ALG_NEED_FALLBACK,
983 .cra_blocksize = SHA1_BLOCK_SIZE,
984 .cra_ctxsize = sizeof(struct mv_tfm_hash_ctx),
985 .cra_init = mv_cra_hash_sha1_init,
986 .cra_exit = mv_cra_hash_exit,
987 .cra_module = THIS_MODULE,
992 struct ahash_alg mv_hmac_sha1_alg = {
993 .init = mv_hash_init,
994 .update = mv_hash_update,
995 .final = mv_hash_final,
996 .finup = mv_hash_finup,
997 .digest = mv_hash_digest,
998 .setkey = mv_hash_setkey,
1000 .digestsize = SHA1_DIGEST_SIZE,
1002 .cra_name = "hmac(sha1)",
1003 .cra_driver_name = "mv-hmac-sha1",
1004 .cra_priority = 300,
1006 CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY |
1007 CRYPTO_ALG_NEED_FALLBACK,
1008 .cra_blocksize = SHA1_BLOCK_SIZE,
1009 .cra_ctxsize = sizeof(struct mv_tfm_hash_ctx),
1010 .cra_init = mv_cra_hash_hmac_sha1_init,
1011 .cra_exit = mv_cra_hash_exit,
1012 .cra_module = THIS_MODULE,
1017 static int mv_probe(struct platform_device *pdev)
1019 struct crypto_priv *cp;
1020 struct resource *res;
1025 printk(KERN_ERR MV_CESA "Second crypto dev?\n");
1029 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1033 cp = kzalloc(sizeof(*cp), GFP_KERNEL);
1037 spin_lock_init(&cp->lock);
1038 crypto_init_queue(&cp->queue, 50);
1039 cp->reg = ioremap(res->start, resource_size(res));
1045 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
1050 cp->sram_size = resource_size(res);
1051 cp->max_req_size = cp->sram_size - SRAM_CFG_SPACE;
1052 cp->sram = ioremap(res->start, cp->sram_size);
1058 irq = platform_get_irq(pdev, 0);
1059 if (irq < 0 || irq == NO_IRQ) {
1061 goto err_unmap_sram;
1065 platform_set_drvdata(pdev, cp);
1068 cp->queue_th = kthread_run(queue_manag, cp, "mv_crypto");
1069 if (IS_ERR(cp->queue_th)) {
1070 ret = PTR_ERR(cp->queue_th);
1071 goto err_unmap_sram;
1074 ret = request_irq(irq, crypto_int, IRQF_DISABLED, dev_name(&pdev->dev),
1079 /* Not all platforms can gate the clock, so it is not
1080 an error if the clock does not exists. */
1081 cp->clk = clk_get(&pdev->dev, NULL);
1082 if (!IS_ERR(cp->clk))
1083 clk_prepare_enable(cp->clk);
1085 writel(SEC_INT_ACCEL0_DONE, cpg->reg + SEC_ACCEL_INT_MASK);
1086 writel(SEC_CFG_STOP_DIG_ERR, cpg->reg + SEC_ACCEL_CFG);
1087 writel(SRAM_CONFIG, cpg->reg + SEC_ACCEL_DESC_P0);
1089 ret = crypto_register_alg(&mv_aes_alg_ecb);
1091 printk(KERN_WARNING MV_CESA
1092 "Could not register aes-ecb driver\n");
1096 ret = crypto_register_alg(&mv_aes_alg_cbc);
1098 printk(KERN_WARNING MV_CESA
1099 "Could not register aes-cbc driver\n");
1103 ret = crypto_register_ahash(&mv_sha1_alg);
1107 printk(KERN_WARNING MV_CESA "Could not register sha1 driver\n");
1109 ret = crypto_register_ahash(&mv_hmac_sha1_alg);
1111 cpg->has_hmac_sha1 = 1;
1113 printk(KERN_WARNING MV_CESA
1114 "Could not register hmac-sha1 driver\n");
1119 crypto_unregister_alg(&mv_aes_alg_ecb);
1123 kthread_stop(cp->queue_th);
1131 platform_set_drvdata(pdev, NULL);
1135 static int mv_remove(struct platform_device *pdev)
1137 struct crypto_priv *cp = platform_get_drvdata(pdev);
1139 crypto_unregister_alg(&mv_aes_alg_ecb);
1140 crypto_unregister_alg(&mv_aes_alg_cbc);
1142 crypto_unregister_ahash(&mv_sha1_alg);
1143 if (cp->has_hmac_sha1)
1144 crypto_unregister_ahash(&mv_hmac_sha1_alg);
1145 kthread_stop(cp->queue_th);
1146 free_irq(cp->irq, cp);
1147 memset(cp->sram, 0, cp->sram_size);
1151 if (!IS_ERR(cp->clk)) {
1152 clk_disable_unprepare(cp->clk);
1161 static struct platform_driver marvell_crypto = {
1163 .remove = mv_remove,
1165 .owner = THIS_MODULE,
1166 .name = "mv_crypto",
1169 MODULE_ALIAS("platform:mv_crypto");
1171 module_platform_driver(marvell_crypto);
1173 MODULE_AUTHOR("Sebastian Andrzej Siewior <sebastian@breakpoint.cc>");
1174 MODULE_DESCRIPTION("Support for Marvell's cryptographic engine");
1175 MODULE_LICENSE("GPL");