4 * Support for OMAP SHA1/MD5 HW acceleration.
6 * Copyright (c) 2010 Nokia Corporation
7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
8 * Copyright (c) 2011 Texas Instruments Incorporated
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
14 * Some ideas are from old omap-sha1-md5.c driver.
17 #define pr_fmt(fmt) "%s: " fmt, __func__
19 #include <linux/err.h>
20 #include <linux/device.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/irq.h>
28 #include <linux/platform_device.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
32 #include <linux/omap-dma.h>
33 #include <linux/pm_runtime.h>
35 #include <linux/of_device.h>
36 #include <linux/of_address.h>
37 #include <linux/of_irq.h>
38 #include <linux/delay.h>
39 #include <linux/crypto.h>
40 #include <linux/cryptohash.h>
41 #include <crypto/scatterwalk.h>
42 #include <crypto/algapi.h>
43 #include <crypto/sha.h>
44 #include <crypto/hash.h>
45 #include <crypto/internal/hash.h>
47 #define MD5_DIGEST_SIZE 16
49 #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04))
50 #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04))
51 #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs)
53 #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04))
55 #define SHA_REG_CTRL 0x18
56 #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5)
57 #define SHA_REG_CTRL_CLOSE_HASH (1 << 4)
58 #define SHA_REG_CTRL_ALGO_CONST (1 << 3)
59 #define SHA_REG_CTRL_ALGO (1 << 2)
60 #define SHA_REG_CTRL_INPUT_READY (1 << 1)
61 #define SHA_REG_CTRL_OUTPUT_READY (1 << 0)
63 #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs)
65 #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs)
66 #define SHA_REG_MASK_DMA_EN (1 << 3)
67 #define SHA_REG_MASK_IT_EN (1 << 2)
68 #define SHA_REG_MASK_SOFTRESET (1 << 1)
69 #define SHA_REG_AUTOIDLE (1 << 0)
71 #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs)
72 #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0)
74 #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs)
75 #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7)
76 #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5)
77 #define SHA_REG_MODE_CLOSE_HASH (1 << 4)
78 #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3)
80 #define SHA_REG_MODE_ALGO_MASK (7 << 0)
81 #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1)
82 #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1)
83 #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1)
84 #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1)
85 #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0)
86 #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0)
88 #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs)
90 #define SHA_REG_IRQSTATUS 0x118
91 #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3)
92 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
93 #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1)
94 #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0)
96 #define SHA_REG_IRQENA 0x11C
97 #define SHA_REG_IRQENA_CTX_RDY (1 << 3)
98 #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2)
99 #define SHA_REG_IRQENA_INPUT_RDY (1 << 1)
100 #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0)
102 #define DEFAULT_TIMEOUT_INTERVAL HZ
104 /* mostly device flags */
106 #define FLAGS_FINAL 1
107 #define FLAGS_DMA_ACTIVE 2
108 #define FLAGS_OUTPUT_READY 3
111 #define FLAGS_DMA_READY 6
112 #define FLAGS_AUTO_XOR 7
113 #define FLAGS_BE32_SHA1 8
115 #define FLAGS_FINUP 16
118 #define FLAGS_MODE_SHIFT 18
119 #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
120 #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
121 #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
122 #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
123 #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
124 #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
125 #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
127 #define FLAGS_HMAC 21
128 #define FLAGS_ERROR 22
133 #define OMAP_ALIGN_MASK (sizeof(u32)-1)
134 #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32))))
136 #define BUFLEN PAGE_SIZE
138 struct omap_sham_dev;
140 struct omap_sham_reqctx {
141 struct omap_sham_dev *dd;
145 u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
152 struct scatterlist *sg;
153 struct scatterlist sgl;
154 unsigned int offset; /* offset in current sg */
155 unsigned int total; /* total request */
157 u8 buffer[0] OMAP_ALIGNED;
160 struct omap_sham_hmac_ctx {
161 struct crypto_shash *shash;
162 u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
163 u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
166 struct omap_sham_ctx {
167 struct omap_sham_dev *dd;
172 struct crypto_shash *fallback;
174 struct omap_sham_hmac_ctx base[0];
177 #define OMAP_SHAM_QUEUE_LENGTH 1
179 struct omap_sham_algs_info {
180 struct ahash_alg *algs_list;
182 unsigned int registered;
185 struct omap_sham_pdata {
186 struct omap_sham_algs_info *algs_info;
187 unsigned int algs_info_size;
191 void (*copy_hash)(struct ahash_request *req, int out);
192 void (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
194 void (*trigger)(struct omap_sham_dev *dd, size_t length);
195 int (*poll_irq)(struct omap_sham_dev *dd);
196 irqreturn_t (*intr_hdlr)(int irq, void *dev_id);
214 struct omap_sham_dev {
215 struct list_head list;
216 unsigned long phys_base;
218 void __iomem *io_base;
223 struct dma_chan *dma_lch;
224 struct tasklet_struct done_task;
228 struct crypto_queue queue;
229 struct ahash_request *req;
231 const struct omap_sham_pdata *pdata;
234 struct omap_sham_drv {
235 struct list_head dev_list;
240 static struct omap_sham_drv sham = {
241 .dev_list = LIST_HEAD_INIT(sham.dev_list),
242 .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
245 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
247 return __raw_readl(dd->io_base + offset);
250 static inline void omap_sham_write(struct omap_sham_dev *dd,
251 u32 offset, u32 value)
253 __raw_writel(value, dd->io_base + offset);
256 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
261 val = omap_sham_read(dd, address);
264 omap_sham_write(dd, address, val);
267 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
269 unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
271 while (!(omap_sham_read(dd, offset) & bit)) {
272 if (time_is_before_jiffies(timeout))
279 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
281 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
282 struct omap_sham_dev *dd = ctx->dd;
283 u32 *hash = (u32 *)ctx->digest;
286 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
288 hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
290 omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
294 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
296 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
297 struct omap_sham_dev *dd = ctx->dd;
300 if (ctx->flags & BIT(FLAGS_HMAC)) {
301 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
302 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
303 struct omap_sham_hmac_ctx *bctx = tctx->base;
304 u32 *opad = (u32 *)bctx->opad;
306 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
308 opad[i] = omap_sham_read(dd,
309 SHA_REG_ODIGEST(dd, i));
311 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
316 omap_sham_copy_hash_omap2(req, out);
319 static void omap_sham_copy_ready_hash(struct ahash_request *req)
321 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
322 u32 *in = (u32 *)ctx->digest;
323 u32 *hash = (u32 *)req->result;
324 int i, d, big_endian = 0;
329 switch (ctx->flags & FLAGS_MODE_MASK) {
331 d = MD5_DIGEST_SIZE / sizeof(u32);
333 case FLAGS_MODE_SHA1:
334 /* OMAP2 SHA1 is big endian */
335 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
337 d = SHA1_DIGEST_SIZE / sizeof(u32);
339 case FLAGS_MODE_SHA224:
340 d = SHA224_DIGEST_SIZE / sizeof(u32);
342 case FLAGS_MODE_SHA256:
343 d = SHA256_DIGEST_SIZE / sizeof(u32);
345 case FLAGS_MODE_SHA384:
346 d = SHA384_DIGEST_SIZE / sizeof(u32);
348 case FLAGS_MODE_SHA512:
349 d = SHA512_DIGEST_SIZE / sizeof(u32);
356 for (i = 0; i < d; i++)
357 hash[i] = be32_to_cpu(in[i]);
359 for (i = 0; i < d; i++)
360 hash[i] = le32_to_cpu(in[i]);
363 static int omap_sham_hw_init(struct omap_sham_dev *dd)
365 pm_runtime_get_sync(dd->dev);
367 if (!test_bit(FLAGS_INIT, &dd->flags)) {
368 set_bit(FLAGS_INIT, &dd->flags);
375 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
378 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
379 u32 val = length << 5, mask;
381 if (likely(ctx->digcnt))
382 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
384 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
385 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
386 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
388 * Setting ALGO_CONST only for the first iteration
389 * and CLOSE_HASH only for the last one.
391 if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
392 val |= SHA_REG_CTRL_ALGO;
394 val |= SHA_REG_CTRL_ALGO_CONST;
396 val |= SHA_REG_CTRL_CLOSE_HASH;
398 mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
399 SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
401 omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
404 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
408 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
410 return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
413 static int get_block_size(struct omap_sham_reqctx *ctx)
417 switch (ctx->flags & FLAGS_MODE_MASK) {
419 case FLAGS_MODE_SHA1:
422 case FLAGS_MODE_SHA224:
423 case FLAGS_MODE_SHA256:
424 d = SHA256_BLOCK_SIZE;
426 case FLAGS_MODE_SHA384:
427 case FLAGS_MODE_SHA512:
428 d = SHA512_BLOCK_SIZE;
437 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
438 u32 *value, int count)
440 for (; count--; value++, offset += 4)
441 omap_sham_write(dd, offset, *value);
444 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
447 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
451 * Setting ALGO_CONST only for the first iteration and
452 * CLOSE_HASH only for the last one. Note that flags mode bits
453 * correspond to algorithm encoding in mode register.
455 val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
457 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
458 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
459 struct omap_sham_hmac_ctx *bctx = tctx->base;
462 val |= SHA_REG_MODE_ALGO_CONSTANT;
464 if (ctx->flags & BIT(FLAGS_HMAC)) {
465 bs = get_block_size(ctx);
466 nr_dr = bs / (2 * sizeof(u32));
467 val |= SHA_REG_MODE_HMAC_KEY_PROC;
468 omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
469 (u32 *)bctx->ipad, nr_dr);
470 omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
471 (u32 *)bctx->ipad + nr_dr, nr_dr);
477 val |= SHA_REG_MODE_CLOSE_HASH;
479 if (ctx->flags & BIT(FLAGS_HMAC))
480 val |= SHA_REG_MODE_HMAC_OUTER_HASH;
483 mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
484 SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
485 SHA_REG_MODE_HMAC_KEY_PROC;
487 dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
488 omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
489 omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
490 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
492 (dma ? SHA_REG_MASK_DMA_EN : 0),
493 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
496 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
498 omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
501 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
503 return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
504 SHA_REG_IRQSTATUS_INPUT_RDY);
507 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
508 size_t length, int final)
510 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
511 int count, len32, bs32, offset = 0;
512 const u32 *buffer = (const u32 *)buf;
514 dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
515 ctx->digcnt, length, final);
517 dd->pdata->write_ctrl(dd, length, final, 0);
518 dd->pdata->trigger(dd, length);
520 /* should be non-zero before next lines to disable clocks later */
521 ctx->digcnt += length;
524 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
526 set_bit(FLAGS_CPU, &dd->flags);
528 len32 = DIV_ROUND_UP(length, sizeof(u32));
529 bs32 = get_block_size(ctx) / sizeof(u32);
532 if (dd->pdata->poll_irq(dd))
535 for (count = 0; count < min(len32, bs32); count++, offset++)
536 omap_sham_write(dd, SHA_REG_DIN(dd, count),
538 len32 -= min(len32, bs32);
544 static void omap_sham_dma_callback(void *param)
546 struct omap_sham_dev *dd = param;
548 set_bit(FLAGS_DMA_READY, &dd->flags);
549 tasklet_schedule(&dd->done_task);
552 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
553 size_t length, int final, int is_sg)
555 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
556 struct dma_async_tx_descriptor *tx;
557 struct dma_slave_config cfg;
558 int len32, ret, dma_min = get_block_size(ctx);
560 dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
561 ctx->digcnt, length, final);
563 memset(&cfg, 0, sizeof(cfg));
565 cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
566 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
567 cfg.dst_maxburst = dma_min / DMA_SLAVE_BUSWIDTH_4_BYTES;
569 ret = dmaengine_slave_config(dd->dma_lch, &cfg);
571 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
575 len32 = DIV_ROUND_UP(length, dma_min) * dma_min;
579 * The SG entry passed in may not have the 'length' member
580 * set correctly so use a local SG entry (sgl) with the
581 * proper value for 'length' instead. If this is not done,
582 * the dmaengine may try to DMA the incorrect amount of data.
584 sg_init_table(&ctx->sgl, 1);
585 ctx->sgl.page_link = ctx->sg->page_link;
586 ctx->sgl.offset = ctx->sg->offset;
587 sg_dma_len(&ctx->sgl) = len32;
588 sg_dma_address(&ctx->sgl) = sg_dma_address(ctx->sg);
590 tx = dmaengine_prep_slave_sg(dd->dma_lch, &ctx->sgl, 1,
591 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
593 tx = dmaengine_prep_slave_single(dd->dma_lch, dma_addr, len32,
594 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
598 dev_err(dd->dev, "prep_slave_sg/single() failed\n");
602 tx->callback = omap_sham_dma_callback;
603 tx->callback_param = dd;
605 dd->pdata->write_ctrl(dd, length, final, 1);
607 ctx->digcnt += length;
610 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
612 set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
614 dmaengine_submit(tx);
615 dma_async_issue_pending(dd->dma_lch);
617 dd->pdata->trigger(dd, length);
622 static size_t omap_sham_append_buffer(struct omap_sham_reqctx *ctx,
623 const u8 *data, size_t length)
625 size_t count = min(length, ctx->buflen - ctx->bufcnt);
627 count = min(count, ctx->total);
630 memcpy(ctx->buffer + ctx->bufcnt, data, count);
631 ctx->bufcnt += count;
636 static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx)
642 vaddr = kmap_atomic(sg_page(ctx->sg));
644 count = omap_sham_append_buffer(ctx,
646 ctx->sg->length - ctx->offset);
648 kunmap_atomic((void *)vaddr);
652 ctx->offset += count;
654 if (ctx->offset == ctx->sg->length) {
655 ctx->sg = sg_next(ctx->sg);
666 static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd,
667 struct omap_sham_reqctx *ctx,
668 size_t length, int final)
672 ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen,
674 if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
675 dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen);
679 ctx->flags &= ~BIT(FLAGS_SG);
681 ret = omap_sham_xmit_dma(dd, ctx->dma_addr, length, final, 0);
682 if (ret != -EINPROGRESS)
683 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
689 static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
691 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
695 omap_sham_append_sg(ctx);
697 final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
699 dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n",
700 ctx->bufcnt, ctx->digcnt, final);
702 if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
705 return omap_sham_xmit_dma_map(dd, ctx, count, final);
711 /* Start address alignment */
712 #define SG_AA(sg) (IS_ALIGNED(sg->offset, sizeof(u32)))
713 /* SHA1 block size alignment */
714 #define SG_SA(sg, bs) (IS_ALIGNED(sg->length, bs))
716 static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
718 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
719 unsigned int length, final, tail;
720 struct scatterlist *sg;
726 if (ctx->bufcnt || ctx->offset)
727 return omap_sham_update_dma_slow(dd);
730 * Don't use the sg interface when the transfer size is less
731 * than the number of elements in a DMA frame. Otherwise,
732 * the dmaengine infrastructure will calculate that it needs
733 * to transfer 0 frames which ultimately fails.
735 if (ctx->total < get_block_size(ctx))
736 return omap_sham_update_dma_slow(dd);
738 dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n",
739 ctx->digcnt, ctx->bufcnt, ctx->total);
742 bs = get_block_size(ctx);
745 return omap_sham_update_dma_slow(dd);
747 if (!sg_is_last(sg) && !SG_SA(sg, bs))
748 /* size is not BLOCK_SIZE aligned */
749 return omap_sham_update_dma_slow(dd);
751 length = min(ctx->total, sg->length);
753 if (sg_is_last(sg)) {
754 if (!(ctx->flags & BIT(FLAGS_FINUP))) {
755 /* not last sg must be BLOCK_SIZE aligned */
756 tail = length & (bs - 1);
757 /* without finup() we need one block to close hash */
764 if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
765 dev_err(dd->dev, "dma_map_sg error\n");
769 ctx->flags |= BIT(FLAGS_SG);
771 ctx->total -= length;
772 ctx->offset = length; /* offset where to start slow */
774 final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
776 ret = omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final, 1);
777 if (ret != -EINPROGRESS)
778 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
783 static int omap_sham_update_cpu(struct omap_sham_dev *dd)
785 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
791 omap_sham_append_sg(ctx);
793 final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
795 dev_dbg(dd->dev, "cpu: bufcnt: %u, digcnt: %d, final: %d\n",
796 ctx->bufcnt, ctx->digcnt, final);
798 if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
799 bufcnt = ctx->bufcnt;
801 return omap_sham_xmit_cpu(dd, ctx->buffer, bufcnt, final);
807 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
809 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
811 dmaengine_terminate_all(dd->dma_lch);
813 if (ctx->flags & BIT(FLAGS_SG)) {
814 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
815 if (ctx->sg->length == ctx->offset) {
816 ctx->sg = sg_next(ctx->sg);
821 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
828 static int omap_sham_init(struct ahash_request *req)
830 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
831 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
832 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
833 struct omap_sham_dev *dd = NULL, *tmp;
836 spin_lock_bh(&sham.lock);
838 list_for_each_entry(tmp, &sham.dev_list, list) {
846 spin_unlock_bh(&sham.lock);
852 dev_dbg(dd->dev, "init: digest size: %d\n",
853 crypto_ahash_digestsize(tfm));
855 switch (crypto_ahash_digestsize(tfm)) {
856 case MD5_DIGEST_SIZE:
857 ctx->flags |= FLAGS_MODE_MD5;
858 bs = SHA1_BLOCK_SIZE;
860 case SHA1_DIGEST_SIZE:
861 ctx->flags |= FLAGS_MODE_SHA1;
862 bs = SHA1_BLOCK_SIZE;
864 case SHA224_DIGEST_SIZE:
865 ctx->flags |= FLAGS_MODE_SHA224;
866 bs = SHA224_BLOCK_SIZE;
868 case SHA256_DIGEST_SIZE:
869 ctx->flags |= FLAGS_MODE_SHA256;
870 bs = SHA256_BLOCK_SIZE;
872 case SHA384_DIGEST_SIZE:
873 ctx->flags |= FLAGS_MODE_SHA384;
874 bs = SHA384_BLOCK_SIZE;
876 case SHA512_DIGEST_SIZE:
877 ctx->flags |= FLAGS_MODE_SHA512;
878 bs = SHA512_BLOCK_SIZE;
884 ctx->buflen = BUFLEN;
886 if (tctx->flags & BIT(FLAGS_HMAC)) {
887 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
888 struct omap_sham_hmac_ctx *bctx = tctx->base;
890 memcpy(ctx->buffer, bctx->ipad, bs);
894 ctx->flags |= BIT(FLAGS_HMAC);
901 static int omap_sham_update_req(struct omap_sham_dev *dd)
903 struct ahash_request *req = dd->req;
904 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
907 dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
908 ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
910 if (ctx->flags & BIT(FLAGS_CPU))
911 err = omap_sham_update_cpu(dd);
913 err = omap_sham_update_dma_start(dd);
915 /* wait for dma completion before can take more data */
916 dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
921 static int omap_sham_final_req(struct omap_sham_dev *dd)
923 struct ahash_request *req = dd->req;
924 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
925 int err = 0, use_dma = 1;
927 if ((ctx->bufcnt <= get_block_size(ctx)) || dd->polling_mode)
929 * faster to handle last block with cpu or
930 * use cpu when dma is not present.
935 err = omap_sham_xmit_dma_map(dd, ctx, ctx->bufcnt, 1);
937 err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1);
941 dev_dbg(dd->dev, "final_req: err: %d\n", err);
946 static int omap_sham_finish_hmac(struct ahash_request *req)
948 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
949 struct omap_sham_hmac_ctx *bctx = tctx->base;
950 int bs = crypto_shash_blocksize(bctx->shash);
951 int ds = crypto_shash_digestsize(bctx->shash);
952 SHASH_DESC_ON_STACK(shash, bctx->shash);
954 shash->tfm = bctx->shash;
955 shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
957 return crypto_shash_init(shash) ?:
958 crypto_shash_update(shash, bctx->opad, bs) ?:
959 crypto_shash_finup(shash, req->result, ds, req->result);
962 static int omap_sham_finish(struct ahash_request *req)
964 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
965 struct omap_sham_dev *dd = ctx->dd;
969 omap_sham_copy_ready_hash(req);
970 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
971 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
972 err = omap_sham_finish_hmac(req);
975 dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
980 static void omap_sham_finish_req(struct ahash_request *req, int err)
982 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
983 struct omap_sham_dev *dd = ctx->dd;
986 dd->pdata->copy_hash(req, 1);
987 if (test_bit(FLAGS_FINAL, &dd->flags))
988 err = omap_sham_finish(req);
990 ctx->flags |= BIT(FLAGS_ERROR);
993 /* atomic operation is not needed here */
994 dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
995 BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
997 pm_runtime_put(dd->dev);
999 if (req->base.complete)
1000 req->base.complete(&req->base, err);
1002 /* handle new request */
1003 tasklet_schedule(&dd->done_task);
1006 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1007 struct ahash_request *req)
1009 struct crypto_async_request *async_req, *backlog;
1010 struct omap_sham_reqctx *ctx;
1011 unsigned long flags;
1012 int err = 0, ret = 0;
1014 spin_lock_irqsave(&dd->lock, flags);
1016 ret = ahash_enqueue_request(&dd->queue, req);
1017 if (test_bit(FLAGS_BUSY, &dd->flags)) {
1018 spin_unlock_irqrestore(&dd->lock, flags);
1021 backlog = crypto_get_backlog(&dd->queue);
1022 async_req = crypto_dequeue_request(&dd->queue);
1024 set_bit(FLAGS_BUSY, &dd->flags);
1025 spin_unlock_irqrestore(&dd->lock, flags);
1031 backlog->complete(backlog, -EINPROGRESS);
1033 req = ahash_request_cast(async_req);
1035 ctx = ahash_request_ctx(req);
1037 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1038 ctx->op, req->nbytes);
1040 err = omap_sham_hw_init(dd);
1045 /* request has changed - restore hash */
1046 dd->pdata->copy_hash(req, 0);
1048 if (ctx->op == OP_UPDATE) {
1049 err = omap_sham_update_req(dd);
1050 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1051 /* no final() after finup() */
1052 err = omap_sham_final_req(dd);
1053 } else if (ctx->op == OP_FINAL) {
1054 err = omap_sham_final_req(dd);
1057 if (err != -EINPROGRESS)
1058 /* done_task will not finish it, so do it here */
1059 omap_sham_finish_req(req, err);
1061 dev_dbg(dd->dev, "exit, err: %d\n", err);
1066 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1068 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1069 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1070 struct omap_sham_dev *dd = tctx->dd;
1074 return omap_sham_handle_queue(dd, req);
1077 static int omap_sham_update(struct ahash_request *req)
1079 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1080 struct omap_sham_dev *dd = ctx->dd;
1081 int bs = get_block_size(ctx);
1086 ctx->total = req->nbytes;
1090 if (ctx->flags & BIT(FLAGS_FINUP)) {
1091 if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 9) {
1093 * OMAP HW accel works only with buffers >= 9
1094 * will switch to bypass in final()
1095 * final has the same request and data
1097 omap_sham_append_sg(ctx);
1099 } else if ((ctx->bufcnt + ctx->total <= bs) ||
1102 * faster to use CPU for short transfers or
1103 * use cpu when dma is not present.
1105 ctx->flags |= BIT(FLAGS_CPU);
1107 } else if (ctx->bufcnt + ctx->total < ctx->buflen) {
1108 omap_sham_append_sg(ctx);
1112 if (dd->polling_mode)
1113 ctx->flags |= BIT(FLAGS_CPU);
1115 return omap_sham_enqueue(req, OP_UPDATE);
1118 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1119 const u8 *data, unsigned int len, u8 *out)
1121 SHASH_DESC_ON_STACK(shash, tfm);
1124 shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
1126 return crypto_shash_digest(shash, data, len, out);
1129 static int omap_sham_final_shash(struct ahash_request *req)
1131 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1132 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1134 return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1135 ctx->buffer, ctx->bufcnt, req->result);
1138 static int omap_sham_final(struct ahash_request *req)
1140 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1142 ctx->flags |= BIT(FLAGS_FINUP);
1144 if (ctx->flags & BIT(FLAGS_ERROR))
1145 return 0; /* uncompleted hash is not needed */
1147 /* OMAP HW accel works only with buffers >= 9 */
1148 /* HMAC is always >= 9 because ipad == block size */
1149 if ((ctx->digcnt + ctx->bufcnt) < 9)
1150 return omap_sham_final_shash(req);
1151 else if (ctx->bufcnt)
1152 return omap_sham_enqueue(req, OP_FINAL);
1154 /* copy ready hash (+ finalize hmac) */
1155 return omap_sham_finish(req);
1158 static int omap_sham_finup(struct ahash_request *req)
1160 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1163 ctx->flags |= BIT(FLAGS_FINUP);
1165 err1 = omap_sham_update(req);
1166 if (err1 == -EINPROGRESS || err1 == -EBUSY)
1169 * final() has to be always called to cleanup resources
1170 * even if udpate() failed, except EINPROGRESS
1172 err2 = omap_sham_final(req);
1174 return err1 ?: err2;
1177 static int omap_sham_digest(struct ahash_request *req)
1179 return omap_sham_init(req) ?: omap_sham_finup(req);
1182 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1183 unsigned int keylen)
1185 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1186 struct omap_sham_hmac_ctx *bctx = tctx->base;
1187 int bs = crypto_shash_blocksize(bctx->shash);
1188 int ds = crypto_shash_digestsize(bctx->shash);
1189 struct omap_sham_dev *dd = NULL, *tmp;
1192 spin_lock_bh(&sham.lock);
1194 list_for_each_entry(tmp, &sham.dev_list, list) {
1202 spin_unlock_bh(&sham.lock);
1204 err = crypto_shash_setkey(tctx->fallback, key, keylen);
1209 err = omap_sham_shash_digest(bctx->shash,
1210 crypto_shash_get_flags(bctx->shash),
1211 key, keylen, bctx->ipad);
1216 memcpy(bctx->ipad, key, keylen);
1219 memset(bctx->ipad + keylen, 0, bs - keylen);
1221 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
1222 memcpy(bctx->opad, bctx->ipad, bs);
1224 for (i = 0; i < bs; i++) {
1225 bctx->ipad[i] ^= 0x36;
1226 bctx->opad[i] ^= 0x5c;
1233 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1235 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1236 const char *alg_name = crypto_tfm_alg_name(tfm);
1238 /* Allocate a fallback and abort if it failed. */
1239 tctx->fallback = crypto_alloc_shash(alg_name, 0,
1240 CRYPTO_ALG_NEED_FALLBACK);
1241 if (IS_ERR(tctx->fallback)) {
1242 pr_err("omap-sham: fallback driver '%s' "
1243 "could not be loaded.\n", alg_name);
1244 return PTR_ERR(tctx->fallback);
1247 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1248 sizeof(struct omap_sham_reqctx) + BUFLEN);
1251 struct omap_sham_hmac_ctx *bctx = tctx->base;
1252 tctx->flags |= BIT(FLAGS_HMAC);
1253 bctx->shash = crypto_alloc_shash(alg_base, 0,
1254 CRYPTO_ALG_NEED_FALLBACK);
1255 if (IS_ERR(bctx->shash)) {
1256 pr_err("omap-sham: base driver '%s' "
1257 "could not be loaded.\n", alg_base);
1258 crypto_free_shash(tctx->fallback);
1259 return PTR_ERR(bctx->shash);
1267 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1269 return omap_sham_cra_init_alg(tfm, NULL);
1272 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1274 return omap_sham_cra_init_alg(tfm, "sha1");
1277 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1279 return omap_sham_cra_init_alg(tfm, "sha224");
1282 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1284 return omap_sham_cra_init_alg(tfm, "sha256");
1287 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1289 return omap_sham_cra_init_alg(tfm, "md5");
1292 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1294 return omap_sham_cra_init_alg(tfm, "sha384");
1297 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1299 return omap_sham_cra_init_alg(tfm, "sha512");
1302 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1304 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1306 crypto_free_shash(tctx->fallback);
1307 tctx->fallback = NULL;
1309 if (tctx->flags & BIT(FLAGS_HMAC)) {
1310 struct omap_sham_hmac_ctx *bctx = tctx->base;
1311 crypto_free_shash(bctx->shash);
1315 static struct ahash_alg algs_sha1_md5[] = {
1317 .init = omap_sham_init,
1318 .update = omap_sham_update,
1319 .final = omap_sham_final,
1320 .finup = omap_sham_finup,
1321 .digest = omap_sham_digest,
1322 .halg.digestsize = SHA1_DIGEST_SIZE,
1325 .cra_driver_name = "omap-sha1",
1326 .cra_priority = 100,
1327 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1328 CRYPTO_ALG_KERN_DRIVER_ONLY |
1330 CRYPTO_ALG_NEED_FALLBACK,
1331 .cra_blocksize = SHA1_BLOCK_SIZE,
1332 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1334 .cra_module = THIS_MODULE,
1335 .cra_init = omap_sham_cra_init,
1336 .cra_exit = omap_sham_cra_exit,
1340 .init = omap_sham_init,
1341 .update = omap_sham_update,
1342 .final = omap_sham_final,
1343 .finup = omap_sham_finup,
1344 .digest = omap_sham_digest,
1345 .halg.digestsize = MD5_DIGEST_SIZE,
1348 .cra_driver_name = "omap-md5",
1349 .cra_priority = 100,
1350 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1351 CRYPTO_ALG_KERN_DRIVER_ONLY |
1353 CRYPTO_ALG_NEED_FALLBACK,
1354 .cra_blocksize = SHA1_BLOCK_SIZE,
1355 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1356 .cra_alignmask = OMAP_ALIGN_MASK,
1357 .cra_module = THIS_MODULE,
1358 .cra_init = omap_sham_cra_init,
1359 .cra_exit = omap_sham_cra_exit,
1363 .init = omap_sham_init,
1364 .update = omap_sham_update,
1365 .final = omap_sham_final,
1366 .finup = omap_sham_finup,
1367 .digest = omap_sham_digest,
1368 .setkey = omap_sham_setkey,
1369 .halg.digestsize = SHA1_DIGEST_SIZE,
1371 .cra_name = "hmac(sha1)",
1372 .cra_driver_name = "omap-hmac-sha1",
1373 .cra_priority = 100,
1374 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1375 CRYPTO_ALG_KERN_DRIVER_ONLY |
1377 CRYPTO_ALG_NEED_FALLBACK,
1378 .cra_blocksize = SHA1_BLOCK_SIZE,
1379 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1380 sizeof(struct omap_sham_hmac_ctx),
1381 .cra_alignmask = OMAP_ALIGN_MASK,
1382 .cra_module = THIS_MODULE,
1383 .cra_init = omap_sham_cra_sha1_init,
1384 .cra_exit = omap_sham_cra_exit,
1388 .init = omap_sham_init,
1389 .update = omap_sham_update,
1390 .final = omap_sham_final,
1391 .finup = omap_sham_finup,
1392 .digest = omap_sham_digest,
1393 .setkey = omap_sham_setkey,
1394 .halg.digestsize = MD5_DIGEST_SIZE,
1396 .cra_name = "hmac(md5)",
1397 .cra_driver_name = "omap-hmac-md5",
1398 .cra_priority = 100,
1399 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1400 CRYPTO_ALG_KERN_DRIVER_ONLY |
1402 CRYPTO_ALG_NEED_FALLBACK,
1403 .cra_blocksize = SHA1_BLOCK_SIZE,
1404 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1405 sizeof(struct omap_sham_hmac_ctx),
1406 .cra_alignmask = OMAP_ALIGN_MASK,
1407 .cra_module = THIS_MODULE,
1408 .cra_init = omap_sham_cra_md5_init,
1409 .cra_exit = omap_sham_cra_exit,
1414 /* OMAP4 has some algs in addition to what OMAP2 has */
1415 static struct ahash_alg algs_sha224_sha256[] = {
1417 .init = omap_sham_init,
1418 .update = omap_sham_update,
1419 .final = omap_sham_final,
1420 .finup = omap_sham_finup,
1421 .digest = omap_sham_digest,
1422 .halg.digestsize = SHA224_DIGEST_SIZE,
1424 .cra_name = "sha224",
1425 .cra_driver_name = "omap-sha224",
1426 .cra_priority = 100,
1427 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1429 CRYPTO_ALG_NEED_FALLBACK,
1430 .cra_blocksize = SHA224_BLOCK_SIZE,
1431 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1433 .cra_module = THIS_MODULE,
1434 .cra_init = omap_sham_cra_init,
1435 .cra_exit = omap_sham_cra_exit,
1439 .init = omap_sham_init,
1440 .update = omap_sham_update,
1441 .final = omap_sham_final,
1442 .finup = omap_sham_finup,
1443 .digest = omap_sham_digest,
1444 .halg.digestsize = SHA256_DIGEST_SIZE,
1446 .cra_name = "sha256",
1447 .cra_driver_name = "omap-sha256",
1448 .cra_priority = 100,
1449 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1451 CRYPTO_ALG_NEED_FALLBACK,
1452 .cra_blocksize = SHA256_BLOCK_SIZE,
1453 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1455 .cra_module = THIS_MODULE,
1456 .cra_init = omap_sham_cra_init,
1457 .cra_exit = omap_sham_cra_exit,
1461 .init = omap_sham_init,
1462 .update = omap_sham_update,
1463 .final = omap_sham_final,
1464 .finup = omap_sham_finup,
1465 .digest = omap_sham_digest,
1466 .setkey = omap_sham_setkey,
1467 .halg.digestsize = SHA224_DIGEST_SIZE,
1469 .cra_name = "hmac(sha224)",
1470 .cra_driver_name = "omap-hmac-sha224",
1471 .cra_priority = 100,
1472 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1474 CRYPTO_ALG_NEED_FALLBACK,
1475 .cra_blocksize = SHA224_BLOCK_SIZE,
1476 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1477 sizeof(struct omap_sham_hmac_ctx),
1478 .cra_alignmask = OMAP_ALIGN_MASK,
1479 .cra_module = THIS_MODULE,
1480 .cra_init = omap_sham_cra_sha224_init,
1481 .cra_exit = omap_sham_cra_exit,
1485 .init = omap_sham_init,
1486 .update = omap_sham_update,
1487 .final = omap_sham_final,
1488 .finup = omap_sham_finup,
1489 .digest = omap_sham_digest,
1490 .setkey = omap_sham_setkey,
1491 .halg.digestsize = SHA256_DIGEST_SIZE,
1493 .cra_name = "hmac(sha256)",
1494 .cra_driver_name = "omap-hmac-sha256",
1495 .cra_priority = 100,
1496 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1498 CRYPTO_ALG_NEED_FALLBACK,
1499 .cra_blocksize = SHA256_BLOCK_SIZE,
1500 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1501 sizeof(struct omap_sham_hmac_ctx),
1502 .cra_alignmask = OMAP_ALIGN_MASK,
1503 .cra_module = THIS_MODULE,
1504 .cra_init = omap_sham_cra_sha256_init,
1505 .cra_exit = omap_sham_cra_exit,
1510 static struct ahash_alg algs_sha384_sha512[] = {
1512 .init = omap_sham_init,
1513 .update = omap_sham_update,
1514 .final = omap_sham_final,
1515 .finup = omap_sham_finup,
1516 .digest = omap_sham_digest,
1517 .halg.digestsize = SHA384_DIGEST_SIZE,
1519 .cra_name = "sha384",
1520 .cra_driver_name = "omap-sha384",
1521 .cra_priority = 100,
1522 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1524 CRYPTO_ALG_NEED_FALLBACK,
1525 .cra_blocksize = SHA384_BLOCK_SIZE,
1526 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1528 .cra_module = THIS_MODULE,
1529 .cra_init = omap_sham_cra_init,
1530 .cra_exit = omap_sham_cra_exit,
1534 .init = omap_sham_init,
1535 .update = omap_sham_update,
1536 .final = omap_sham_final,
1537 .finup = omap_sham_finup,
1538 .digest = omap_sham_digest,
1539 .halg.digestsize = SHA512_DIGEST_SIZE,
1541 .cra_name = "sha512",
1542 .cra_driver_name = "omap-sha512",
1543 .cra_priority = 100,
1544 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1546 CRYPTO_ALG_NEED_FALLBACK,
1547 .cra_blocksize = SHA512_BLOCK_SIZE,
1548 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1550 .cra_module = THIS_MODULE,
1551 .cra_init = omap_sham_cra_init,
1552 .cra_exit = omap_sham_cra_exit,
1556 .init = omap_sham_init,
1557 .update = omap_sham_update,
1558 .final = omap_sham_final,
1559 .finup = omap_sham_finup,
1560 .digest = omap_sham_digest,
1561 .setkey = omap_sham_setkey,
1562 .halg.digestsize = SHA384_DIGEST_SIZE,
1564 .cra_name = "hmac(sha384)",
1565 .cra_driver_name = "omap-hmac-sha384",
1566 .cra_priority = 100,
1567 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1569 CRYPTO_ALG_NEED_FALLBACK,
1570 .cra_blocksize = SHA384_BLOCK_SIZE,
1571 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1572 sizeof(struct omap_sham_hmac_ctx),
1573 .cra_alignmask = OMAP_ALIGN_MASK,
1574 .cra_module = THIS_MODULE,
1575 .cra_init = omap_sham_cra_sha384_init,
1576 .cra_exit = omap_sham_cra_exit,
1580 .init = omap_sham_init,
1581 .update = omap_sham_update,
1582 .final = omap_sham_final,
1583 .finup = omap_sham_finup,
1584 .digest = omap_sham_digest,
1585 .setkey = omap_sham_setkey,
1586 .halg.digestsize = SHA512_DIGEST_SIZE,
1588 .cra_name = "hmac(sha512)",
1589 .cra_driver_name = "omap-hmac-sha512",
1590 .cra_priority = 100,
1591 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1593 CRYPTO_ALG_NEED_FALLBACK,
1594 .cra_blocksize = SHA512_BLOCK_SIZE,
1595 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1596 sizeof(struct omap_sham_hmac_ctx),
1597 .cra_alignmask = OMAP_ALIGN_MASK,
1598 .cra_module = THIS_MODULE,
1599 .cra_init = omap_sham_cra_sha512_init,
1600 .cra_exit = omap_sham_cra_exit,
1605 static void omap_sham_done_task(unsigned long data)
1607 struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1610 if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1611 omap_sham_handle_queue(dd, NULL);
1615 if (test_bit(FLAGS_CPU, &dd->flags)) {
1616 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1617 /* hash or semi-hash ready */
1618 err = omap_sham_update_cpu(dd);
1619 if (err != -EINPROGRESS)
1622 } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1623 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1624 omap_sham_update_dma_stop(dd);
1630 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1631 /* hash or semi-hash ready */
1632 clear_bit(FLAGS_DMA_READY, &dd->flags);
1633 err = omap_sham_update_dma_start(dd);
1634 if (err != -EINPROGRESS)
1642 dev_dbg(dd->dev, "update done: err: %d\n", err);
1643 /* finish curent request */
1644 omap_sham_finish_req(dd->req, err);
1647 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1649 if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1650 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1652 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1653 tasklet_schedule(&dd->done_task);
1659 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1661 struct omap_sham_dev *dd = dev_id;
1663 if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1664 /* final -> allow device to go to power-saving mode */
1665 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1667 omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1668 SHA_REG_CTRL_OUTPUT_READY);
1669 omap_sham_read(dd, SHA_REG_CTRL);
1671 return omap_sham_irq_common(dd);
1674 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1676 struct omap_sham_dev *dd = dev_id;
1678 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1680 return omap_sham_irq_common(dd);
1683 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1685 .algs_list = algs_sha1_md5,
1686 .size = ARRAY_SIZE(algs_sha1_md5),
1690 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1691 .algs_info = omap_sham_algs_info_omap2,
1692 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1693 .flags = BIT(FLAGS_BE32_SHA1),
1694 .digest_size = SHA1_DIGEST_SIZE,
1695 .copy_hash = omap_sham_copy_hash_omap2,
1696 .write_ctrl = omap_sham_write_ctrl_omap2,
1697 .trigger = omap_sham_trigger_omap2,
1698 .poll_irq = omap_sham_poll_irq_omap2,
1699 .intr_hdlr = omap_sham_irq_omap2,
1700 .idigest_ofs = 0x00,
1705 .sysstatus_ofs = 0x64,
1713 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1715 .algs_list = algs_sha1_md5,
1716 .size = ARRAY_SIZE(algs_sha1_md5),
1719 .algs_list = algs_sha224_sha256,
1720 .size = ARRAY_SIZE(algs_sha224_sha256),
1724 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1725 .algs_info = omap_sham_algs_info_omap4,
1726 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1727 .flags = BIT(FLAGS_AUTO_XOR),
1728 .digest_size = SHA256_DIGEST_SIZE,
1729 .copy_hash = omap_sham_copy_hash_omap4,
1730 .write_ctrl = omap_sham_write_ctrl_omap4,
1731 .trigger = omap_sham_trigger_omap4,
1732 .poll_irq = omap_sham_poll_irq_omap4,
1733 .intr_hdlr = omap_sham_irq_omap4,
1734 .idigest_ofs = 0x020,
1737 .digcnt_ofs = 0x040,
1740 .sysstatus_ofs = 0x114,
1743 .major_mask = 0x0700,
1745 .minor_mask = 0x003f,
1749 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1751 .algs_list = algs_sha1_md5,
1752 .size = ARRAY_SIZE(algs_sha1_md5),
1755 .algs_list = algs_sha224_sha256,
1756 .size = ARRAY_SIZE(algs_sha224_sha256),
1759 .algs_list = algs_sha384_sha512,
1760 .size = ARRAY_SIZE(algs_sha384_sha512),
1764 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1765 .algs_info = omap_sham_algs_info_omap5,
1766 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1767 .flags = BIT(FLAGS_AUTO_XOR),
1768 .digest_size = SHA512_DIGEST_SIZE,
1769 .copy_hash = omap_sham_copy_hash_omap4,
1770 .write_ctrl = omap_sham_write_ctrl_omap4,
1771 .trigger = omap_sham_trigger_omap4,
1772 .poll_irq = omap_sham_poll_irq_omap4,
1773 .intr_hdlr = omap_sham_irq_omap4,
1774 .idigest_ofs = 0x240,
1775 .odigest_ofs = 0x200,
1777 .digcnt_ofs = 0x280,
1780 .sysstatus_ofs = 0x114,
1782 .length_ofs = 0x288,
1783 .major_mask = 0x0700,
1785 .minor_mask = 0x003f,
1789 static const struct of_device_id omap_sham_of_match[] = {
1791 .compatible = "ti,omap2-sham",
1792 .data = &omap_sham_pdata_omap2,
1795 .compatible = "ti,omap4-sham",
1796 .data = &omap_sham_pdata_omap4,
1799 .compatible = "ti,omap5-sham",
1800 .data = &omap_sham_pdata_omap5,
1804 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1806 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1807 struct device *dev, struct resource *res)
1809 struct device_node *node = dev->of_node;
1810 const struct of_device_id *match;
1813 match = of_match_device(of_match_ptr(omap_sham_of_match), dev);
1815 dev_err(dev, "no compatible OF match\n");
1820 err = of_address_to_resource(node, 0, res);
1822 dev_err(dev, "can't translate OF node address\n");
1827 dd->irq = irq_of_parse_and_map(node, 0);
1829 dev_err(dev, "can't translate OF irq value\n");
1834 dd->dma = -1; /* Dummy value that's unused */
1835 dd->pdata = match->data;
1841 static const struct of_device_id omap_sham_of_match[] = {
1845 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1846 struct device *dev, struct resource *res)
1852 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1853 struct platform_device *pdev, struct resource *res)
1855 struct device *dev = &pdev->dev;
1859 /* Get the base address */
1860 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1862 dev_err(dev, "no MEM resource info\n");
1866 memcpy(res, r, sizeof(*res));
1869 dd->irq = platform_get_irq(pdev, 0);
1871 dev_err(dev, "no IRQ resource info\n");
1877 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1879 dev_err(dev, "no DMA resource info\n");
1885 /* Only OMAP2/3 can be non-DT */
1886 dd->pdata = &omap_sham_pdata_omap2;
1892 static int omap_sham_probe(struct platform_device *pdev)
1894 struct omap_sham_dev *dd;
1895 struct device *dev = &pdev->dev;
1896 struct resource res;
1897 dma_cap_mask_t mask;
1901 dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
1903 dev_err(dev, "unable to alloc data struct.\n");
1908 platform_set_drvdata(pdev, dd);
1910 INIT_LIST_HEAD(&dd->list);
1911 spin_lock_init(&dd->lock);
1912 tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
1913 crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
1915 err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
1916 omap_sham_get_res_pdev(dd, pdev, &res);
1920 dd->io_base = devm_ioremap_resource(dev, &res);
1921 if (IS_ERR(dd->io_base)) {
1922 err = PTR_ERR(dd->io_base);
1925 dd->phys_base = res.start;
1927 err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
1928 IRQF_TRIGGER_NONE, dev_name(dev), dd);
1930 dev_err(dev, "unable to request irq %d, err = %d\n",
1936 dma_cap_set(DMA_SLAVE, mask);
1938 dd->dma_lch = dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
1939 &dd->dma, dev, "rx");
1941 dd->polling_mode = 1;
1942 dev_dbg(dev, "using polling mode instead of dma\n");
1945 dd->flags |= dd->pdata->flags;
1947 pm_runtime_enable(dev);
1948 pm_runtime_get_sync(dev);
1949 rev = omap_sham_read(dd, SHA_REG_REV(dd));
1950 pm_runtime_put_sync(&pdev->dev);
1952 dev_info(dev, "hw accel on OMAP rev %u.%u\n",
1953 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
1954 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1956 spin_lock(&sham.lock);
1957 list_add_tail(&dd->list, &sham.dev_list);
1958 spin_unlock(&sham.lock);
1960 for (i = 0; i < dd->pdata->algs_info_size; i++) {
1961 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1962 err = crypto_register_ahash(
1963 &dd->pdata->algs_info[i].algs_list[j]);
1967 dd->pdata->algs_info[i].registered++;
1974 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1975 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1976 crypto_unregister_ahash(
1977 &dd->pdata->algs_info[i].algs_list[j]);
1978 pm_runtime_disable(dev);
1980 dma_release_channel(dd->dma_lch);
1982 dev_err(dev, "initialization failed.\n");
1987 static int omap_sham_remove(struct platform_device *pdev)
1989 static struct omap_sham_dev *dd;
1992 dd = platform_get_drvdata(pdev);
1995 spin_lock(&sham.lock);
1996 list_del(&dd->list);
1997 spin_unlock(&sham.lock);
1998 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1999 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2000 crypto_unregister_ahash(
2001 &dd->pdata->algs_info[i].algs_list[j]);
2002 tasklet_kill(&dd->done_task);
2003 pm_runtime_disable(&pdev->dev);
2006 dma_release_channel(dd->dma_lch);
2011 #ifdef CONFIG_PM_SLEEP
2012 static int omap_sham_suspend(struct device *dev)
2014 pm_runtime_put_sync(dev);
2018 static int omap_sham_resume(struct device *dev)
2020 pm_runtime_get_sync(dev);
2025 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2027 static struct platform_driver omap_sham_driver = {
2028 .probe = omap_sham_probe,
2029 .remove = omap_sham_remove,
2031 .name = "omap-sham",
2032 .owner = THIS_MODULE,
2033 .pm = &omap_sham_pm_ops,
2034 .of_match_table = omap_sham_of_match,
2038 module_platform_driver(omap_sham_driver);
2040 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2041 MODULE_LICENSE("GPL v2");
2042 MODULE_AUTHOR("Dmitry Kasatkin");
2043 MODULE_ALIAS("platform:omap-sham");