2 * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/device.h>
15 #include <linux/interrupt.h>
16 #include <crypto/internal/hash.h>
22 /* crypto hw padding constant for first operation */
23 #define SHA_PADDING 64
24 #define SHA_PADDING_MASK (SHA_PADDING - 1)
26 static LIST_HEAD(ahash_algs);
28 static const u32 std_iv_sha1[SHA256_DIGEST_SIZE / sizeof(u32)] = {
29 SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4, 0, 0, 0
32 static const u32 std_iv_sha256[SHA256_DIGEST_SIZE / sizeof(u32)] = {
33 SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3,
34 SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7
37 static void qce_ahash_done(void *data)
39 struct crypto_async_request *async_req = data;
40 struct ahash_request *req = ahash_request_cast(async_req);
41 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
42 struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
43 struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm);
44 struct qce_device *qce = tmpl->qce;
45 struct qce_result_dump *result = qce->dma.result_buf;
46 unsigned int digestsize = crypto_ahash_digestsize(ahash);
50 error = qce_dma_terminate_all(&qce->dma);
52 dev_dbg(qce->dev, "ahash dma termination error (%d)\n", error);
54 dma_unmap_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
55 dma_unmap_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE);
57 memcpy(rctx->digest, result->auth_iv, digestsize);
59 memcpy(req->result, result->auth_iv, digestsize);
61 rctx->byte_count[0] = cpu_to_be32(result->auth_byte_count[0]);
62 rctx->byte_count[1] = cpu_to_be32(result->auth_byte_count[1]);
64 error = qce_check_status(qce, &status);
66 dev_dbg(qce->dev, "ahash operation error (%x)\n", status);
68 req->src = rctx->src_orig;
69 req->nbytes = rctx->nbytes_orig;
70 rctx->last_blk = false;
71 rctx->first_blk = false;
73 qce->async_req_done(tmpl->qce, error);
76 static int qce_ahash_async_req_handle(struct crypto_async_request *async_req)
78 struct ahash_request *req = ahash_request_cast(async_req);
79 struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
80 struct qce_sha_ctx *ctx = crypto_tfm_ctx(async_req->tfm);
81 struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm);
82 struct qce_device *qce = tmpl->qce;
83 unsigned long flags = rctx->flags;
86 if (IS_SHA_HMAC(flags)) {
87 rctx->authkey = ctx->authkey;
88 rctx->authklen = QCE_SHA_HMAC_KEY_SIZE;
89 } else if (IS_CMAC(flags)) {
90 rctx->authkey = ctx->authkey;
91 rctx->authklen = AES_KEYSIZE_128;
94 rctx->src_nents = sg_nents_for_len(req->src, req->nbytes);
95 ret = dma_map_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
99 sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ);
101 ret = dma_map_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE);
103 goto error_unmap_src;
105 ret = qce_dma_prep_sgs(&qce->dma, req->src, rctx->src_nents,
106 &rctx->result_sg, 1, qce_ahash_done, async_req);
108 goto error_unmap_dst;
110 qce_dma_issue_pending(&qce->dma);
112 ret = qce_start(async_req, tmpl->crypto_alg_type, 0, 0);
114 goto error_terminate;
119 qce_dma_terminate_all(&qce->dma);
121 dma_unmap_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE);
123 dma_unmap_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
127 static int qce_ahash_init(struct ahash_request *req)
129 struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
130 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
131 const u32 *std_iv = tmpl->std_iv;
133 memset(rctx, 0, sizeof(*rctx));
134 rctx->first_blk = true;
135 rctx->last_blk = false;
136 rctx->flags = tmpl->alg_flags;
137 memcpy(rctx->digest, std_iv, sizeof(rctx->digest));
142 static int qce_ahash_export(struct ahash_request *req, void *out)
144 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
145 struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
146 unsigned long flags = rctx->flags;
147 unsigned int digestsize = crypto_ahash_digestsize(ahash);
148 unsigned int blocksize =
149 crypto_tfm_alg_blocksize(crypto_ahash_tfm(ahash));
151 if (IS_SHA1(flags) || IS_SHA1_HMAC(flags)) {
152 struct sha1_state *out_state = out;
154 out_state->count = rctx->count;
155 qce_cpu_to_be32p_array((__be32 *)out_state->state,
156 rctx->digest, digestsize);
157 memcpy(out_state->buffer, rctx->buf, blocksize);
158 } else if (IS_SHA256(flags) || IS_SHA256_HMAC(flags)) {
159 struct sha256_state *out_state = out;
161 out_state->count = rctx->count;
162 qce_cpu_to_be32p_array((__be32 *)out_state->state,
163 rctx->digest, digestsize);
164 memcpy(out_state->buf, rctx->buf, blocksize);
172 static int qce_import_common(struct ahash_request *req, u64 in_count,
173 const u32 *state, const u8 *buffer, bool hmac)
175 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
176 struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
177 unsigned int digestsize = crypto_ahash_digestsize(ahash);
178 unsigned int blocksize;
179 u64 count = in_count;
181 blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(ahash));
182 rctx->count = in_count;
183 memcpy(rctx->buf, buffer, blocksize);
185 if (in_count <= blocksize) {
190 * For HMAC, there is a hardware padding done when first block
191 * is set. Therefore the byte_count must be incremened by 64
192 * after the first block operation.
195 count += SHA_PADDING;
198 rctx->byte_count[0] = (__force __be32)(count & ~SHA_PADDING_MASK);
199 rctx->byte_count[1] = (__force __be32)(count >> 32);
200 qce_cpu_to_be32p_array((__be32 *)rctx->digest, (const u8 *)state,
202 rctx->buflen = (unsigned int)(in_count & (blocksize - 1));
207 static int qce_ahash_import(struct ahash_request *req, const void *in)
209 struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
210 unsigned long flags = rctx->flags;
211 bool hmac = IS_SHA_HMAC(flags);
214 if (IS_SHA1(flags) || IS_SHA1_HMAC(flags)) {
215 const struct sha1_state *state = in;
217 ret = qce_import_common(req, state->count, state->state,
218 state->buffer, hmac);
219 } else if (IS_SHA256(flags) || IS_SHA256_HMAC(flags)) {
220 const struct sha256_state *state = in;
222 ret = qce_import_common(req, state->count, state->state,
229 static int qce_ahash_update(struct ahash_request *req)
231 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
232 struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
233 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
234 struct qce_device *qce = tmpl->qce;
235 struct scatterlist *sg_last, *sg;
236 unsigned int total, len;
237 unsigned int hash_later;
239 unsigned int blocksize;
241 blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
242 rctx->count += req->nbytes;
244 /* check for buffer from previous updates and append it */
245 total = req->nbytes + rctx->buflen;
247 if (total <= blocksize) {
248 scatterwalk_map_and_copy(rctx->buf + rctx->buflen, req->src,
250 rctx->buflen += req->nbytes;
254 /* save the original req structure fields */
255 rctx->src_orig = req->src;
256 rctx->nbytes_orig = req->nbytes;
259 * if we have data from previous update copy them on buffer. The old
260 * data will be combined with current request bytes.
263 memcpy(rctx->tmpbuf, rctx->buf, rctx->buflen);
265 /* calculate how many bytes will be hashed later */
266 hash_later = total % blocksize;
268 unsigned int src_offset = req->nbytes - hash_later;
269 scatterwalk_map_and_copy(rctx->buf, req->src, src_offset,
273 /* here nbytes is multiple of blocksize */
274 nbytes = total - hash_later;
277 sg = sg_last = req->src;
279 while (len < nbytes && sg) {
280 if (len + sg_dma_len(sg) > nbytes)
282 len += sg_dma_len(sg);
290 sg_mark_end(sg_last);
293 sg_init_table(rctx->sg, 2);
294 sg_set_buf(rctx->sg, rctx->tmpbuf, rctx->buflen);
295 sg_chain(rctx->sg, 2, req->src);
299 req->nbytes = nbytes;
300 rctx->buflen = hash_later;
302 return qce->async_req_enqueue(tmpl->qce, &req->base);
305 static int qce_ahash_final(struct ahash_request *req)
307 struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
308 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
309 struct qce_device *qce = tmpl->qce;
314 rctx->last_blk = true;
316 rctx->src_orig = req->src;
317 rctx->nbytes_orig = req->nbytes;
319 memcpy(rctx->tmpbuf, rctx->buf, rctx->buflen);
320 sg_init_one(rctx->sg, rctx->tmpbuf, rctx->buflen);
323 req->nbytes = rctx->buflen;
325 return qce->async_req_enqueue(tmpl->qce, &req->base);
328 static int qce_ahash_digest(struct ahash_request *req)
330 struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
331 struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
332 struct qce_device *qce = tmpl->qce;
335 ret = qce_ahash_init(req);
339 rctx->src_orig = req->src;
340 rctx->nbytes_orig = req->nbytes;
341 rctx->first_blk = true;
342 rctx->last_blk = true;
344 return qce->async_req_enqueue(tmpl->qce, &req->base);
347 struct qce_ahash_result {
348 struct completion completion;
352 static void qce_digest_complete(struct crypto_async_request *req, int error)
354 struct qce_ahash_result *result = req->data;
356 if (error == -EINPROGRESS)
359 result->error = error;
360 complete(&result->completion);
363 static int qce_ahash_hmac_setkey(struct crypto_ahash *tfm, const u8 *key,
366 unsigned int digestsize = crypto_ahash_digestsize(tfm);
367 struct qce_sha_ctx *ctx = crypto_tfm_ctx(&tfm->base);
368 struct qce_ahash_result result;
369 struct ahash_request *req;
370 struct scatterlist sg;
371 unsigned int blocksize;
372 struct crypto_ahash *ahash_tfm;
375 const char *alg_name;
377 blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
378 memset(ctx->authkey, 0, sizeof(ctx->authkey));
380 if (keylen <= blocksize) {
381 memcpy(ctx->authkey, key, keylen);
385 if (digestsize == SHA1_DIGEST_SIZE)
386 alg_name = "sha1-qce";
387 else if (digestsize == SHA256_DIGEST_SIZE)
388 alg_name = "sha256-qce";
392 ahash_tfm = crypto_alloc_ahash(alg_name, CRYPTO_ALG_TYPE_AHASH,
393 CRYPTO_ALG_TYPE_AHASH_MASK);
394 if (IS_ERR(ahash_tfm))
395 return PTR_ERR(ahash_tfm);
397 req = ahash_request_alloc(ahash_tfm, GFP_KERNEL);
403 init_completion(&result.completion);
404 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
405 qce_digest_complete, &result);
406 crypto_ahash_clear_flags(ahash_tfm, ~0);
408 buf = kzalloc(keylen + QCE_MAX_ALIGN_SIZE, GFP_KERNEL);
414 memcpy(buf, key, keylen);
415 sg_init_one(&sg, buf, keylen);
416 ahash_request_set_crypt(req, &sg, ctx->authkey, keylen);
418 ret = crypto_ahash_digest(req);
419 if (ret == -EINPROGRESS || ret == -EBUSY) {
420 ret = wait_for_completion_interruptible(&result.completion);
426 crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
430 ahash_request_free(req);
432 crypto_free_ahash(ahash_tfm);
436 static int qce_ahash_cra_init(struct crypto_tfm *tfm)
438 struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
439 struct qce_sha_ctx *ctx = crypto_tfm_ctx(tfm);
441 crypto_ahash_set_reqsize(ahash, sizeof(struct qce_sha_reqctx));
442 memset(ctx, 0, sizeof(*ctx));
446 struct qce_ahash_def {
449 const char *drv_name;
450 unsigned int digestsize;
451 unsigned int blocksize;
452 unsigned int statesize;
456 static const struct qce_ahash_def ahash_def[] = {
458 .flags = QCE_HASH_SHA1,
460 .drv_name = "sha1-qce",
461 .digestsize = SHA1_DIGEST_SIZE,
462 .blocksize = SHA1_BLOCK_SIZE,
463 .statesize = sizeof(struct sha1_state),
464 .std_iv = std_iv_sha1,
467 .flags = QCE_HASH_SHA256,
469 .drv_name = "sha256-qce",
470 .digestsize = SHA256_DIGEST_SIZE,
471 .blocksize = SHA256_BLOCK_SIZE,
472 .statesize = sizeof(struct sha256_state),
473 .std_iv = std_iv_sha256,
476 .flags = QCE_HASH_SHA1_HMAC,
477 .name = "hmac(sha1)",
478 .drv_name = "hmac-sha1-qce",
479 .digestsize = SHA1_DIGEST_SIZE,
480 .blocksize = SHA1_BLOCK_SIZE,
481 .statesize = sizeof(struct sha1_state),
482 .std_iv = std_iv_sha1,
485 .flags = QCE_HASH_SHA256_HMAC,
486 .name = "hmac(sha256)",
487 .drv_name = "hmac-sha256-qce",
488 .digestsize = SHA256_DIGEST_SIZE,
489 .blocksize = SHA256_BLOCK_SIZE,
490 .statesize = sizeof(struct sha256_state),
491 .std_iv = std_iv_sha256,
495 static int qce_ahash_register_one(const struct qce_ahash_def *def,
496 struct qce_device *qce)
498 struct qce_alg_template *tmpl;
499 struct ahash_alg *alg;
500 struct crypto_alg *base;
503 tmpl = kzalloc(sizeof(*tmpl), GFP_KERNEL);
507 tmpl->std_iv = def->std_iv;
509 alg = &tmpl->alg.ahash;
510 alg->init = qce_ahash_init;
511 alg->update = qce_ahash_update;
512 alg->final = qce_ahash_final;
513 alg->digest = qce_ahash_digest;
514 alg->export = qce_ahash_export;
515 alg->import = qce_ahash_import;
516 if (IS_SHA_HMAC(def->flags))
517 alg->setkey = qce_ahash_hmac_setkey;
518 alg->halg.digestsize = def->digestsize;
519 alg->halg.statesize = def->statesize;
521 base = &alg->halg.base;
522 base->cra_blocksize = def->blocksize;
523 base->cra_priority = 300;
524 base->cra_flags = CRYPTO_ALG_ASYNC;
525 base->cra_ctxsize = sizeof(struct qce_sha_ctx);
526 base->cra_alignmask = 0;
527 base->cra_module = THIS_MODULE;
528 base->cra_init = qce_ahash_cra_init;
529 INIT_LIST_HEAD(&base->cra_list);
531 snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "%s", def->name);
532 snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
535 INIT_LIST_HEAD(&tmpl->entry);
536 tmpl->crypto_alg_type = CRYPTO_ALG_TYPE_AHASH;
537 tmpl->alg_flags = def->flags;
540 ret = crypto_register_ahash(alg);
543 dev_err(qce->dev, "%s registration failed\n", base->cra_name);
547 list_add_tail(&tmpl->entry, &ahash_algs);
548 dev_dbg(qce->dev, "%s is registered\n", base->cra_name);
552 static void qce_ahash_unregister(struct qce_device *qce)
554 struct qce_alg_template *tmpl, *n;
556 list_for_each_entry_safe(tmpl, n, &ahash_algs, entry) {
557 crypto_unregister_ahash(&tmpl->alg.ahash);
558 list_del(&tmpl->entry);
563 static int qce_ahash_register(struct qce_device *qce)
567 for (i = 0; i < ARRAY_SIZE(ahash_def); i++) {
568 ret = qce_ahash_register_one(&ahash_def[i], qce);
575 qce_ahash_unregister(qce);
579 const struct qce_algo_ops ahash_ops = {
580 .type = CRYPTO_ALG_TYPE_AHASH,
581 .register_algs = qce_ahash_register,
582 .unregister_algs = qce_ahash_unregister,
583 .async_req_handle = qce_ahash_async_req_handle,