drivers/crypto/talitos.c

   1 /*
   2  * talitos - Freescale Integrated Security Engine (SEC) device driver
   3  *
   4  * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
   5  *
   6  * Scatterlist Crypto API glue code copied from files with the following:
   7  * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
   8  *
   9  * Crypto algorithm registration code copied from hifn driver:
  10  * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
  11  * All rights reserved.
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  26  */
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/device.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/crypto.h>
  34 #include <linux/hw_random.h>
  35 #include <linux/of_address.h>
  36 #include <linux/of_irq.h>
  37 #include <linux/of_platform.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/io.h>
  40 #include <linux/spinlock.h>
  41 #include <linux/rtnetlink.h>
  42 #include <linux/slab.h>
  43
  44 #include <crypto/algapi.h>
  45 #include <crypto/aes.h>
  46 #include <crypto/des.h>
  47 #include <crypto/sha.h>
  48 #include <crypto/md5.h>
  49 #include <crypto/aead.h>
  50 #include <crypto/authenc.h>
  51 #include <crypto/skcipher.h>
  52 #include <crypto/hash.h>
  53 #include <crypto/internal/hash.h>
  54 #include <crypto/scatterwalk.h>
  55
  56 #include "talitos.h"
  57
  58 static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
  59 {
  60         talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
  61         talitos_ptr->eptr = upper_32_bits(dma_addr);
  62 }
  63
  64 /*
  65  * map virtual single (contiguous) pointer to h/w descriptor pointer
  66  */
  67 static void map_single_talitos_ptr(struct device *dev,
  68                                    struct talitos_ptr *talitos_ptr,
  69                                    unsigned short len, void *data,
  70                                    unsigned char extent,
  71                                    enum dma_data_direction dir)
  72 {
  73         dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
  74
  75         talitos_ptr->len = cpu_to_be16(len);
  76         to_talitos_ptr(talitos_ptr, dma_addr);
  77         talitos_ptr->j_extent = extent;
  78 }
  79
  80 /*
  81  * unmap bus single (contiguous) h/w descriptor pointer
  82  */
  83 static void unmap_single_talitos_ptr(struct device *dev,
  84                                      struct talitos_ptr *talitos_ptr,
  85                                      enum dma_data_direction dir)
  86 {
  87         dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
  88                          be16_to_cpu(talitos_ptr->len), dir);
  89 }
  90
  91 static int reset_channel(struct device *dev, int ch)
  92 {
  93         struct talitos_private *priv = dev_get_drvdata(dev);
  94         unsigned int timeout = TALITOS_TIMEOUT;
  95
  96         setbits32(priv->chan[ch].reg + TALITOS_CCCR, TALITOS_CCCR_RESET);
  97
  98         while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) & TALITOS_CCCR_RESET)
  99                && --timeout)
 100                 cpu_relax();
 101
 102         if (timeout == 0) {
 103                 dev_err(dev, "failed to reset channel %d\n", ch);
 104                 return -EIO;
 105         }
 106
 107         /* set 36-bit addressing, done writeback enable and done IRQ enable */
 108         setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
 109                   TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
 110
 111         /* and ICCR writeback, if available */
 112         if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
 113                 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
 114                           TALITOS_CCCR_LO_IWSE);
 115
 116         return 0;
 117 }
 118
 119 static int reset_device(struct device *dev)
 120 {
 121         struct talitos_private *priv = dev_get_drvdata(dev);
 122         unsigned int timeout = TALITOS_TIMEOUT;
 123         u32 mcr = TALITOS_MCR_SWR;
 124
 125         setbits32(priv->reg + TALITOS_MCR, mcr);
 126
 127         while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
 128                && --timeout)
 129                 cpu_relax();
 130
 131         if (priv->irq[1]) {
 132                 mcr = TALITOS_MCR_RCA1 | TALITOS_MCR_RCA3;
 133                 setbits32(priv->reg + TALITOS_MCR, mcr);
 134         }
 135
 136         if (timeout == 0) {
 137                 dev_err(dev, "failed to reset device\n");
 138                 return -EIO;
 139         }
 140
 141         return 0;
 142 }
 143
 144 /*
 145  * Reset and initialize the device
 146  */
 147 static int init_device(struct device *dev)
 148 {
 149         struct talitos_private *priv = dev_get_drvdata(dev);
 150         int ch, err;
 151
 152         /*
 153          * Master reset
 154          * errata documentation: warning: certain SEC interrupts
 155          * are not fully cleared by writing the MCR:SWR bit,
 156          * set bit twice to completely reset
 157          */
 158         err = reset_device(dev);
 159         if (err)
 160                 return err;
 161
 162         err = reset_device(dev);
 163         if (err)
 164                 return err;
 165
 166         /* reset channels */
 167         for (ch = 0; ch < priv->num_channels; ch++) {
 168                 err = reset_channel(dev, ch);
 169                 if (err)
 170                         return err;
 171         }
 172
 173         /* enable channel done and error interrupts */
 174         setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
 175         setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
 176
 177         /* disable integrity check error interrupts (use writeback instead) */
 178         if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
 179                 setbits32(priv->reg + TALITOS_MDEUICR_LO,
 180                           TALITOS_MDEUICR_LO_ICE);
 181
 182         return 0;
 183 }
 184
 185 /**
 186  * talitos_submit - submits a descriptor to the device for processing
 187  * @dev:        the SEC device to be used
 188  * @ch:         the SEC device channel to be used
 189  * @desc:       the descriptor to be processed by the device
 190  * @callback:   whom to call when processing is complete
 191  * @context:    a handle for use by caller (optional)
 192  *
 193  * desc must contain valid dma-mapped (bus physical) address pointers.
 194  * callback must check err and feedback in descriptor header
 195  * for device processing status.
 196  */
 197 int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
 198                    void (*callback)(struct device *dev,
 199                                     struct talitos_desc *desc,
 200                                     void *context, int error),
 201                    void *context)
 202 {
 203         struct talitos_private *priv = dev_get_drvdata(dev);
 204         struct talitos_request *request;
 205         unsigned long flags;
 206         int head;
 207
 208         spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
 209
 210         if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
 211                 /* h/w fifo is full */
 212                 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
 213                 return -EAGAIN;
 214         }
 215
 216         head = priv->chan[ch].head;
 217         request = &priv->chan[ch].fifo[head];
 218
 219         /* map descriptor and save caller data */
 220         request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
 221                                            DMA_BIDIRECTIONAL);
 222         request->callback = callback;
 223         request->context = context;
 224
 225         /* increment fifo head */
 226         priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
 227
 228         smp_wmb();
 229         request->desc = desc;
 230
 231         /* GO! */
 232         wmb();
 233         out_be32(priv->chan[ch].reg + TALITOS_FF,
 234                  upper_32_bits(request->dma_desc));
 235         out_be32(priv->chan[ch].reg + TALITOS_FF_LO,
 236                  lower_32_bits(request->dma_desc));
 237
 238         spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
 239
 240         return -EINPROGRESS;
 241 }
 242 EXPORT_SYMBOL(talitos_submit);
 243
 244 /*
 245  * process what was done, notify callback of error if not
 246  */
 247 static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
 248 {
 249         struct talitos_private *priv = dev_get_drvdata(dev);
 250         struct talitos_request *request, saved_req;
 251         unsigned long flags;
 252         int tail, status;
 253
 254         spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
 255
 256         tail = priv->chan[ch].tail;
 257         while (priv->chan[ch].fifo[tail].desc) {
 258                 request = &priv->chan[ch].fifo[tail];
 259
 260                 /* descriptors with their done bits set don't get the error */
 261                 rmb();
 262                 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
 263                         status = 0;
 264                 else
 265                         if (!error)
 266                                 break;
 267                         else
 268                                 status = error;
 269
 270                 dma_unmap_single(dev, request->dma_desc,
 271                                  sizeof(struct talitos_desc),
 272                                  DMA_BIDIRECTIONAL);
 273
 274                 /* copy entries so we can call callback outside lock */
 275                 saved_req.desc = request->desc;
 276                 saved_req.callback = request->callback;
 277                 saved_req.context = request->context;
 278
 279                 /* release request entry in fifo */
 280                 smp_wmb();
 281                 request->desc = NULL;
 282
 283                 /* increment fifo tail */
 284                 priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
 285
 286                 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
 287
 288                 atomic_dec(&priv->chan[ch].submit_count);
 289
 290                 saved_req.callback(dev, saved_req.desc, saved_req.context,
 291                                    status);
 292                 /* channel may resume processing in single desc error case */
 293                 if (error && !reset_ch && status == error)
 294                         return;
 295                 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
 296                 tail = priv->chan[ch].tail;
 297         }
 298
 299         spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
 300 }
 301
 302 /*
 303  * process completed requests for channels that have done status
 304  */
 305 #define DEF_TALITOS_DONE(name, ch_done_mask)                            \
 306 static void talitos_done_##name(unsigned long data)                     \
 307 {                                                                       \
 308         struct device *dev = (struct device *)data;                     \
 309         struct talitos_private *priv = dev_get_drvdata(dev);            \
 310         unsigned long flags;                                            \
 311                                                                         \
 312         if (ch_done_mask & 1)                                           \
 313                 flush_channel(dev, 0, 0, 0);                            \
 314         if (priv->num_channels == 1)                                    \
 315                 goto out;                                               \
 316         if (ch_done_mask & (1 << 2))                                    \
 317                 flush_channel(dev, 1, 0, 0);                            \
 318         if (ch_done_mask & (1 << 4))                                    \
 319                 flush_channel(dev, 2, 0, 0);                            \
 320         if (ch_done_mask & (1 << 6))                                    \
 321                 flush_channel(dev, 3, 0, 0);                            \
 322                                                                         \
 323 out:                                                                    \
 324         /* At this point, all completed channels have been processed */ \
 325         /* Unmask done interrupts for channels completed later on. */   \
 326         spin_lock_irqsave(&priv->reg_lock, flags);                      \
 327         setbits32(priv->reg + TALITOS_IMR, ch_done_mask);               \
 328         setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);     \
 329         spin_unlock_irqrestore(&priv->reg_lock, flags);                 \
 330 }
 331 DEF_TALITOS_DONE(4ch, TALITOS_ISR_4CHDONE)
 332 DEF_TALITOS_DONE(ch0_2, TALITOS_ISR_CH_0_2_DONE)
 333 DEF_TALITOS_DONE(ch1_3, TALITOS_ISR_CH_1_3_DONE)
 334
 335 /*
 336  * locate current (offending) descriptor
 337  */
 338 static u32 current_desc_hdr(struct device *dev, int ch)
 339 {
 340         struct talitos_private *priv = dev_get_drvdata(dev);
 341         int tail, iter;
 342         dma_addr_t cur_desc;
 343
 344         cur_desc = ((u64)in_be32(priv->chan[ch].reg + TALITOS_CDPR)) << 32;
 345         cur_desc |= in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO);
 346
 347         if (!cur_desc) {
 348                 dev_err(dev, "CDPR is NULL, giving up search for offending descriptor\n");
 349                 return 0;
 350         }
 351
 352         tail = priv->chan[ch].tail;
 353
 354         iter = tail;
 355         while (priv->chan[ch].fifo[iter].dma_desc != cur_desc) {
 356                 iter = (iter + 1) & (priv->fifo_len - 1);
 357                 if (iter == tail) {
 358                         dev_err(dev, "couldn't locate current descriptor\n");
 359                         return 0;
 360                 }
 361         }
 362
 363         return priv->chan[ch].fifo[iter].desc->hdr;
 364 }
 365
 366 /*
 367  * user diagnostics; report root cause of error based on execution unit status
 368  */
 369 static void report_eu_error(struct device *dev, int ch, u32 desc_hdr)
 370 {
 371         struct talitos_private *priv = dev_get_drvdata(dev);
 372         int i;
 373
 374         if (!desc_hdr)
 375                 desc_hdr = in_be32(priv->chan[ch].reg + TALITOS_DESCBUF);
 376
 377         switch (desc_hdr & DESC_HDR_SEL0_MASK) {
 378         case DESC_HDR_SEL0_AFEU:
 379                 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
 380                         in_be32(priv->reg + TALITOS_AFEUISR),
 381                         in_be32(priv->reg + TALITOS_AFEUISR_LO));
 382                 break;
 383         case DESC_HDR_SEL0_DEU:
 384                 dev_err(dev, "DEUISR 0x%08x_%08x\n",
 385                         in_be32(priv->reg + TALITOS_DEUISR),
 386                         in_be32(priv->reg + TALITOS_DEUISR_LO));
 387                 break;
 388         case DESC_HDR_SEL0_MDEUA:
 389         case DESC_HDR_SEL0_MDEUB:
 390                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
 391                         in_be32(priv->reg + TALITOS_MDEUISR),
 392                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
 393                 break;
 394         case DESC_HDR_SEL0_RNG:
 395                 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
 396                         in_be32(priv->reg + TALITOS_RNGUISR),
 397                         in_be32(priv->reg + TALITOS_RNGUISR_LO));
 398                 break;
 399         case DESC_HDR_SEL0_PKEU:
 400                 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
 401                         in_be32(priv->reg + TALITOS_PKEUISR),
 402                         in_be32(priv->reg + TALITOS_PKEUISR_LO));
 403                 break;
 404         case DESC_HDR_SEL0_AESU:
 405                 dev_err(dev, "AESUISR 0x%08x_%08x\n",
 406                         in_be32(priv->reg + TALITOS_AESUISR),
 407                         in_be32(priv->reg + TALITOS_AESUISR_LO));
 408                 break;
 409         case DESC_HDR_SEL0_CRCU:
 410                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
 411                         in_be32(priv->reg + TALITOS_CRCUISR),
 412                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
 413                 break;
 414         case DESC_HDR_SEL0_KEU:
 415                 dev_err(dev, "KEUISR 0x%08x_%08x\n",
 416                         in_be32(priv->reg + TALITOS_KEUISR),
 417                         in_be32(priv->reg + TALITOS_KEUISR_LO));
 418                 break;
 419         }
 420
 421         switch (desc_hdr & DESC_HDR_SEL1_MASK) {
 422         case DESC_HDR_SEL1_MDEUA:
 423         case DESC_HDR_SEL1_MDEUB:
 424                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
 425                         in_be32(priv->reg + TALITOS_MDEUISR),
 426                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
 427                 break;
 428         case DESC_HDR_SEL1_CRCU:
 429                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
 430                         in_be32(priv->reg + TALITOS_CRCUISR),
 431                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
 432                 break;
 433         }
 434
 435         for (i = 0; i < 8; i++)
 436                 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
 437                         in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i),
 438                         in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
 439 }
 440
 441 /*
 442  * recover from error interrupts
 443  */
 444 static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
 445 {
 446         struct talitos_private *priv = dev_get_drvdata(dev);
 447         unsigned int timeout = TALITOS_TIMEOUT;
 448         int ch, error, reset_dev = 0, reset_ch = 0;
 449         u32 v, v_lo;
 450
 451         for (ch = 0; ch < priv->num_channels; ch++) {
 452                 /* skip channels without errors */
 453                 if (!(isr & (1 << (ch * 2 + 1))))
 454                         continue;
 455
 456                 error = -EINVAL;
 457
 458                 v = in_be32(priv->chan[ch].reg + TALITOS_CCPSR);
 459                 v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
 460
 461                 if (v_lo & TALITOS_CCPSR_LO_DOF) {
 462                         dev_err(dev, "double fetch fifo overflow error\n");
 463                         error = -EAGAIN;
 464                         reset_ch = 1;
 465                 }
 466                 if (v_lo & TALITOS_CCPSR_LO_SOF) {
 467                         /* h/w dropped descriptor */
 468                         dev_err(dev, "single fetch fifo overflow error\n");
 469                         error = -EAGAIN;
 470                 }
 471                 if (v_lo & TALITOS_CCPSR_LO_MDTE)
 472                         dev_err(dev, "master data transfer error\n");
 473                 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
 474                         dev_err(dev, "s/g data length zero error\n");
 475                 if (v_lo & TALITOS_CCPSR_LO_FPZ)
 476                         dev_err(dev, "fetch pointer zero error\n");
 477                 if (v_lo & TALITOS_CCPSR_LO_IDH)
 478                         dev_err(dev, "illegal descriptor header error\n");
 479                 if (v_lo & TALITOS_CCPSR_LO_IEU)
 480                         dev_err(dev, "invalid execution unit error\n");
 481                 if (v_lo & TALITOS_CCPSR_LO_EU)
 482                         report_eu_error(dev, ch, current_desc_hdr(dev, ch));
 483                 if (v_lo & TALITOS_CCPSR_LO_GB)
 484                         dev_err(dev, "gather boundary error\n");
 485                 if (v_lo & TALITOS_CCPSR_LO_GRL)
 486                         dev_err(dev, "gather return/length error\n");
 487                 if (v_lo & TALITOS_CCPSR_LO_SB)
 488                         dev_err(dev, "scatter boundary error\n");
 489                 if (v_lo & TALITOS_CCPSR_LO_SRL)
 490                         dev_err(dev, "scatter return/length error\n");
 491
 492                 flush_channel(dev, ch, error, reset_ch);
 493
 494                 if (reset_ch) {
 495                         reset_channel(dev, ch);
 496                 } else {
 497                         setbits32(priv->chan[ch].reg + TALITOS_CCCR,
 498                                   TALITOS_CCCR_CONT);
 499                         setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
 500                         while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
 501                                TALITOS_CCCR_CONT) && --timeout)
 502                                 cpu_relax();
 503                         if (timeout == 0) {
 504                                 dev_err(dev, "failed to restart channel %d\n",
 505                                         ch);
 506                                 reset_dev = 1;
 507                         }
 508                 }
 509         }
 510         if (reset_dev || isr & ~TALITOS_ISR_4CHERR || isr_lo) {
 511                 dev_err(dev, "done overflow, internal time out, or rngu error: "
 512                         "ISR 0x%08x_%08x\n", isr, isr_lo);
 513
 514                 /* purge request queues */
 515                 for (ch = 0; ch < priv->num_channels; ch++)
 516                         flush_channel(dev, ch, -EIO, 1);
 517
 518                 /* reset and reinitialize the device */
 519                 init_device(dev);
 520         }
 521 }
 522
 523 #define DEF_TALITOS_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet)           \
 524 static irqreturn_t talitos_interrupt_##name(int irq, void *data)               \
 525 {                                                                              \
 526         struct device *dev = data;                                             \
 527         struct talitos_private *priv = dev_get_drvdata(dev);                   \
 528         u32 isr, isr_lo;                                                       \
 529         unsigned long flags;                                                   \
 530                                                                                \
 531         spin_lock_irqsave(&priv->reg_lock, flags);                             \
 532         isr = in_be32(priv->reg + TALITOS_ISR);                                \
 533         isr_lo = in_be32(priv->reg + TALITOS_ISR_LO);                          \
 534         /* Acknowledge interrupt */                                            \
 535         out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
 536         out_be32(priv->reg + TALITOS_ICR_LO, isr_lo);                          \
 537                                                                                \
 538         if (unlikely(isr & ch_err_mask || isr_lo)) {                           \
 539                 spin_unlock_irqrestore(&priv->reg_lock, flags);                \
 540                 talitos_error(dev, isr & ch_err_mask, isr_lo);                 \
 541         }                                                                      \
 542         else {                                                                 \
 543                 if (likely(isr & ch_done_mask)) {                              \
 544                         /* mask further done interrupts. */                    \
 545                         clrbits32(priv->reg + TALITOS_IMR, ch_done_mask);      \
 546                         /* done_task will unmask done interrupts at exit */    \
 547                         tasklet_schedule(&priv->done_task[tlet]);              \
 548                 }                                                              \
 549                 spin_unlock_irqrestore(&priv->reg_lock, flags);                \
 550         }                                                                      \
 551                                                                                \
 552         return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED :  \
 553                                                                 IRQ_NONE;      \
 554 }
 555 DEF_TALITOS_INTERRUPT(4ch, TALITOS_ISR_4CHDONE, TALITOS_ISR_4CHERR, 0)
 556 DEF_TALITOS_INTERRUPT(ch0_2, TALITOS_ISR_CH_0_2_DONE, TALITOS_ISR_CH_0_2_ERR, 0)
 557 DEF_TALITOS_INTERRUPT(ch1_3, TALITOS_ISR_CH_1_3_DONE, TALITOS_ISR_CH_1_3_ERR, 1)
 558
 559 /*
 560  * hwrng
 561  */
 562 static int talitos_rng_data_present(struct hwrng *rng, int wait)
 563 {
 564         struct device *dev = (struct device *)rng->priv;
 565         struct talitos_private *priv = dev_get_drvdata(dev);
 566         u32 ofl;
 567         int i;
 568
 569         for (i = 0; i < 20; i++) {
 570                 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
 571                       TALITOS_RNGUSR_LO_OFL;
 572                 if (ofl || !wait)
 573                         break;
 574                 udelay(10);
 575         }
 576
 577         return !!ofl;
 578 }
 579
 580 static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
 581 {
 582         struct device *dev = (struct device *)rng->priv;
 583         struct talitos_private *priv = dev_get_drvdata(dev);
 584
 585         /* rng fifo requires 64-bit accesses */
 586         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
 587         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
 588
 589         return sizeof(u32);
 590 }
 591
 592 static int talitos_rng_init(struct hwrng *rng)
 593 {
 594         struct device *dev = (struct device *)rng->priv;
 595         struct talitos_private *priv = dev_get_drvdata(dev);
 596         unsigned int timeout = TALITOS_TIMEOUT;
 597
 598         setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
 599         while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
 600                && --timeout)
 601                 cpu_relax();
 602         if (timeout == 0) {
 603                 dev_err(dev, "failed to reset rng hw\n");
 604                 return -ENODEV;
 605         }
 606
 607         /* start generating */
 608         setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
 609
 610         return 0;
 611 }
 612
 613 static int talitos_register_rng(struct device *dev)
 614 {
 615         struct talitos_private *priv = dev_get_drvdata(dev);
 616
 617         priv->rng.name          = dev_driver_string(dev),
 618         priv->rng.init          = talitos_rng_init,
 619         priv->rng.data_present  = talitos_rng_data_present,
 620         priv->rng.data_read     = talitos_rng_data_read,
 621         priv->rng.priv          = (unsigned long)dev;
 622
 623         return hwrng_register(&priv->rng);
 624 }
 625
 626 static void talitos_unregister_rng(struct device *dev)
 627 {
 628         struct talitos_private *priv = dev_get_drvdata(dev);
 629
 630         hwrng_unregister(&priv->rng);
 631 }
 632
 633 /*
 634  * crypto alg
 635  */
 636 #define TALITOS_CRA_PRIORITY            3000
 637 #define TALITOS_MAX_KEY_SIZE            96
 638 #define TALITOS_MAX_IV_LENGTH           16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
 639
 640 struct talitos_ctx {
 641         struct device *dev;
 642         int ch;
 643         __be32 desc_hdr_template;
 644         u8 key[TALITOS_MAX_KEY_SIZE];
 645         u8 iv[TALITOS_MAX_IV_LENGTH];
 646         unsigned int keylen;
 647         unsigned int enckeylen;
 648         unsigned int authkeylen;
 649         unsigned int authsize;
 650 };
 651
 652 #define HASH_MAX_BLOCK_SIZE             SHA512_BLOCK_SIZE
 653 #define TALITOS_MDEU_MAX_CONTEXT_SIZE   TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
 654
 655 struct talitos_ahash_req_ctx {
 656         u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
 657         unsigned int hw_context_size;
 658         u8 buf[HASH_MAX_BLOCK_SIZE];
 659         u8 bufnext[HASH_MAX_BLOCK_SIZE];
 660         unsigned int swinit;
 661         unsigned int first;
 662         unsigned int last;
 663         unsigned int to_hash_later;
 664         u64 nbuf;
 665         struct scatterlist bufsl[2];
 666         struct scatterlist *psrc;
 667 };
 668
 669 static int aead_setauthsize(struct crypto_aead *authenc,
 670                             unsigned int authsize)
 671 {
 672         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 673
 674         ctx->authsize = authsize;
 675
 676         return 0;
 677 }
 678
 679 static int aead_setkey(struct crypto_aead *authenc,
 680                        const u8 *key, unsigned int keylen)
 681 {
 682         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 683         struct crypto_authenc_keys keys;
 684
 685         if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
 686                 goto badkey;
 687
 688         if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE)
 689                 goto badkey;
 690
 691         memcpy(ctx->key, keys.authkey, keys.authkeylen);
 692         memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen);
 693
 694         ctx->keylen = keys.authkeylen + keys.enckeylen;
 695         ctx->enckeylen = keys.enckeylen;
 696         ctx->authkeylen = keys.authkeylen;
 697
 698         return 0;
 699
 700 badkey:
 701         crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
 702         return -EINVAL;
 703 }
 704
 705 /*
 706  * talitos_edesc - s/w-extended descriptor
 707  * @assoc_nents: number of segments in associated data scatterlist
 708  * @src_nents: number of segments in input scatterlist
 709  * @dst_nents: number of segments in output scatterlist
 710  * @assoc_chained: whether assoc is chained or not
 711  * @src_chained: whether src is chained or not
 712  * @dst_chained: whether dst is chained or not
 713  * @iv_dma: dma address of iv for checking continuity and link table
 714  * @dma_len: length of dma mapped link_tbl space
 715  * @dma_link_tbl: bus physical address of link_tbl
 716  * @desc: h/w descriptor
 717  * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
 718  *
 719  * if decrypting (with authcheck), or either one of src_nents or dst_nents
 720  * is greater than 1, an integrity check value is concatenated to the end
 721  * of link_tbl data
 722  */
 723 struct talitos_edesc {
 724         int assoc_nents;
 725         int src_nents;
 726         int dst_nents;
 727         bool assoc_chained;
 728         bool src_chained;
 729         bool dst_chained;
 730         dma_addr_t iv_dma;
 731         int dma_len;
 732         dma_addr_t dma_link_tbl;
 733         struct talitos_desc desc;
 734         struct talitos_ptr link_tbl[0];
 735 };
 736
 737 static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
 738                           unsigned int nents, enum dma_data_direction dir,
 739                           bool chained)
 740 {
 741         if (unlikely(chained))
 742                 while (sg) {
 743                         dma_map_sg(dev, sg, 1, dir);
 744                         sg = sg_next(sg);
 745                 }
 746         else
 747                 dma_map_sg(dev, sg, nents, dir);
 748         return nents;
 749 }
 750
 751 static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
 752                                    enum dma_data_direction dir)
 753 {
 754         while (sg) {
 755                 dma_unmap_sg(dev, sg, 1, dir);
 756                 sg = sg_next(sg);
 757         }
 758 }
 759
 760 static void talitos_sg_unmap(struct device *dev,
 761                              struct talitos_edesc *edesc,
 762                              struct scatterlist *src,
 763                              struct scatterlist *dst)
 764 {
 765         unsigned int src_nents = edesc->src_nents ? : 1;
 766         unsigned int dst_nents = edesc->dst_nents ? : 1;
 767
 768         if (src != dst) {
 769                 if (edesc->src_chained)
 770                         talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
 771                 else
 772                         dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
 773
 774                 if (dst) {
 775                         if (edesc->dst_chained)
 776                                 talitos_unmap_sg_chain(dev, dst,
 777                                                        DMA_FROM_DEVICE);
 778                         else
 779                                 dma_unmap_sg(dev, dst, dst_nents,
 780                                              DMA_FROM_DEVICE);
 781                 }
 782         } else
 783                 if (edesc->src_chained)
 784                         talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
 785                 else
 786                         dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
 787 }
 788
 789 static void ipsec_esp_unmap(struct device *dev,
 790                             struct talitos_edesc *edesc,
 791                             struct aead_request *areq)
 792 {
 793         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
 794         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
 795         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
 796         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
 797
 798         if (edesc->assoc_chained)
 799                 talitos_unmap_sg_chain(dev, areq->assoc, DMA_TO_DEVICE);
 800         else if (areq->assoclen)
 801                 /* assoc_nents counts also for IV in non-contiguous cases */
 802                 dma_unmap_sg(dev, areq->assoc,
 803                              edesc->assoc_nents ? edesc->assoc_nents - 1 : 1,
 804                              DMA_TO_DEVICE);
 805
 806         talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
 807
 808         if (edesc->dma_len)
 809                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
 810                                  DMA_BIDIRECTIONAL);
 811 }
 812
 813 /*
 814  * ipsec_esp descriptor callbacks
 815  */
 816 static void ipsec_esp_encrypt_done(struct device *dev,
 817                                    struct talitos_desc *desc, void *context,
 818                                    int err)
 819 {
 820         struct aead_request *areq = context;
 821         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
 822         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 823         struct talitos_edesc *edesc;
 824         struct scatterlist *sg;
 825         void *icvdata;
 826
 827         edesc = container_of(desc, struct talitos_edesc, desc);
 828
 829         ipsec_esp_unmap(dev, edesc, areq);
 830
 831         /* copy the generated ICV to dst */
 832         if (edesc->dst_nents) {
 833                 icvdata = &edesc->link_tbl[edesc->src_nents +
 834                                            edesc->dst_nents + 2 +
 835                                            edesc->assoc_nents];
 836                 sg = sg_last(areq->dst, edesc->dst_nents);
 837                 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
 838                        icvdata, ctx->authsize);
 839         }
 840
 841         kfree(edesc);
 842
 843         aead_request_complete(areq, err);
 844 }
 845
 846 static void ipsec_esp_decrypt_swauth_done(struct device *dev,
 847                                           struct talitos_desc *desc,
 848                                           void *context, int err)
 849 {
 850         struct aead_request *req = context;
 851         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
 852         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 853         struct talitos_edesc *edesc;
 854         struct scatterlist *sg;
 855         void *icvdata;
 856
 857         edesc = container_of(desc, struct talitos_edesc, desc);
 858
 859         ipsec_esp_unmap(dev, edesc, req);
 860
 861         if (!err) {
 862                 /* auth check */
 863                 if (edesc->dma_len)
 864                         icvdata = &edesc->link_tbl[edesc->src_nents +
 865                                                    edesc->dst_nents + 2 +
 866                                                    edesc->assoc_nents];
 867                 else
 868                         icvdata = &edesc->link_tbl[0];
 869
 870                 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
 871                 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
 872                              ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
 873         }
 874
 875         kfree(edesc);
 876
 877         aead_request_complete(req, err);
 878 }
 879
 880 static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
 881                                           struct talitos_desc *desc,
 882                                           void *context, int err)
 883 {
 884         struct aead_request *req = context;
 885         struct talitos_edesc *edesc;
 886
 887         edesc = container_of(desc, struct talitos_edesc, desc);
 888
 889         ipsec_esp_unmap(dev, edesc, req);
 890
 891         /* check ICV auth status */
 892         if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
 893                      DESC_HDR_LO_ICCR1_PASS))
 894                 err = -EBADMSG;
 895
 896         kfree(edesc);
 897
 898         aead_request_complete(req, err);
 899 }
 900
 901 /*
 902  * convert scatterlist to SEC h/w link table format
 903  * stop at cryptlen bytes
 904  */
 905 static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
 906                            int cryptlen, struct talitos_ptr *link_tbl_ptr)
 907 {
 908         int n_sg = sg_count;
 909
 910         while (n_sg--) {
 911                 to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
 912                 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
 913                 link_tbl_ptr->j_extent = 0;
 914                 link_tbl_ptr++;
 915                 cryptlen -= sg_dma_len(sg);
 916                 sg = sg_next(sg);
 917         }
 918
 919         /* adjust (decrease) last one (or two) entry's len to cryptlen */
 920         link_tbl_ptr--;
 921         while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
 922                 /* Empty this entry, and move to previous one */
 923                 cryptlen += be16_to_cpu(link_tbl_ptr->len);
 924                 link_tbl_ptr->len = 0;
 925                 sg_count--;
 926                 link_tbl_ptr--;
 927         }
 928         be16_add_cpu(&link_tbl_ptr->len, cryptlen);
 929
 930         /* tag end of link table */
 931         link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
 932
 933         return sg_count;
 934 }
 935
 936 /*
 937  * fill in and submit ipsec_esp descriptor
 938  */
 939 static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
 940                      u64 seq, void (*callback) (struct device *dev,
 941                                                 struct talitos_desc *desc,
 942                                                 void *context, int error))
 943 {
 944         struct crypto_aead *aead = crypto_aead_reqtfm(areq);
 945         struct talitos_ctx *ctx = crypto_aead_ctx(aead);
 946         struct device *dev = ctx->dev;
 947         struct talitos_desc *desc = &edesc->desc;
 948         unsigned int cryptlen = areq->cryptlen;
 949         unsigned int authsize = ctx->authsize;
 950         unsigned int ivsize = crypto_aead_ivsize(aead);
 951         int sg_count, ret;
 952         int sg_link_tbl_len;
 953
 954         /* hmac key */
 955         map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
 956                                0, DMA_TO_DEVICE);
 957
 958         /* hmac data */
 959         desc->ptr[1].len = cpu_to_be16(areq->assoclen + ivsize);
 960         if (edesc->assoc_nents) {
 961                 int tbl_off = edesc->src_nents + edesc->dst_nents + 2;
 962                 struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
 963
 964                 to_talitos_ptr(&desc->ptr[1], edesc->dma_link_tbl + tbl_off *
 965                                sizeof(struct talitos_ptr));
 966                 desc->ptr[1].j_extent = DESC_PTR_LNKTBL_JUMP;
 967
 968                 /* assoc_nents - 1 entries for assoc, 1 for IV */
 969                 sg_count = sg_to_link_tbl(areq->assoc, edesc->assoc_nents - 1,
 970                                           areq->assoclen, tbl_ptr);
 971
 972                 /* add IV to link table */
 973                 tbl_ptr += sg_count - 1;
 974                 tbl_ptr->j_extent = 0;
 975                 tbl_ptr++;
 976                 to_talitos_ptr(tbl_ptr, edesc->iv_dma);
 977                 tbl_ptr->len = cpu_to_be16(ivsize);
 978                 tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
 979
 980                 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
 981                                            edesc->dma_len, DMA_BIDIRECTIONAL);
 982         } else {
 983                 if (areq->assoclen)
 984                         to_talitos_ptr(&desc->ptr[1],
 985                                        sg_dma_address(areq->assoc));
 986                 else
 987                         to_talitos_ptr(&desc->ptr[1], edesc->iv_dma);
 988                 desc->ptr[1].j_extent = 0;
 989         }
 990
 991         /* cipher iv */
 992         to_talitos_ptr(&desc->ptr[2], edesc->iv_dma);
 993         desc->ptr[2].len = cpu_to_be16(ivsize);
 994         desc->ptr[2].j_extent = 0;
 995         /* Sync needed for the aead_givencrypt case */
 996         dma_sync_single_for_device(dev, edesc->iv_dma, ivsize, DMA_TO_DEVICE);
 997
 998         /* cipher key */
 999         map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
1000                                (char *)&ctx->key + ctx->authkeylen, 0,
1001                                DMA_TO_DEVICE);
1002
1003         /*
1004          * cipher in
1005          * map and adjust cipher len to aead request cryptlen.
1006          * extent is bytes of HMAC postpended to ciphertext,
1007          * typically 12 for ipsec
1008          */
1009         desc->ptr[4].len = cpu_to_be16(cryptlen);
1010         desc->ptr[4].j_extent = authsize;
1011
1012         sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1013                                   (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1014                                                            : DMA_TO_DEVICE,
1015                                   edesc->src_chained);
1016
1017         if (sg_count == 1) {
1018                 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src));
1019         } else {
1020                 sg_link_tbl_len = cryptlen;
1021
1022                 if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
1023                         sg_link_tbl_len = cryptlen + authsize;
1024
1025                 sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
1026                                           &edesc->link_tbl[0]);
1027                 if (sg_count > 1) {
1028                         desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1029                         to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl);
1030                         dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1031                                                    edesc->dma_len,
1032                                                    DMA_BIDIRECTIONAL);
1033                 } else {
1034                         /* Only one segment now, so no link tbl needed */
1035                         to_talitos_ptr(&desc->ptr[4],
1036                                        sg_dma_address(areq->src));
1037                 }
1038         }
1039
1040         /* cipher out */
1041         desc->ptr[5].len = cpu_to_be16(cryptlen);
1042         desc->ptr[5].j_extent = authsize;
1043
1044         if (areq->src != areq->dst)
1045                 sg_count = talitos_map_sg(dev, areq->dst,
1046                                           edesc->dst_nents ? : 1,
1047                                           DMA_FROM_DEVICE, edesc->dst_chained);
1048
1049         if (sg_count == 1) {
1050                 to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst));
1051         } else {
1052                 int tbl_off = edesc->src_nents + 1;
1053                 struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
1054
1055                 to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
1056                                tbl_off * sizeof(struct talitos_ptr));
1057                 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1058                                           tbl_ptr);
1059
1060                 /* Add an entry to the link table for ICV data */
1061                 tbl_ptr += sg_count - 1;
1062                 tbl_ptr->j_extent = 0;
1063                 tbl_ptr++;
1064                 tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1065                 tbl_ptr->len = cpu_to_be16(authsize);
1066
1067                 /* icv data follows link tables */
1068                 to_talitos_ptr(tbl_ptr, edesc->dma_link_tbl +
1069                                (tbl_off + edesc->dst_nents + 1 +
1070                                 edesc->assoc_nents) *
1071                                sizeof(struct talitos_ptr));
1072                 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
1073                 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1074                                            edesc->dma_len, DMA_BIDIRECTIONAL);
1075         }
1076
1077         /* iv out */
1078         map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
1079                                DMA_FROM_DEVICE);
1080
1081         ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1082         if (ret != -EINPROGRESS) {
1083                 ipsec_esp_unmap(dev, edesc, areq);
1084                 kfree(edesc);
1085         }
1086         return ret;
1087 }
1088
1089 /*
1090  * derive number of elements in scatterlist
1091  */
1092 static int sg_count(struct scatterlist *sg_list, int nbytes, bool *chained)
1093 {
1094         struct scatterlist *sg = sg_list;
1095         int sg_nents = 0;
1096
1097         *chained = false;
1098         while (nbytes > 0) {
1099                 sg_nents++;
1100                 nbytes -= sg->length;
1101                 if (!sg_is_last(sg) && (sg + 1)->length == 0)
1102                         *chained = true;
1103                 sg = sg_next(sg);
1104         }
1105
1106         return sg_nents;
1107 }
1108
1109 /*
1110  * allocate and map the extended descriptor
1111  */
1112 static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1113                                                  struct scatterlist *assoc,
1114                                                  struct scatterlist *src,
1115                                                  struct scatterlist *dst,
1116                                                  u8 *iv,
1117                                                  unsigned int assoclen,
1118                                                  unsigned int cryptlen,
1119                                                  unsigned int authsize,
1120                                                  unsigned int ivsize,
1121                                                  int icv_stashing,
1122                                                  u32 cryptoflags,
1123                                                  bool encrypt)
1124 {
1125         struct talitos_edesc *edesc;
1126         int assoc_nents = 0, src_nents, dst_nents, alloc_len, dma_len;
1127         bool assoc_chained = false, src_chained = false, dst_chained = false;
1128         dma_addr_t iv_dma = 0;
1129         gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
1130                       GFP_ATOMIC;
1131
1132         if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) {
1133                 dev_err(dev, "length exceeds h/w max limit\n");
1134                 return ERR_PTR(-EINVAL);
1135         }
1136
1137         if (ivsize)
1138                 iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE);
1139
1140         if (assoclen) {
1141                 /*
1142                  * Currently it is assumed that iv is provided whenever assoc
1143                  * is.
1144                  */
1145                 BUG_ON(!iv);
1146
1147                 assoc_nents = sg_count(assoc, assoclen, &assoc_chained);
1148                 talitos_map_sg(dev, assoc, assoc_nents, DMA_TO_DEVICE,
1149                                assoc_chained);
1150                 assoc_nents = (assoc_nents == 1) ? 0 : assoc_nents;
1151
1152                 if (assoc_nents || sg_dma_address(assoc) + assoclen != iv_dma)
1153                         assoc_nents = assoc_nents ? assoc_nents + 1 : 2;
1154         }
1155
1156         if (!dst || dst == src) {
1157                 src_nents = sg_count(src, cryptlen + authsize, &src_chained);
1158                 src_nents = (src_nents == 1) ? 0 : src_nents;
1159                 dst_nents = dst ? src_nents : 0;
1160         } else { /* dst && dst != src*/
1161                 src_nents = sg_count(src, cryptlen + (encrypt ? 0 : authsize),
1162                                      &src_chained);
1163                 src_nents = (src_nents == 1) ? 0 : src_nents;
1164                 dst_nents = sg_count(dst, cryptlen + (encrypt ? authsize : 0),
1165                                      &dst_chained);
1166                 dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1167         }
1168
1169         /*
1170          * allocate space for base edesc plus the link tables,
1171          * allowing for two separate entries for ICV and generated ICV (+ 2),
1172          * and the ICV data itself
1173          */
1174         alloc_len = sizeof(struct talitos_edesc);
1175         if (assoc_nents || src_nents || dst_nents) {
1176                 dma_len = (src_nents + dst_nents + 2 + assoc_nents) *
1177                           sizeof(struct talitos_ptr) + authsize;
1178                 alloc_len += dma_len;
1179         } else {
1180                 dma_len = 0;
1181                 alloc_len += icv_stashing ? authsize : 0;
1182         }
1183
1184         edesc = kmalloc(alloc_len, GFP_DMA | flags);
1185         if (!edesc) {
1186                 if (assoc_chained)
1187                         talitos_unmap_sg_chain(dev, assoc, DMA_TO_DEVICE);
1188                 else if (assoclen)
1189                         dma_unmap_sg(dev, assoc,
1190                                      assoc_nents ? assoc_nents - 1 : 1,
1191                                      DMA_TO_DEVICE);
1192
1193                 if (iv_dma)
1194                         dma_unmap_single(dev, iv_dma, ivsize, DMA_TO_DEVICE);
1195
1196                 dev_err(dev, "could not allocate edescriptor\n");
1197                 return ERR_PTR(-ENOMEM);
1198         }
1199
1200         edesc->assoc_nents = assoc_nents;
1201         edesc->src_nents = src_nents;
1202         edesc->dst_nents = dst_nents;
1203         edesc->assoc_chained = assoc_chained;
1204         edesc->src_chained = src_chained;
1205         edesc->dst_chained = dst_chained;
1206         edesc->iv_dma = iv_dma;
1207         edesc->dma_len = dma_len;
1208         if (dma_len)
1209                 edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
1210                                                      edesc->dma_len,
1211                                                      DMA_BIDIRECTIONAL);
1212
1213         return edesc;
1214 }
1215
1216 static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u8 *iv,
1217                                               int icv_stashing, bool encrypt)
1218 {
1219         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1220         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1221         unsigned int ivsize = crypto_aead_ivsize(authenc);
1222
1223         return talitos_edesc_alloc(ctx->dev, areq->assoc, areq->src, areq->dst,
1224                                    iv, areq->assoclen, areq->cryptlen,
1225                                    ctx->authsize, ivsize, icv_stashing,
1226                                    areq->base.flags, encrypt);
1227 }
1228
1229 static int aead_encrypt(struct aead_request *req)
1230 {
1231         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1232         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1233         struct talitos_edesc *edesc;
1234
1235         /* allocate extended descriptor */
1236         edesc = aead_edesc_alloc(req, req->iv, 0, true);
1237         if (IS_ERR(edesc))
1238                 return PTR_ERR(edesc);
1239
1240         /* set encrypt */
1241         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1242
1243         return ipsec_esp(edesc, req, 0, ipsec_esp_encrypt_done);
1244 }
1245
1246 static int aead_decrypt(struct aead_request *req)
1247 {
1248         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1249         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1250         unsigned int authsize = ctx->authsize;
1251         struct talitos_private *priv = dev_get_drvdata(ctx->dev);
1252         struct talitos_edesc *edesc;
1253         struct scatterlist *sg;
1254         void *icvdata;
1255
1256         req->cryptlen -= authsize;
1257
1258         /* allocate extended descriptor */
1259         edesc = aead_edesc_alloc(req, req->iv, 1, false);
1260         if (IS_ERR(edesc))
1261                 return PTR_ERR(edesc);
1262
1263         if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
1264             ((!edesc->src_nents && !edesc->dst_nents) ||
1265              priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
1266
1267                 /* decrypt and check the ICV */
1268                 edesc->desc.hdr = ctx->desc_hdr_template |
1269                                   DESC_HDR_DIR_INBOUND |
1270                                   DESC_HDR_MODE1_MDEU_CICV;
1271
1272                 /* reset integrity check result bits */
1273                 edesc->desc.hdr_lo = 0;
1274
1275                 return ipsec_esp(edesc, req, 0, ipsec_esp_decrypt_hwauth_done);
1276         }
1277
1278         /* Have to check the ICV with software */
1279         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1280
1281         /* stash incoming ICV for later cmp with ICV generated by the h/w */
1282         if (edesc->dma_len)
1283                 icvdata = &edesc->link_tbl[edesc->src_nents +
1284                                            edesc->dst_nents + 2 +
1285                                            edesc->assoc_nents];
1286         else
1287                 icvdata = &edesc->link_tbl[0];
1288
1289         sg = sg_last(req->src, edesc->src_nents ? : 1);
1290
1291         memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1292                ctx->authsize);
1293
1294         return ipsec_esp(edesc, req, 0, ipsec_esp_decrypt_swauth_done);
1295 }
1296
1297 static int aead_givencrypt(struct aead_givcrypt_request *req)
1298 {
1299         struct aead_request *areq = &req->areq;
1300         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1301         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1302         struct talitos_edesc *edesc;
1303
1304         /* allocate extended descriptor */
1305         edesc = aead_edesc_alloc(areq, req->giv, 0, true);
1306         if (IS_ERR(edesc))
1307                 return PTR_ERR(edesc);
1308
1309         /* set encrypt */
1310         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1311
1312         memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
1313         /* avoid consecutive packets going out with same IV */
1314         *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
1315
1316         return ipsec_esp(edesc, areq, req->seq, ipsec_esp_encrypt_done);
1317 }
1318
1319 static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
1320                              const u8 *key, unsigned int keylen)
1321 {
1322         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1323
1324         memcpy(&ctx->key, key, keylen);
1325         ctx->keylen = keylen;
1326
1327         return 0;
1328 }
1329
1330 static void common_nonsnoop_unmap(struct device *dev,
1331                                   struct talitos_edesc *edesc,
1332                                   struct ablkcipher_request *areq)
1333 {
1334         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1335         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
1336         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
1337
1338         talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
1339
1340         if (edesc->dma_len)
1341                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1342                                  DMA_BIDIRECTIONAL);
1343 }
1344
1345 static void ablkcipher_done(struct device *dev,
1346                             struct talitos_desc *desc, void *context,
1347                             int err)
1348 {
1349         struct ablkcipher_request *areq = context;
1350         struct talitos_edesc *edesc;
1351
1352         edesc = container_of(desc, struct talitos_edesc, desc);
1353
1354         common_nonsnoop_unmap(dev, edesc, areq);
1355
1356         kfree(edesc);
1357
1358         areq->base.complete(&areq->base, err);
1359 }
1360
1361 static int common_nonsnoop(struct talitos_edesc *edesc,
1362                            struct ablkcipher_request *areq,
1363                            void (*callback) (struct device *dev,
1364                                              struct talitos_desc *desc,
1365                                              void *context, int error))
1366 {
1367         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1368         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1369         struct device *dev = ctx->dev;
1370         struct talitos_desc *desc = &edesc->desc;
1371         unsigned int cryptlen = areq->nbytes;
1372         unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
1373         int sg_count, ret;
1374
1375         /* first DWORD empty */
1376         desc->ptr[0] = zero_entry;
1377
1378         /* cipher iv */
1379         to_talitos_ptr(&desc->ptr[1], edesc->iv_dma);
1380         desc->ptr[1].len = cpu_to_be16(ivsize);
1381         desc->ptr[1].j_extent = 0;
1382
1383         /* cipher key */
1384         map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1385                                (char *)&ctx->key, 0, DMA_TO_DEVICE);
1386
1387         /*
1388          * cipher in
1389          */
1390         desc->ptr[3].len = cpu_to_be16(cryptlen);
1391         desc->ptr[3].j_extent = 0;
1392
1393         sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1394                                   (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1395                                                            : DMA_TO_DEVICE,
1396                                   edesc->src_chained);
1397
1398         if (sg_count == 1) {
1399                 to_talitos_ptr(&desc->ptr[3], sg_dma_address(areq->src));
1400         } else {
1401                 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
1402                                           &edesc->link_tbl[0]);
1403                 if (sg_count > 1) {
1404                         to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1405                         desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1406                         dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1407                                                    edesc->dma_len,
1408                                                    DMA_BIDIRECTIONAL);
1409                 } else {
1410                         /* Only one segment now, so no link tbl needed */
1411                         to_talitos_ptr(&desc->ptr[3],
1412                                        sg_dma_address(areq->src));
1413                 }
1414         }
1415
1416         /* cipher out */
1417         desc->ptr[4].len = cpu_to_be16(cryptlen);
1418         desc->ptr[4].j_extent = 0;
1419
1420         if (areq->src != areq->dst)
1421                 sg_count = talitos_map_sg(dev, areq->dst,
1422                                           edesc->dst_nents ? : 1,
1423                                           DMA_FROM_DEVICE, edesc->dst_chained);
1424
1425         if (sg_count == 1) {
1426                 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->dst));
1427         } else {
1428                 struct talitos_ptr *link_tbl_ptr =
1429                         &edesc->link_tbl[edesc->src_nents + 1];
1430
1431                 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
1432                                               (edesc->src_nents + 1) *
1433                                               sizeof(struct talitos_ptr));
1434                 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1435                 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1436                                           link_tbl_ptr);
1437                 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1438                                            edesc->dma_len, DMA_BIDIRECTIONAL);
1439         }
1440
1441         /* iv out */
1442         map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0,
1443                                DMA_FROM_DEVICE);
1444
1445         /* last DWORD empty */
1446         desc->ptr[6] = zero_entry;
1447
1448         ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1449         if (ret != -EINPROGRESS) {
1450                 common_nonsnoop_unmap(dev, edesc, areq);
1451                 kfree(edesc);
1452         }
1453         return ret;
1454 }
1455
1456 static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1457                                                     areq, bool encrypt)
1458 {
1459         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1460         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1461         unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
1462
1463         return talitos_edesc_alloc(ctx->dev, NULL, areq->src, areq->dst,
1464                                    areq->info, 0, areq->nbytes, 0, ivsize, 0,
1465                                    areq->base.flags, encrypt);
1466 }
1467
1468 static int ablkcipher_encrypt(struct ablkcipher_request *areq)
1469 {
1470         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1471         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1472         struct talitos_edesc *edesc;
1473
1474         /* allocate extended descriptor */
1475         edesc = ablkcipher_edesc_alloc(areq, true);
1476         if (IS_ERR(edesc))
1477                 return PTR_ERR(edesc);
1478
1479         /* set encrypt */
1480         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1481
1482         return common_nonsnoop(edesc, areq, ablkcipher_done);
1483 }
1484
1485 static int ablkcipher_decrypt(struct ablkcipher_request *areq)
1486 {
1487         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1488         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1489         struct talitos_edesc *edesc;
1490
1491         /* allocate extended descriptor */
1492         edesc = ablkcipher_edesc_alloc(areq, false);
1493         if (IS_ERR(edesc))
1494                 return PTR_ERR(edesc);
1495
1496         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1497
1498         return common_nonsnoop(edesc, areq, ablkcipher_done);
1499 }
1500
1501 static void common_nonsnoop_hash_unmap(struct device *dev,
1502                                        struct talitos_edesc *edesc,
1503                                        struct ahash_request *areq)
1504 {
1505         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1506
1507         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1508
1509         /* When using hashctx-in, must unmap it. */
1510         if (edesc->desc.ptr[1].len)
1511                 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1],
1512                                          DMA_TO_DEVICE);
1513
1514         if (edesc->desc.ptr[2].len)
1515                 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2],
1516                                          DMA_TO_DEVICE);
1517
1518         talitos_sg_unmap(dev, edesc, req_ctx->psrc, NULL);
1519
1520         if (edesc->dma_len)
1521                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1522                                  DMA_BIDIRECTIONAL);
1523
1524 }
1525
1526 static void ahash_done(struct device *dev,
1527                        struct talitos_desc *desc, void *context,
1528                        int err)
1529 {
1530         struct ahash_request *areq = context;
1531         struct talitos_edesc *edesc =
1532                  container_of(desc, struct talitos_edesc, desc);
1533         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1534
1535         if (!req_ctx->last && req_ctx->to_hash_later) {
1536                 /* Position any partial block for next update/final/finup */
1537                 memcpy(req_ctx->buf, req_ctx->bufnext, req_ctx->to_hash_later);
1538                 req_ctx->nbuf = req_ctx->to_hash_later;
1539         }
1540         common_nonsnoop_hash_unmap(dev, edesc, areq);
1541
1542         kfree(edesc);
1543
1544         areq->base.complete(&areq->base, err);
1545 }
1546
1547 static int common_nonsnoop_hash(struct talitos_edesc *edesc,
1548                                 struct ahash_request *areq, unsigned int length,
1549                                 void (*callback) (struct device *dev,
1550                                                   struct talitos_desc *desc,
1551                                                   void *context, int error))
1552 {
1553         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1554         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1555         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1556         struct device *dev = ctx->dev;
1557         struct talitos_desc *desc = &edesc->desc;
1558         int sg_count, ret;
1559
1560         /* first DWORD empty */
1561         desc->ptr[0] = zero_entry;
1562
1563         /* hash context in */
1564         if (!req_ctx->first || req_ctx->swinit) {
1565                 map_single_talitos_ptr(dev, &desc->ptr[1],
1566                                        req_ctx->hw_context_size,
1567                                        (char *)req_ctx->hw_context, 0,
1568                                        DMA_TO_DEVICE);
1569                 req_ctx->swinit = 0;
1570         } else {
1571                 desc->ptr[1] = zero_entry;
1572                 /* Indicate next op is not the first. */
1573                 req_ctx->first = 0;
1574         }
1575
1576         /* HMAC key */
1577         if (ctx->keylen)
1578                 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1579                                        (char *)&ctx->key, 0, DMA_TO_DEVICE);
1580         else
1581                 desc->ptr[2] = zero_entry;
1582
1583         /*
1584          * data in
1585          */
1586         desc->ptr[3].len = cpu_to_be16(length);
1587         desc->ptr[3].j_extent = 0;
1588
1589         sg_count = talitos_map_sg(dev, req_ctx->psrc,
1590                                   edesc->src_nents ? : 1,
1591                                   DMA_TO_DEVICE, edesc->src_chained);
1592
1593         if (sg_count == 1) {
1594                 to_talitos_ptr(&desc->ptr[3], sg_dma_address(req_ctx->psrc));
1595         } else {
1596                 sg_count = sg_to_link_tbl(req_ctx->psrc, sg_count, length,
1597                                           &edesc->link_tbl[0]);
1598                 if (sg_count > 1) {
1599                         desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1600                         to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1601                         dma_sync_single_for_device(ctx->dev,
1602                                                    edesc->dma_link_tbl,
1603                                                    edesc->dma_len,
1604                                                    DMA_BIDIRECTIONAL);
1605                 } else {
1606                         /* Only one segment now, so no link tbl needed */
1607                         to_talitos_ptr(&desc->ptr[3],
1608                                        sg_dma_address(req_ctx->psrc));
1609                 }
1610         }
1611
1612         /* fifth DWORD empty */
1613         desc->ptr[4] = zero_entry;
1614
1615         /* hash/HMAC out -or- hash context out */
1616         if (req_ctx->last)
1617                 map_single_talitos_ptr(dev, &desc->ptr[5],
1618                                        crypto_ahash_digestsize(tfm),
1619                                        areq->result, 0, DMA_FROM_DEVICE);
1620         else
1621                 map_single_talitos_ptr(dev, &desc->ptr[5],
1622                                        req_ctx->hw_context_size,
1623                                        req_ctx->hw_context, 0, DMA_FROM_DEVICE);
1624
1625         /* last DWORD empty */
1626         desc->ptr[6] = zero_entry;
1627
1628         ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1629         if (ret != -EINPROGRESS) {
1630                 common_nonsnoop_hash_unmap(dev, edesc, areq);
1631                 kfree(edesc);
1632         }
1633         return ret;
1634 }
1635
1636 static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
1637                                                unsigned int nbytes)
1638 {
1639         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1640         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1641         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1642
1643         return talitos_edesc_alloc(ctx->dev, NULL, req_ctx->psrc, NULL, NULL, 0,
1644                                    nbytes, 0, 0, 0, areq->base.flags, false);
1645 }
1646
1647 static int ahash_init(struct ahash_request *areq)
1648 {
1649         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1650         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1651
1652         /* Initialize the context */
1653         req_ctx->nbuf = 0;
1654         req_ctx->first = 1; /* first indicates h/w must init its context */
1655         req_ctx->swinit = 0; /* assume h/w init of context */
1656         req_ctx->hw_context_size =
1657                 (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
1658                         ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
1659                         : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
1660
1661         return 0;
1662 }
1663
1664 /*
1665  * on h/w without explicit sha224 support, we initialize h/w context
1666  * manually with sha224 constants, and tell it to run sha256.
1667  */
1668 static int ahash_init_sha224_swinit(struct ahash_request *areq)
1669 {
1670         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1671
1672         ahash_init(areq);
1673         req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
1674
1675         req_ctx->hw_context[0] = SHA224_H0;
1676         req_ctx->hw_context[1] = SHA224_H1;
1677         req_ctx->hw_context[2] = SHA224_H2;
1678         req_ctx->hw_context[3] = SHA224_H3;
1679         req_ctx->hw_context[4] = SHA224_H4;
1680         req_ctx->hw_context[5] = SHA224_H5;
1681         req_ctx->hw_context[6] = SHA224_H6;
1682         req_ctx->hw_context[7] = SHA224_H7;
1683
1684         /* init 64-bit count */
1685         req_ctx->hw_context[8] = 0;
1686         req_ctx->hw_context[9] = 0;
1687
1688         return 0;
1689 }
1690
1691 static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
1692 {
1693         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1694         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1695         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1696         struct talitos_edesc *edesc;
1697         unsigned int blocksize =
1698                         crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1699         unsigned int nbytes_to_hash;
1700         unsigned int to_hash_later;
1701         unsigned int nsg;
1702         bool chained;
1703
1704         if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) {
1705                 /* Buffer up to one whole block */
1706                 sg_copy_to_buffer(areq->src,
1707                                   sg_count(areq->src, nbytes, &chained),
1708                                   req_ctx->buf + req_ctx->nbuf, nbytes);
1709                 req_ctx->nbuf += nbytes;
1710                 return 0;
1711         }
1712
1713         /* At least (blocksize + 1) bytes are available to hash */
1714         nbytes_to_hash = nbytes + req_ctx->nbuf;
1715         to_hash_later = nbytes_to_hash & (blocksize - 1);
1716
1717         if (req_ctx->last)
1718                 to_hash_later = 0;
1719         else if (to_hash_later)
1720                 /* There is a partial block. Hash the full block(s) now */
1721                 nbytes_to_hash -= to_hash_later;
1722         else {
1723                 /* Keep one block buffered */
1724                 nbytes_to_hash -= blocksize;
1725                 to_hash_later = blocksize;
1726         }
1727
1728         /* Chain in any previously buffered data */
1729         if (req_ctx->nbuf) {
1730                 nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
1731                 sg_init_table(req_ctx->bufsl, nsg);
1732                 sg_set_buf(req_ctx->bufsl, req_ctx->buf, req_ctx->nbuf);
1733                 if (nsg > 1)
1734                         scatterwalk_sg_chain(req_ctx->bufsl, 2, areq->src);
1735                 req_ctx->psrc = req_ctx->bufsl;
1736         } else
1737                 req_ctx->psrc = areq->src;
1738
1739         if (to_hash_later) {
1740                 int nents = sg_count(areq->src, nbytes, &chained);
1741                 sg_pcopy_to_buffer(areq->src, nents,
1742                                       req_ctx->bufnext,
1743                                       to_hash_later,
1744                                       nbytes - to_hash_later);
1745         }
1746         req_ctx->to_hash_later = to_hash_later;
1747
1748         /* Allocate extended descriptor */
1749         edesc = ahash_edesc_alloc(areq, nbytes_to_hash);
1750         if (IS_ERR(edesc))
1751                 return PTR_ERR(edesc);
1752
1753         edesc->desc.hdr = ctx->desc_hdr_template;
1754
1755         /* On last one, request SEC to pad; otherwise continue */
1756         if (req_ctx->last)
1757                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
1758         else
1759                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
1760
1761         /* request SEC to INIT hash. */
1762         if (req_ctx->first && !req_ctx->swinit)
1763                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
1764
1765         /* When the tfm context has a keylen, it's an HMAC.
1766          * A first or last (ie. not middle) descriptor must request HMAC.
1767          */
1768         if (ctx->keylen && (req_ctx->first || req_ctx->last))
1769                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
1770
1771         return common_nonsnoop_hash(edesc, areq, nbytes_to_hash,
1772                                     ahash_done);
1773 }
1774
1775 static int ahash_update(struct ahash_request *areq)
1776 {
1777         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1778
1779         req_ctx->last = 0;
1780
1781         return ahash_process_req(areq, areq->nbytes);
1782 }
1783
1784 static int ahash_final(struct ahash_request *areq)
1785 {
1786         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1787
1788         req_ctx->last = 1;
1789
1790         return ahash_process_req(areq, 0);
1791 }
1792
1793 static int ahash_finup(struct ahash_request *areq)
1794 {
1795         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1796
1797         req_ctx->last = 1;
1798
1799         return ahash_process_req(areq, areq->nbytes);
1800 }
1801
1802 static int ahash_digest(struct ahash_request *areq)
1803 {
1804         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1805         struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
1806
1807         ahash->init(areq);
1808         req_ctx->last = 1;
1809
1810         return ahash_process_req(areq, areq->nbytes);
1811 }
1812
1813 struct keyhash_result {
1814         struct completion completion;
1815         int err;
1816 };
1817
1818 static void keyhash_complete(struct crypto_async_request *req, int err)
1819 {
1820         struct keyhash_result *res = req->data;
1821
1822         if (err == -EINPROGRESS)
1823                 return;
1824
1825         res->err = err;
1826         complete(&res->completion);
1827 }
1828
1829 static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int keylen,
1830                    u8 *hash)
1831 {
1832         struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1833
1834         struct scatterlist sg[1];
1835         struct ahash_request *req;
1836         struct keyhash_result hresult;
1837         int ret;
1838
1839         init_completion(&hresult.completion);
1840
1841         req = ahash_request_alloc(tfm, GFP_KERNEL);
1842         if (!req)
1843                 return -ENOMEM;
1844
1845         /* Keep tfm keylen == 0 during hash of the long key */
1846         ctx->keylen = 0;
1847         ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1848                                    keyhash_complete, &hresult);
1849
1850         sg_init_one(&sg[0], key, keylen);
1851
1852         ahash_request_set_crypt(req, sg, hash, keylen);
1853         ret = crypto_ahash_digest(req);
1854         switch (ret) {
1855         case 0:
1856                 break;
1857         case -EINPROGRESS:
1858         case -EBUSY:
1859                 ret = wait_for_completion_interruptible(
1860                         &hresult.completion);
1861                 if (!ret)
1862                         ret = hresult.err;
1863                 break;
1864         default:
1865                 break;
1866         }
1867         ahash_request_free(req);
1868
1869         return ret;
1870 }
1871
1872 static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
1873                         unsigned int keylen)
1874 {
1875         struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1876         unsigned int blocksize =
1877                         crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1878         unsigned int digestsize = crypto_ahash_digestsize(tfm);
1879         unsigned int keysize = keylen;
1880         u8 hash[SHA512_DIGEST_SIZE];
1881         int ret;
1882
1883         if (keylen <= blocksize)
1884                 memcpy(ctx->key, key, keysize);
1885         else {
1886                 /* Must get the hash of the long key */
1887                 ret = keyhash(tfm, key, keylen, hash);
1888
1889                 if (ret) {
1890                         crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1891                         return -EINVAL;
1892                 }
1893
1894                 keysize = digestsize;
1895                 memcpy(ctx->key, hash, digestsize);
1896         }
1897
1898         ctx->keylen = keysize;
1899
1900         return 0;
1901 }
1902
1903
1904 struct talitos_alg_template {
1905         u32 type;
1906         union {
1907                 struct crypto_alg crypto;
1908                 struct ahash_alg hash;
1909         } alg;
1910         __be32 desc_hdr_template;
1911 };
1912
1913 static struct talitos_alg_template driver_algs[] = {
1914         /* AEAD algorithms.  These use a single-pass ipsec_esp descriptor */
1915         {       .type = CRYPTO_ALG_TYPE_AEAD,
1916                 .alg.crypto = {
1917                         .cra_name = "authenc(hmac(sha1),cbc(aes))",
1918                         .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1919                         .cra_blocksize = AES_BLOCK_SIZE,
1920                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1921                         .cra_aead = {
1922                                 .ivsize = AES_BLOCK_SIZE,
1923                                 .maxauthsize = SHA1_DIGEST_SIZE,
1924                         }
1925                 },
1926                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1927                                      DESC_HDR_SEL0_AESU |
1928                                      DESC_HDR_MODE0_AESU_CBC |
1929                                      DESC_HDR_SEL1_MDEUA |
1930                                      DESC_HDR_MODE1_MDEU_INIT |
1931                                      DESC_HDR_MODE1_MDEU_PAD |
1932                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1933         },
1934         {       .type = CRYPTO_ALG_TYPE_AEAD,
1935                 .alg.crypto = {
1936                         .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1937                         .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
1938                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1939                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1940                         .cra_aead = {
1941                                 .ivsize = DES3_EDE_BLOCK_SIZE,
1942                                 .maxauthsize = SHA1_DIGEST_SIZE,
1943                         }
1944                 },
1945                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1946                                      DESC_HDR_SEL0_DEU |
1947                                      DESC_HDR_MODE0_DEU_CBC |
1948                                      DESC_HDR_MODE0_DEU_3DES |
1949                                      DESC_HDR_SEL1_MDEUA |
1950                                      DESC_HDR_MODE1_MDEU_INIT |
1951                                      DESC_HDR_MODE1_MDEU_PAD |
1952                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1953         },
1954         {       .type = CRYPTO_ALG_TYPE_AEAD,
1955                 .alg.crypto = {
1956                         .cra_name = "authenc(hmac(sha224),cbc(aes))",
1957                         .cra_driver_name = "authenc-hmac-sha224-cbc-aes-talitos",
1958                         .cra_blocksize = AES_BLOCK_SIZE,
1959                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1960                         .cra_aead = {
1961                                 .ivsize = AES_BLOCK_SIZE,
1962                                 .maxauthsize = SHA224_DIGEST_SIZE,
1963                         }
1964                 },
1965                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1966                                      DESC_HDR_SEL0_AESU |
1967                                      DESC_HDR_MODE0_AESU_CBC |
1968                                      DESC_HDR_SEL1_MDEUA |
1969                                      DESC_HDR_MODE1_MDEU_INIT |
1970                                      DESC_HDR_MODE1_MDEU_PAD |
1971                                      DESC_HDR_MODE1_MDEU_SHA224_HMAC,
1972         },
1973         {       .type = CRYPTO_ALG_TYPE_AEAD,
1974                 .alg.crypto = {
1975                         .cra_name = "authenc(hmac(sha224),cbc(des3_ede))",
1976                         .cra_driver_name = "authenc-hmac-sha224-cbc-3des-talitos",
1977                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1978                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1979                         .cra_aead = {
1980                                 .ivsize = DES3_EDE_BLOCK_SIZE,
1981                                 .maxauthsize = SHA224_DIGEST_SIZE,
1982                         }
1983                 },
1984                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1985                                      DESC_HDR_SEL0_DEU |
1986                                      DESC_HDR_MODE0_DEU_CBC |
1987                                      DESC_HDR_MODE0_DEU_3DES |
1988                                      DESC_HDR_SEL1_MDEUA |
1989                                      DESC_HDR_MODE1_MDEU_INIT |
1990                                      DESC_HDR_MODE1_MDEU_PAD |
1991                                      DESC_HDR_MODE1_MDEU_SHA224_HMAC,
1992         },
1993         {       .type = CRYPTO_ALG_TYPE_AEAD,
1994                 .alg.crypto = {
1995                         .cra_name = "authenc(hmac(sha256),cbc(aes))",
1996                         .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
1997                         .cra_blocksize = AES_BLOCK_SIZE,
1998                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1999                         .cra_aead = {
2000                                 .ivsize = AES_BLOCK_SIZE,
2001                                 .maxauthsize = SHA256_DIGEST_SIZE,
2002                         }
2003                 },
2004                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2005                                      DESC_HDR_SEL0_AESU |
2006                                      DESC_HDR_MODE0_AESU_CBC |
2007                                      DESC_HDR_SEL1_MDEUA |
2008                                      DESC_HDR_MODE1_MDEU_INIT |
2009                                      DESC_HDR_MODE1_MDEU_PAD |
2010                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2011         },
2012         {       .type = CRYPTO_ALG_TYPE_AEAD,
2013                 .alg.crypto = {
2014                         .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
2015                         .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
2016                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2017                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2018                         .cra_aead = {
2019                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2020                                 .maxauthsize = SHA256_DIGEST_SIZE,
2021                         }
2022                 },
2023                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2024                                      DESC_HDR_SEL0_DEU |
2025                                      DESC_HDR_MODE0_DEU_CBC |
2026                                      DESC_HDR_MODE0_DEU_3DES |
2027                                      DESC_HDR_SEL1_MDEUA |
2028                                      DESC_HDR_MODE1_MDEU_INIT |
2029                                      DESC_HDR_MODE1_MDEU_PAD |
2030                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2031         },
2032         {       .type = CRYPTO_ALG_TYPE_AEAD,
2033                 .alg.crypto = {
2034                         .cra_name = "authenc(hmac(sha384),cbc(aes))",
2035                         .cra_driver_name = "authenc-hmac-sha384-cbc-aes-talitos",
2036                         .cra_blocksize = AES_BLOCK_SIZE,
2037                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2038                         .cra_aead = {
2039                                 .ivsize = AES_BLOCK_SIZE,
2040                                 .maxauthsize = SHA384_DIGEST_SIZE,
2041                         }
2042                 },
2043                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2044                                      DESC_HDR_SEL0_AESU |
2045                                      DESC_HDR_MODE0_AESU_CBC |
2046                                      DESC_HDR_SEL1_MDEUB |
2047                                      DESC_HDR_MODE1_MDEU_INIT |
2048                                      DESC_HDR_MODE1_MDEU_PAD |
2049                                      DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2050         },
2051         {       .type = CRYPTO_ALG_TYPE_AEAD,
2052                 .alg.crypto = {
2053                         .cra_name = "authenc(hmac(sha384),cbc(des3_ede))",
2054                         .cra_driver_name = "authenc-hmac-sha384-cbc-3des-talitos",
2055                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2056                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2057                         .cra_aead = {
2058                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2059                                 .maxauthsize = SHA384_DIGEST_SIZE,
2060                         }
2061                 },
2062                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2063                                      DESC_HDR_SEL0_DEU |
2064                                      DESC_HDR_MODE0_DEU_CBC |
2065                                      DESC_HDR_MODE0_DEU_3DES |
2066                                      DESC_HDR_SEL1_MDEUB |
2067                                      DESC_HDR_MODE1_MDEU_INIT |
2068                                      DESC_HDR_MODE1_MDEU_PAD |
2069                                      DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2070         },
2071         {       .type = CRYPTO_ALG_TYPE_AEAD,
2072                 .alg.crypto = {
2073                         .cra_name = "authenc(hmac(sha512),cbc(aes))",
2074                         .cra_driver_name = "authenc-hmac-sha512-cbc-aes-talitos",
2075                         .cra_blocksize = AES_BLOCK_SIZE,
2076                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2077                         .cra_aead = {
2078                                 .ivsize = AES_BLOCK_SIZE,
2079                                 .maxauthsize = SHA512_DIGEST_SIZE,
2080                         }
2081                 },
2082                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2083                                      DESC_HDR_SEL0_AESU |
2084                                      DESC_HDR_MODE0_AESU_CBC |
2085                                      DESC_HDR_SEL1_MDEUB |
2086                                      DESC_HDR_MODE1_MDEU_INIT |
2087                                      DESC_HDR_MODE1_MDEU_PAD |
2088                                      DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2089         },
2090         {       .type = CRYPTO_ALG_TYPE_AEAD,
2091                 .alg.crypto = {
2092                         .cra_name = "authenc(hmac(sha512),cbc(des3_ede))",
2093                         .cra_driver_name = "authenc-hmac-sha512-cbc-3des-talitos",
2094                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2095                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2096                         .cra_aead = {
2097                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2098                                 .maxauthsize = SHA512_DIGEST_SIZE,
2099                         }
2100                 },
2101                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2102                                      DESC_HDR_SEL0_DEU |
2103                                      DESC_HDR_MODE0_DEU_CBC |
2104                                      DESC_HDR_MODE0_DEU_3DES |
2105                                      DESC_HDR_SEL1_MDEUB |
2106                                      DESC_HDR_MODE1_MDEU_INIT |
2107                                      DESC_HDR_MODE1_MDEU_PAD |
2108                                      DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2109         },
2110         {       .type = CRYPTO_ALG_TYPE_AEAD,
2111                 .alg.crypto = {
2112                         .cra_name = "authenc(hmac(md5),cbc(aes))",
2113                         .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
2114                         .cra_blocksize = AES_BLOCK_SIZE,
2115                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2116                         .cra_aead = {
2117                                 .ivsize = AES_BLOCK_SIZE,
2118                                 .maxauthsize = MD5_DIGEST_SIZE,
2119                         }
2120                 },
2121                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2122                                      DESC_HDR_SEL0_AESU |
2123                                      DESC_HDR_MODE0_AESU_CBC |
2124                                      DESC_HDR_SEL1_MDEUA |
2125                                      DESC_HDR_MODE1_MDEU_INIT |
2126                                      DESC_HDR_MODE1_MDEU_PAD |
2127                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
2128         },
2129         {       .type = CRYPTO_ALG_TYPE_AEAD,
2130                 .alg.crypto = {
2131                         .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
2132                         .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos",
2133                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2134                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2135                         .cra_aead = {
2136                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2137                                 .maxauthsize = MD5_DIGEST_SIZE,
2138                         }
2139                 },
2140                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2141                                      DESC_HDR_SEL0_DEU |
2142                                      DESC_HDR_MODE0_DEU_CBC |
2143                                      DESC_HDR_MODE0_DEU_3DES |
2144                                      DESC_HDR_SEL1_MDEUA |
2145                                      DESC_HDR_MODE1_MDEU_INIT |
2146                                      DESC_HDR_MODE1_MDEU_PAD |
2147                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
2148         },
2149         /* ABLKCIPHER algorithms. */
2150         {       .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2151                 .alg.crypto = {
2152                         .cra_name = "cbc(aes)",
2153                         .cra_driver_name = "cbc-aes-talitos",
2154                         .cra_blocksize = AES_BLOCK_SIZE,
2155                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2156                                      CRYPTO_ALG_ASYNC,
2157                         .cra_ablkcipher = {
2158                                 .min_keysize = AES_MIN_KEY_SIZE,
2159                                 .max_keysize = AES_MAX_KEY_SIZE,
2160                                 .ivsize = AES_BLOCK_SIZE,
2161                         }
2162                 },
2163                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2164                                      DESC_HDR_SEL0_AESU |
2165                                      DESC_HDR_MODE0_AESU_CBC,
2166         },
2167         {       .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2168                 .alg.crypto = {
2169                         .cra_name = "cbc(des3_ede)",
2170                         .cra_driver_name = "cbc-3des-talitos",
2171                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2172                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2173                                      CRYPTO_ALG_ASYNC,
2174                         .cra_ablkcipher = {
2175                                 .min_keysize = DES3_EDE_KEY_SIZE,
2176                                 .max_keysize = DES3_EDE_KEY_SIZE,
2177                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2178                         }
2179                 },
2180                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2181                                      DESC_HDR_SEL0_DEU |
2182                                      DESC_HDR_MODE0_DEU_CBC |
2183                                      DESC_HDR_MODE0_DEU_3DES,
2184         },
2185         /* AHASH algorithms. */
2186         {       .type = CRYPTO_ALG_TYPE_AHASH,
2187                 .alg.hash = {
2188                         .halg.digestsize = MD5_DIGEST_SIZE,
2189                         .halg.base = {
2190                                 .cra_name = "md5",
2191                                 .cra_driver_name = "md5-talitos",
2192                                 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
2193                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2194                                              CRYPTO_ALG_ASYNC,
2195                         }
2196                 },
2197                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2198                                      DESC_HDR_SEL0_MDEUA |
2199                                      DESC_HDR_MODE0_MDEU_MD5,
2200         },
2201         {       .type = CRYPTO_ALG_TYPE_AHASH,
2202                 .alg.hash = {
2203                         .halg.digestsize = SHA1_DIGEST_SIZE,
2204                         .halg.base = {
2205                                 .cra_name = "sha1",
2206                                 .cra_driver_name = "sha1-talitos",
2207                                 .cra_blocksize = SHA1_BLOCK_SIZE,
2208                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2209                                              CRYPTO_ALG_ASYNC,
2210                         }
2211                 },
2212                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2213                                      DESC_HDR_SEL0_MDEUA |
2214                                      DESC_HDR_MODE0_MDEU_SHA1,
2215         },
2216         {       .type = CRYPTO_ALG_TYPE_AHASH,
2217                 .alg.hash = {
2218                         .halg.digestsize = SHA224_DIGEST_SIZE,
2219                         .halg.base = {
2220                                 .cra_name = "sha224",
2221                                 .cra_driver_name = "sha224-talitos",
2222                                 .cra_blocksize = SHA224_BLOCK_SIZE,
2223                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2224                                              CRYPTO_ALG_ASYNC,
2225                         }
2226                 },
2227                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2228                                      DESC_HDR_SEL0_MDEUA |
2229                                      DESC_HDR_MODE0_MDEU_SHA224,
2230         },
2231         {       .type = CRYPTO_ALG_TYPE_AHASH,
2232                 .alg.hash = {
2233                         .halg.digestsize = SHA256_DIGEST_SIZE,
2234                         .halg.base = {
2235                                 .cra_name = "sha256",
2236                                 .cra_driver_name = "sha256-talitos",
2237                                 .cra_blocksize = SHA256_BLOCK_SIZE,
2238                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2239                                              CRYPTO_ALG_ASYNC,
2240                         }
2241                 },
2242                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2243                                      DESC_HDR_SEL0_MDEUA |
2244                                      DESC_HDR_MODE0_MDEU_SHA256,
2245         },
2246         {       .type = CRYPTO_ALG_TYPE_AHASH,
2247                 .alg.hash = {
2248                         .halg.digestsize = SHA384_DIGEST_SIZE,
2249                         .halg.base = {
2250                                 .cra_name = "sha384",
2251                                 .cra_driver_name = "sha384-talitos",
2252                                 .cra_blocksize = SHA384_BLOCK_SIZE,
2253                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2254                                              CRYPTO_ALG_ASYNC,
2255                         }
2256                 },
2257                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2258                                      DESC_HDR_SEL0_MDEUB |
2259                                      DESC_HDR_MODE0_MDEUB_SHA384,
2260         },
2261         {       .type = CRYPTO_ALG_TYPE_AHASH,
2262                 .alg.hash = {
2263                         .halg.digestsize = SHA512_DIGEST_SIZE,
2264                         .halg.base = {
2265                                 .cra_name = "sha512",
2266                                 .cra_driver_name = "sha512-talitos",
2267                                 .cra_blocksize = SHA512_BLOCK_SIZE,
2268                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2269                                              CRYPTO_ALG_ASYNC,
2270                         }
2271                 },
2272                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2273                                      DESC_HDR_SEL0_MDEUB |
2274                                      DESC_HDR_MODE0_MDEUB_SHA512,
2275         },
2276         {       .type = CRYPTO_ALG_TYPE_AHASH,
2277                 .alg.hash = {
2278                         .halg.digestsize = MD5_DIGEST_SIZE,
2279                         .halg.base = {
2280                                 .cra_name = "hmac(md5)",
2281                                 .cra_driver_name = "hmac-md5-talitos",
2282                                 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
2283                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2284                                              CRYPTO_ALG_ASYNC,
2285                         }
2286                 },
2287                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2288                                      DESC_HDR_SEL0_MDEUA |
2289                                      DESC_HDR_MODE0_MDEU_MD5,
2290         },
2291         {       .type = CRYPTO_ALG_TYPE_AHASH,
2292                 .alg.hash = {
2293                         .halg.digestsize = SHA1_DIGEST_SIZE,
2294                         .halg.base = {
2295                                 .cra_name = "hmac(sha1)",
2296                                 .cra_driver_name = "hmac-sha1-talitos",
2297                                 .cra_blocksize = SHA1_BLOCK_SIZE,
2298                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2299                                              CRYPTO_ALG_ASYNC,
2300                         }
2301                 },
2302                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2303                                      DESC_HDR_SEL0_MDEUA |
2304                                      DESC_HDR_MODE0_MDEU_SHA1,
2305         },
2306         {       .type = CRYPTO_ALG_TYPE_AHASH,
2307                 .alg.hash = {
2308                         .halg.digestsize = SHA224_DIGEST_SIZE,
2309                         .halg.base = {
2310                                 .cra_name = "hmac(sha224)",
2311                                 .cra_driver_name = "hmac-sha224-talitos",
2312                                 .cra_blocksize = SHA224_BLOCK_SIZE,
2313                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2314                                              CRYPTO_ALG_ASYNC,
2315                         }
2316                 },
2317                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2318                                      DESC_HDR_SEL0_MDEUA |
2319                                      DESC_HDR_MODE0_MDEU_SHA224,
2320         },
2321         {       .type = CRYPTO_ALG_TYPE_AHASH,
2322                 .alg.hash = {
2323                         .halg.digestsize = SHA256_DIGEST_SIZE,
2324                         .halg.base = {
2325                                 .cra_name = "hmac(sha256)",
2326                                 .cra_driver_name = "hmac-sha256-talitos",
2327                                 .cra_blocksize = SHA256_BLOCK_SIZE,
2328                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2329                                              CRYPTO_ALG_ASYNC,
2330                         }
2331                 },
2332                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2333                                      DESC_HDR_SEL0_MDEUA |
2334                                      DESC_HDR_MODE0_MDEU_SHA256,
2335         },
2336         {       .type = CRYPTO_ALG_TYPE_AHASH,
2337                 .alg.hash = {
2338                         .halg.digestsize = SHA384_DIGEST_SIZE,
2339                         .halg.base = {
2340                                 .cra_name = "hmac(sha384)",
2341                                 .cra_driver_name = "hmac-sha384-talitos",
2342                                 .cra_blocksize = SHA384_BLOCK_SIZE,
2343                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2344                                              CRYPTO_ALG_ASYNC,
2345                         }
2346                 },
2347                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2348                                      DESC_HDR_SEL0_MDEUB |
2349                                      DESC_HDR_MODE0_MDEUB_SHA384,
2350         },
2351         {       .type = CRYPTO_ALG_TYPE_AHASH,
2352                 .alg.hash = {
2353                         .halg.digestsize = SHA512_DIGEST_SIZE,
2354                         .halg.base = {
2355                                 .cra_name = "hmac(sha512)",
2356                                 .cra_driver_name = "hmac-sha512-talitos",
2357                                 .cra_blocksize = SHA512_BLOCK_SIZE,
2358                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2359                                              CRYPTO_ALG_ASYNC,
2360                         }
2361                 },
2362                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2363                                      DESC_HDR_SEL0_MDEUB |
2364                                      DESC_HDR_MODE0_MDEUB_SHA512,
2365         }
2366 };
2367
2368 struct talitos_crypto_alg {
2369         struct list_head entry;
2370         struct device *dev;
2371         struct talitos_alg_template algt;
2372 };
2373
2374 static int talitos_cra_init(struct crypto_tfm *tfm)
2375 {
2376         struct crypto_alg *alg = tfm->__crt_alg;
2377         struct talitos_crypto_alg *talitos_alg;
2378         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2379         struct talitos_private *priv;
2380
2381         if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
2382                 talitos_alg = container_of(__crypto_ahash_alg(alg),
2383                                            struct talitos_crypto_alg,
2384                                            algt.alg.hash);
2385         else
2386                 talitos_alg = container_of(alg, struct talitos_crypto_alg,
2387                                            algt.alg.crypto);
2388
2389         /* update context with ptr to dev */
2390         ctx->dev = talitos_alg->dev;
2391
2392         /* assign SEC channel to tfm in round-robin fashion */
2393         priv = dev_get_drvdata(ctx->dev);
2394         ctx->ch = atomic_inc_return(&priv->last_chan) &
2395                   (priv->num_channels - 1);
2396
2397         /* copy descriptor header template value */
2398         ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
2399
2400         /* select done notification */
2401         ctx->desc_hdr_template |= DESC_HDR_DONE_NOTIFY;
2402
2403         return 0;
2404 }
2405
2406 static int talitos_cra_init_aead(struct crypto_tfm *tfm)
2407 {
2408         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2409
2410         talitos_cra_init(tfm);
2411
2412         /* random first IV */
2413         get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
2414
2415         return 0;
2416 }
2417
2418 static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
2419 {
2420         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2421
2422         talitos_cra_init(tfm);
2423
2424         ctx->keylen = 0;
2425         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
2426                                  sizeof(struct talitos_ahash_req_ctx));
2427
2428         return 0;
2429 }
2430
2431 /*
2432  * given the alg's descriptor header template, determine whether descriptor
2433  * type and primary/secondary execution units required match the hw
2434  * capabilities description provided in the device tree node.
2435  */
2436 static int hw_supports(struct device *dev, __be32 desc_hdr_template)
2437 {
2438         struct talitos_private *priv = dev_get_drvdata(dev);
2439         int ret;
2440
2441         ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
2442               (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
2443
2444         if (SECONDARY_EU(desc_hdr_template))
2445                 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
2446                               & priv->exec_units);
2447
2448         return ret;
2449 }
2450
2451 static int talitos_remove(struct platform_device *ofdev)
2452 {
2453         struct device *dev = &ofdev->dev;
2454         struct talitos_private *priv = dev_get_drvdata(dev);
2455         struct talitos_crypto_alg *t_alg, *n;
2456         int i;
2457
2458         list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
2459                 switch (t_alg->algt.type) {
2460                 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2461                 case CRYPTO_ALG_TYPE_AEAD:
2462                         crypto_unregister_alg(&t_alg->algt.alg.crypto);
2463                         break;
2464                 case CRYPTO_ALG_TYPE_AHASH:
2465                         crypto_unregister_ahash(&t_alg->algt.alg.hash);
2466                         break;
2467                 }
2468                 list_del(&t_alg->entry);
2469                 kfree(t_alg);
2470         }
2471
2472         if (hw_supports(dev, DESC_HDR_SEL0_RNG))
2473                 talitos_unregister_rng(dev);
2474
2475         for (i = 0; i < priv->num_channels; i++)
2476                 kfree(priv->chan[i].fifo);
2477
2478         kfree(priv->chan);
2479
2480         for (i = 0; i < 2; i++)
2481                 if (priv->irq[i]) {
2482                         free_irq(priv->irq[i], dev);
2483                         irq_dispose_mapping(priv->irq[i]);
2484                 }
2485
2486         tasklet_kill(&priv->done_task[0]);
2487         if (priv->irq[1])
2488                 tasklet_kill(&priv->done_task[1]);
2489
2490         iounmap(priv->reg);
2491
2492         kfree(priv);
2493
2494         return 0;
2495 }
2496
2497 static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
2498                                                     struct talitos_alg_template
2499                                                            *template)
2500 {
2501         struct talitos_private *priv = dev_get_drvdata(dev);
2502         struct talitos_crypto_alg *t_alg;
2503         struct crypto_alg *alg;
2504
2505         t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
2506         if (!t_alg)
2507                 return ERR_PTR(-ENOMEM);
2508
2509         t_alg->algt = *template;
2510
2511         switch (t_alg->algt.type) {
2512         case CRYPTO_ALG_TYPE_ABLKCIPHER:
2513                 alg = &t_alg->algt.alg.crypto;
2514                 alg->cra_init = talitos_cra_init;
2515                 alg->cra_type = &crypto_ablkcipher_type;
2516                 alg->cra_ablkcipher.setkey = ablkcipher_setkey;
2517                 alg->cra_ablkcipher.encrypt = ablkcipher_encrypt;
2518                 alg->cra_ablkcipher.decrypt = ablkcipher_decrypt;
2519                 alg->cra_ablkcipher.geniv = "eseqiv";
2520                 break;
2521         case CRYPTO_ALG_TYPE_AEAD:
2522                 alg = &t_alg->algt.alg.crypto;
2523                 alg->cra_init = talitos_cra_init_aead;
2524                 alg->cra_type = &crypto_aead_type;
2525                 alg->cra_aead.setkey = aead_setkey;
2526                 alg->cra_aead.setauthsize = aead_setauthsize;
2527                 alg->cra_aead.encrypt = aead_encrypt;
2528                 alg->cra_aead.decrypt = aead_decrypt;
2529                 alg->cra_aead.givencrypt = aead_givencrypt;
2530                 alg->cra_aead.geniv = "<built-in>";
2531                 break;
2532         case CRYPTO_ALG_TYPE_AHASH:
2533                 alg = &t_alg->algt.alg.hash.halg.base;
2534                 alg->cra_init = talitos_cra_init_ahash;
2535                 alg->cra_type = &crypto_ahash_type;
2536                 t_alg->algt.alg.hash.init = ahash_init;
2537                 t_alg->algt.alg.hash.update = ahash_update;
2538                 t_alg->algt.alg.hash.final = ahash_final;
2539                 t_alg->algt.alg.hash.finup = ahash_finup;
2540                 t_alg->algt.alg.hash.digest = ahash_digest;
2541                 t_alg->algt.alg.hash.setkey = ahash_setkey;
2542
2543                 if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
2544                     !strncmp(alg->cra_name, "hmac", 4)) {
2545                         kfree(t_alg);
2546                         return ERR_PTR(-ENOTSUPP);
2547                 }
2548                 if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
2549                     (!strcmp(alg->cra_name, "sha224") ||
2550                      !strcmp(alg->cra_name, "hmac(sha224)"))) {
2551                         t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
2552                         t_alg->algt.desc_hdr_template =
2553                                         DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2554                                         DESC_HDR_SEL0_MDEUA |
2555                                         DESC_HDR_MODE0_MDEU_SHA256;
2556                 }
2557                 break;
2558         default:
2559                 dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
2560                 return ERR_PTR(-EINVAL);
2561         }
2562
2563         alg->cra_module = THIS_MODULE;
2564         alg->cra_priority = TALITOS_CRA_PRIORITY;
2565         alg->cra_alignmask = 0;
2566         alg->cra_ctxsize = sizeof(struct talitos_ctx);
2567         alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
2568
2569         t_alg->dev = dev;
2570
2571         return t_alg;
2572 }
2573
2574 static int talitos_probe_irq(struct platform_device *ofdev)
2575 {
2576         struct device *dev = &ofdev->dev;
2577         struct device_node *np = ofdev->dev.of_node;
2578         struct talitos_private *priv = dev_get_drvdata(dev);
2579         int err;
2580
2581         priv->irq[0] = irq_of_parse_and_map(np, 0);
2582         if (!priv->irq[0]) {
2583                 dev_err(dev, "failed to map irq\n");
2584                 return -EINVAL;
2585         }
2586
2587         priv->irq[1] = irq_of_parse_and_map(np, 1);
2588
2589         /* get the primary irq line */
2590         if (!priv->irq[1]) {
2591                 err = request_irq(priv->irq[0], talitos_interrupt_4ch, 0,
2592                                   dev_driver_string(dev), dev);
2593                 goto primary_out;
2594         }
2595
2596         err = request_irq(priv->irq[0], talitos_interrupt_ch0_2, 0,
2597                           dev_driver_string(dev), dev);
2598         if (err)
2599                 goto primary_out;
2600
2601         /* get the secondary irq line */
2602         err = request_irq(priv->irq[1], talitos_interrupt_ch1_3, 0,
2603                           dev_driver_string(dev), dev);
2604         if (err) {
2605                 dev_err(dev, "failed to request secondary irq\n");
2606                 irq_dispose_mapping(priv->irq[1]);
2607                 priv->irq[1] = 0;
2608         }
2609
2610         return err;
2611
2612 primary_out:
2613         if (err) {
2614                 dev_err(dev, "failed to request primary irq\n");
2615                 irq_dispose_mapping(priv->irq[0]);
2616                 priv->irq[0] = 0;
2617         }
2618
2619         return err;
2620 }
2621
2622 static int talitos_probe(struct platform_device *ofdev)
2623 {
2624         struct device *dev = &ofdev->dev;
2625         struct device_node *np = ofdev->dev.of_node;
2626         struct talitos_private *priv;
2627         const unsigned int *prop;
2628         int i, err;
2629
2630         priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
2631         if (!priv)
2632                 return -ENOMEM;
2633
2634         INIT_LIST_HEAD(&priv->alg_list);
2635
2636         dev_set_drvdata(dev, priv);
2637
2638         priv->ofdev = ofdev;
2639
2640         spin_lock_init(&priv->reg_lock);
2641
2642         err = talitos_probe_irq(ofdev);
2643         if (err)
2644                 goto err_out;
2645
2646         if (!priv->irq[1]) {
2647                 tasklet_init(&priv->done_task[0], talitos_done_4ch,
2648                              (unsigned long)dev);
2649         } else {
2650                 tasklet_init(&priv->done_task[0], talitos_done_ch0_2,
2651                              (unsigned long)dev);
2652                 tasklet_init(&priv->done_task[1], talitos_done_ch1_3,
2653                              (unsigned long)dev);
2654         }
2655
2656         priv->reg = of_iomap(np, 0);
2657         if (!priv->reg) {
2658                 dev_err(dev, "failed to of_iomap\n");
2659                 err = -ENOMEM;
2660                 goto err_out;
2661         }
2662
2663         /* get SEC version capabilities from device tree */
2664         prop = of_get_property(np, "fsl,num-channels", NULL);
2665         if (prop)
2666                 priv->num_channels = *prop;
2667
2668         prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
2669         if (prop)
2670                 priv->chfifo_len = *prop;
2671
2672         prop = of_get_property(np, "fsl,exec-units-mask", NULL);
2673         if (prop)
2674                 priv->exec_units = *prop;
2675
2676         prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
2677         if (prop)
2678                 priv->desc_types = *prop;
2679
2680         if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
2681             !priv->exec_units || !priv->desc_types) {
2682                 dev_err(dev, "invalid property data in device tree node\n");
2683                 err = -EINVAL;
2684                 goto err_out;
2685         }
2686
2687         if (of_device_is_compatible(np, "fsl,sec3.0"))
2688                 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
2689
2690         if (of_device_is_compatible(np, "fsl,sec2.1"))
2691                 priv->features |= TALITOS_FTR_HW_AUTH_CHECK |
2692                                   TALITOS_FTR_SHA224_HWINIT |
2693                                   TALITOS_FTR_HMAC_OK;
2694
2695         priv->chan = kzalloc(sizeof(struct talitos_channel) *
2696                              priv->num_channels, GFP_KERNEL);
2697         if (!priv->chan) {
2698                 dev_err(dev, "failed to allocate channel management space\n");
2699                 err = -ENOMEM;
2700                 goto err_out;
2701         }
2702
2703         priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
2704
2705         for (i = 0; i < priv->num_channels; i++) {
2706                 priv->chan[i].reg = priv->reg + TALITOS_CH_STRIDE * (i + 1);
2707                 if (!priv->irq[1] || !(i & 1))
2708                         priv->chan[i].reg += TALITOS_CH_BASE_OFFSET;
2709
2710                 spin_lock_init(&priv->chan[i].head_lock);
2711                 spin_lock_init(&priv->chan[i].tail_lock);
2712
2713                 priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) *
2714                                              priv->fifo_len, GFP_KERNEL);
2715                 if (!priv->chan[i].fifo) {
2716                         dev_err(dev, "failed to allocate request fifo %d\n", i);
2717                         err = -ENOMEM;
2718                         goto err_out;
2719                 }
2720
2721                 atomic_set(&priv->chan[i].submit_count,
2722                            -(priv->chfifo_len - 1));
2723         }
2724
2725         dma_set_mask(dev, DMA_BIT_MASK(36));
2726
2727         /* reset and initialize the h/w */
2728         err = init_device(dev);
2729         if (err) {
2730                 dev_err(dev, "failed to initialize device\n");
2731                 goto err_out;
2732         }
2733
2734         /* register the RNG, if available */
2735         if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
2736                 err = talitos_register_rng(dev);
2737                 if (err) {
2738                         dev_err(dev, "failed to register hwrng: %d\n", err);
2739                         goto err_out;
2740                 } else
2741                         dev_info(dev, "hwrng\n");
2742         }
2743
2744         /* register crypto algorithms the device supports */
2745         for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
2746                 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
2747                         struct talitos_crypto_alg *t_alg;
2748                         char *name = NULL;
2749
2750                         t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
2751                         if (IS_ERR(t_alg)) {
2752                                 err = PTR_ERR(t_alg);
2753                                 if (err == -ENOTSUPP)
2754                                         continue;
2755                                 goto err_out;
2756                         }
2757
2758                         switch (t_alg->algt.type) {
2759                         case CRYPTO_ALG_TYPE_ABLKCIPHER:
2760                         case CRYPTO_ALG_TYPE_AEAD:
2761                                 err = crypto_register_alg(
2762                                                 &t_alg->algt.alg.crypto);
2763                                 name = t_alg->algt.alg.crypto.cra_driver_name;
2764                                 break;
2765                         case CRYPTO_ALG_TYPE_AHASH:
2766                                 err = crypto_register_ahash(
2767                                                 &t_alg->algt.alg.hash);
2768                                 name =
2769                                  t_alg->algt.alg.hash.halg.base.cra_driver_name;
2770                                 break;
2771                         }
2772                         if (err) {
2773                                 dev_err(dev, "%s alg registration failed\n",
2774                                         name);
2775                                 kfree(t_alg);
2776                         } else
2777                                 list_add_tail(&t_alg->entry, &priv->alg_list);
2778                 }
2779         }
2780         if (!list_empty(&priv->alg_list))
2781                 dev_info(dev, "%s algorithms registered in /proc/crypto\n",
2782                          (char *)of_get_property(np, "compatible", NULL));
2783
2784         return 0;
2785
2786 err_out:
2787         talitos_remove(ofdev);
2788
2789         return err;
2790 }
2791
2792 static const struct of_device_id talitos_match[] = {
2793         {
2794                 .compatible = "fsl,sec2.0",
2795         },
2796         {},
2797 };
2798 MODULE_DEVICE_TABLE(of, talitos_match);
2799
2800 static struct platform_driver talitos_driver = {
2801         .driver = {
2802                 .name = "talitos",
2803                 .of_match_table = talitos_match,
2804         },
2805         .probe = talitos_probe,
2806         .remove = talitos_remove,
2807 };
2808
2809 module_platform_driver(talitos_driver);
2810
2811 MODULE_LICENSE("GPL");
2812 MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
2813 MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");