drivers/dbg/wrapcall.S

   1 #include <linux/linkage.h>
   2 #include <asm/memory.h>
   3 #include <asm/glue.h>
   4 #include <asm/vfpmacros.h>
   5 #include <asm/thread_notify.h>
   6 #include <asm/ptrace.h>
   7 #include <asm/assembler.h>
   8 #include <asm/asm-offsets.h>
   9 #include <mach/rk29_iomap.h>
  10
  11 #__scu_call_wrap:
  12 #
  13 # call to the defined funcion.
  14 # r0: func argument array , max = 6
  15 # r1: argument num.
  16 # r2: the function number.
  17
  18 #;      EXPORT __scu_call_wrap
  19 #;
  20 #;      CODE32
  21 #;      AREA   ||funwrap||, CODE, READONLY
  22 ENTRY(__scu_call_wrap)
  23         STMFD    r13!,{r4,r5,r6,lr}
  24         mov             r6,r2
  25         ldmia   r0, {r0-r5}
  26         STMFD    r13!,{r4,r5}
  27         mov     lr , pc
  28         mov pc , r6
  29         add     r13 , r13 ,#8
  30         LDMFD    r13!,{r4,r5,r6,pc}
  31
  32 /**
  33  * 20091126,HSL@RK,change to get syscall struct pt_regs *.
  34  * way: search stack frame for lr = ret_fast_syscall.
  35  * code from bachtrace.S -- __backtrace.
  36  * 20110126,not support at 2.6.32(no fp)
  37  * 20110127,support at debug.c,use c funtion.
  38  */
  39 #define frame   r4
  40 #define sv_fp   r5
  41 #define sv_pc   r6
  42 #define mask    r7
  43 #define offset  r8
  44 /*
  45 ENTRY(__scu_get_usr_regs)
  46                 mov r0, #0
  47                 mov     pc, lr
  48 */
  49
  50 /*
  51  * 20091215,continue running from break point.
  52  * r0 is the struct pt_regs *.
  53  */
  54 ENTRY(__scu_bk_continue)
  55         mov r12, r0
  56         ldr     r0, [r12, #S_PSR]
  57         msr     spsr_cxsf, r0
  58         ldmia   r12, {r0 - pc}^                 @ load r0 - pc, cpsr
  59
  60 ENTRY(__run)
  61                 mov r0, r0
  62                 mov     pc, lr
  63
  64
  65 /* 20110212,HSL@RK, USE parm0 for debug.
  66   *
  67   */
  68 ENTRY(__rb)
  69                 mov     r7,r0
  70 /*              adr   r0 , __rb_info
  71                 adr     r8, __prk
  72                 ldr     r8,[r8,#0]
  73                 adr     r1 , __rb
  74                 mov     lr , pc
  75                 bx      r8
  76                 mov     r0,#0x10000
  77                 bl __rb_delay
  78 */
  79                 mov     r8,r7
  80 /*              adr   r0 , __prk_info
  81 1:
  82                 ldrb    r1,[r0],#1
  83                 cmp r1,#0
  84                 strne r1,[r8,#0]
  85                 bne     1b
  86                 mov     r0,#0x20000
  87                 bl __rb_delay*/
  88
  89                 MRC p15,0,r0,c1,c0,0
  90                 BIC r0,r0,#(1<<0)          @disable mmu
  91                 BIC r0,r0,#(1<<13)    @set vector to 0x00000000
  92                 BIC r0,r0,#(1<<12)         @disable I CACHE
  93                 BIC r0,r0,#(1<<2)          @disable D DACHE
  94                 BIC r0,r0,#(1<<11)         @disable Z
  95                 BIC r0,r0,#(1<<28)         @disable TRE
  96                 MCR p15,0,r0,c1,c0,0
  97                 MOV r0,#0
  98                 mcr p15, 0, r0, c7, c10, 5
  99                 mcr p15, 0, r0, c7, c10, 4
 100                 isb
 101                 dsb
 102                 nop
 103                 nop
 104                 nop
 105
 106                 adr     r7,__regs
 107
 108                 ldr     r8,[r7,#0x10]  @uart1 reg
 109                 adr   r3 , __dbg_info
 110 2:
 111                 ldrb    r1,[r3],#1
 112                 cmp r1,#0
 113                 strne r1,[r8,#0]
 114                 bne     2b
 115
 116                 mov     r0,#0x20000
 117                 bl __rb_delay
 118
 119 wait:
 120                 @b wait
 121                 @arm slow mod.
 122                 ldr     r8,[r7,#0xc]  @CRU reg
 123                 ldr     r9,[r8,#0x10]
 124                 bic     r9,r9,#0x3      @CPU slow mode
 125                 bic r9,r9,#(0x3<<2) @Peri slow mode
 126                 str     r9,[r8,#0]
 127                 dsb
 128                 mov     r0,#0x10000
 129                 bl __rb_delay
 130
 131                 @recover SPI clk
 132                 ldr     r9,[r8,#0x0c] @CRU_PPLL_CON bit 15=1, Peri PLL power down
 133                 bic r9,r9,#(0x1<<15)
 134                 str r9,[r8,#0x0c]
 135                 dsb
 136                 mov     r0,#0x10000
 137                 bl __rb_delay
 138
 139                 ldr r9,[r8,#0x2c] @CRU_CLKSEL6_CON bit [8:2] = 7, bit [1:0] =0
 140                 bic r9,r9,#(0x7F<<2)
 141                 bic r9,r9,#(0x3)
 142                 orr r9,r9,#(0x7<<2)
 143                 str r9,[r8,#0x2c]
 144
 145                 @recover eMMC clk
 146                 ldr r9,[r8,#0x30] @CRU_CLKSEL7_CON bit [23:18] = 0x17, bit [1:0] = 0
 147                 bic r9,r9,#(0x3F<<18)
 148                 bic r9,r9,#0x3
 149                 orr r9,r9,#(0x17<<18)
 150                 str r9,[r8,#0x30]
 151
 152                 @recover UART1 clk
 153                 ldr r9,[r8,#0x34] @CRU_CLKSEL8_CON bit [21:20] = 0x2, bit [19:14] = 0, bit [2:0] = 0
 154                 bic r9,r9,#(0x3<<20)
 155                 bic r9,r9,#(0x3F<<14)
 156                 bic r9,r9,#0x7
 157                 orr r9,r9,#(0x2<<20)
 158                 str r9,[r8,#0x34]
 159
 160                 @clk enable
 161                 ldr r9,[r8,#0x5c]    @CRU_CLKGATE0_CON
 162                 bic r9,r9,#(0x1<<31) @GRF clk enable
 163                 bic r9,r9,#(0x1<<30) @PMU clk enable
 164                 bic r9,r9,#(0x1<<27) @DEBUG clk enable
 165                 bic r9,r9,#(0x7<<18) @DDR clk enable
 166                 bic r9,r9,#(0x1<<14) @mask rom clk enable
 167                 bic r9,r9,#(0x1<<12) @Int Mem clk enable
 168                 bic r9,r9,#(0x1<<11) @GIC clk enable
 169                 bic r9,r9,#(0xFF)    @CPU clk enable
 170                 bic r9,r9,#(0x1<<8)
 171                 str r9,[r8,#0x5c]
 172
 173                 ldr r9,[r8,#0x60]    @CRU_CLKGATE1_CON
 174                 bic r9,r9,#(0x3<<25) @USB clk enable
 175                 bic r9,r9,#(0x3<<23) @eMMC clk enable
 176                 bic r9,r9,#(0x1<<16) @NANC clk enable
 177                 bic r9,r9,#(0x1<<6)  @DDR PERIPH AXI clk enable
 178                 bic r9,r9,#0x17      @PERIPH clk enable
 179                 str r9,[r8,#0x60]
 180
 181                 ldr r9,[r8,#0x64]    @CRU_CLKGATE2_CON
 182                 bic r9,r9,#(0x1<<26) @JTAG clk enable
 183                 bic r9,r9,#(0x1<<15) @SPI0 clk enable
 184                 bic r9,r9,#0x1       @UART1 clk enable
 185                 str r9,[r8,#0x64]
 186
 187                 @soft de-reset
 188                 ldr r9,[r8,#0x6c]    @CRU_SOFTRST0_CON
 189                 bic r9,r9,#(0x1<<25) @ARM core DEBUG soft de-reset
 190                 bic r9,r9,#(0x1<<12) @mask rom soft de-reset
 191                 bic r9,r9,#(0x1<<9)  @Int Mem soft de-reset
 192                 bic r9,r9,#(0x1<<8)  @GIC soft de-reset
 193                 bic r9,r9,#0x3F      @CPU soft de-reset
 194                 str r9,[r8,#0x6c]
 195
 196                 ldr r9,[r8,#0x70]    @CRU_SOFTRST1_CON
 197                 bic r9,r9,#(0x1<<28) @UART1 soft de-reset
 198                 bic r9,r9,#(0x1<<25) @SPI0 soft de-reset
 199                 bic r9,r9,#(0x7<<16) @USB0 soft de-reset
 200                 bic r9,r9,#(0x1<<15) @EMMC soft de-reset
 201                 bic r9,r9,#(0x1<<9)  @NANC soft de-reset
 202                 bic r9,r9,#0x3F      @PERIPH soft de-reset
 203                 str r9,[r8,#0x70]
 204
 205                 ldr r9,[r8,#0x74]    @CRU_SOFTRST2_CON
 206                 bic r9,r9,#(0x1F<<8) @DDR soft de-reset
 207                 str r9,[r8,#0x74]
 208
 209                 @ unremap, and axi.
 210                 ldr     r8,[r7,#0]  @GRF reg
 211                 ldr     r9,[r8,#0xc0]
 212                 bic     r9,r9,#(1<<21)
 213                 str     r9,[r8,#0xc0]
 214
 215                 mov     r9,#0
 216                 ldr     r8,[r7,#4] @CPU_AXI_BUS0
 217                 str     r9,[r8,#0]
 218
 219                 ldr     r8,[r7,#8] @AXI1
 220                 str     r9,[r8,#0]
 221                 dsb
 222
 223                 @eMMC register recover
 224                 ldr     r8,[r7,#0]      @GRF reg
 225                 ldr r9,[r8,#0xbc]   @GRF_SOC_CON0
 226                 bic r9,r9,#(0x1<<9) @emmc_and_boot_en control=0
 227                 str r9,[r8,#0xbc]
 228
 229                 ldr     r8,[r7,#14]     @eMMC reg
 230                 mov r9,#0
 231                 str r9,[r8,#0xc]    @SDMMC_CLKSRC=0, clk_source=clock divider 0
 232                 str r9,[r8,#0x18]   @SDMMC_CTYPE=0, card_width=1 bit mode
 233                 mov r9,#0x200
 234                 str r9,[r8,#0x1c]   @SDMMC_BLKSIZ=0x200, Block size=512
 235
 236                 ldr     r8,[r7,#0x10] @uart1_reg
 237                 adr   r0 , __dbg_info1
 238 3:
 239                 ldrb    r1,[r0],#1
 240                 cmp r1,#0
 241                 strne r1,[r8,#0]
 242                 bne     3b
 243
 244                 mov     r0,#0x10000
 245                 bl __rb_delay
 246
 247         mov r4, #0
 248                 mov     pc, r4
 249
 250 __prk:
 251         .long           printk
 252 __rb_info:
 253         .asciz   "at reboot function,pc=0x%x\n"
 254 __prk_info:
 255         .asciz  "after printk!\n\r"
 256 __dbg_info:
 257         .asciz  "AFTER DIS MMU\n\r"
 258 __dbg_info1:
 259         .asciz  "LAST JUMP TO 0\n\r"
 260         .align
 261 __regs:
 262         .long           RK29_GRF_PHYS           @ 0x20008000 , unremap
 263         .long           RK29_CPU_AXI_BUS0_PHYS  @ 0x15000000
 264         .long           RK29_AXI1_PHYS          @ 0x10000000
 265         .long           RK29_CRU_PHYS           @ 0x20000000
 266         .long           RK29_UART1_PHYS         @ 0x20060000 , printk for debug.
 267         .long   RK29_EMMC_PHYS    @ 0x1021C000
 268         .align
 269
 270 __rb_delay:
 271         subs    r0, r0, #1
 272         bhi     __rb_delay
 273         mov     pc, lr
 274
 275 #if FIQ_ENABLE
 276         .align
 277 ENTRY(rk28_fiq_handle)
 278         mrs r8, spsr
 279         adr r9,__fiq_save
 280         stmia r9 , {r0-r8,lr}
 281         mov   r0,r9     @save addr.
 282         mov r5,#(SVC_MODE|PSR_I_BIT|PSR_F_BIT)
 283         msr  cpsr_cxsf,r5       @ to svc mod.disable irq,fiq.
 284         sub r1, sp, #(S_FRAME_SIZE)
 285
 286         add     r2 , r1 , #32   @ r0--r7.
 287         stmia  r2,{r8-lr}       @ the svc sp not change here.
 288         ldmia  r0,{r3-r10}
 289         stmia  r1,{r3-r10}
 290         ldr      r9,[r0,#36]     @get fiq lr.
 291         sub    r9,r9,#4
 292         str      r9 , [r1,#S_PC]
 293         ldr      r10,[r0,#32]     @get fiq spsr.
 294         str      r10, [r1,#S_PSR]
 295         mov    r5,r1
 296         mov    sp,r5    @stack frame
 297         mov    r0,r5
 298         ldr      r11,1f
 299         blx      r11
 300         b        3f
 301 1:
 302                 .long           rk28_debug_fiq
 303 3:
 304         msr  spsr_cxsf,r10
 305         ldmia r5, {r0 - pc}^
 306 __fiq_save:                @for save fiq spsr r0-r7,spsr,lr.
 307                 .long     0
 308                 .previous
 309 #endif
 310