2 * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, you can access it online at
15 * http://www.gnu.org/licenses/gpl-2.0.html.
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21 #include <linux/of_address.h>
22 #include <linux/platform_device.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
26 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/clk.h>
30 #include <linux/delay.h>
32 #include <asm/cacheflush.h>
33 #include <asm/tlbflush.h>
34 #include <linux/cpu.h>
35 #include <dt-bindings/clock/ddr.h>
36 #include <linux/rockchip/common.h>
37 #include <linux/rockchip/cpu.h>
38 #include <linux/rockchip/cru.h>
39 #include <linux/rockchip/dvfs.h>
40 #include <linux/rockchip/grf.h>
41 #include <linux/rockchip/iomap.h>
42 #include <linux/rockchip/pmu.h>
43 #include <linux/rk_fb.h>
44 #include <linux/scpi_protocol.h>
46 #define GRF_DDRC0_CON0 0x600
47 #define GRF_SOC_STATUS5 0x494
48 #define DDR_PCTL_TOGCNT_1U 0xc0
50 enum ddr_bandwidth_id {
60 struct regmap *ddrpctl_regs;
61 struct regmap *msch_regs;
62 struct regmap *grf_regs;
65 static struct rockchip_ddr *ddr_data = NULL;
67 static int _ddr_recalc_rate(void)
71 regmap_read(ddr_data->ddrpctl_regs, DDR_PCTL_TOGCNT_1U,
73 ddr_freq = ddr_freq * 2 * 1000000;
77 static int _ddr_change_freq(u32 n_mhz)
81 struct rk_lcdc_driver *lcdc_dev = NULL;
83 printk(KERN_DEBUG pr_fmt("In func %s,freq=%dMHz\n"), __func__, n_mhz);
84 lcdc_dev = rk_get_lcdc_drv("lcdc0");
85 lcdc_type = lcdc_dev ? (u32)lcdc_dev->cur_screen->type : 0;
86 printk(KERN_DEBUG pr_fmt("lcdc type:%d\n"), lcdc_type);
87 if (scpi_ddr_set_clk_rate(n_mhz, lcdc_type))
88 pr_info("set ddr freq timeout\n");
89 ret = _ddr_recalc_rate() / 1000000;
90 printk(KERN_DEBUG pr_fmt("Func %s out,freq=%dMHz\n"), __func__, ret);
94 static long _ddr_round_rate(u32 n_mhz)
96 return (n_mhz / 12) * 12;
99 static void _ddr_set_auto_self_refresh(bool en)
101 if (scpi_ddr_set_auto_self_refresh(en))
102 printk(KERN_DEBUG pr_fmt("ddr set auto selfrefresh error\n"));
105 static void ddr_monitor_start(void)
109 /* cpum, gpu probe */
110 for (i = 1; i < 3; i++) {
111 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x8,
113 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0xc,
115 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x138,
117 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x14c,
119 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x160,
121 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x174,
124 /* video, vio0, vio1 probe */
125 for (i = 0; i < 3; i++) {
126 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x8,
128 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0xc,
130 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x138,
132 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x14c,
134 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x160,
136 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x174,
140 regmap_write(ddr_data->grf_regs, GRF_DDRC0_CON0,
141 ((0x3 << 5) << 16) | 0x3 << 5);
144 /* trigger statistic */
145 for (i = 1; i < 3; i++)
146 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x28,
148 for (i = 0; i < 3; i++)
149 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x28,
153 static void ddr_monitor_stop(void)
156 regmap_write(ddr_data->grf_regs, GRF_DDRC0_CON0,
157 ((0x3 << 5) << 16) | 0x0 << 5);
160 static void _ddr_bandwidth_get(struct ddr_bw_info *ddr_bw_ch0,
161 struct ddr_bw_info *ddr_bw_ch1)
163 u32 ddr_bw_val[2][ddrbw_id_end], ddr_freq, dfi_freq;
173 for (j = 0; j < 2; j++) {
174 for (i = 0; i < ddrbw_eff; i++) {
175 regmap_read(ddr_data->grf_regs,
176 GRF_SOC_STATUS5 + 4 * i + j * 16,
180 if (!ddr_bw_val[0][ddrbw_time_num])
183 regmap_read(ddr_data->ddrpctl_regs, DDR_PCTL_TOGCNT_1U,
186 dfi_freq = ddr_freq / 2;
188 temp64 = ((u64) ddr_bw_val[0][0] + ddr_bw_val[0][1]
189 + ddr_bw_val[1][0] + ddr_bw_val[1][1]) * 2 * 100;
190 do_div(temp64, ddr_bw_val[0][ddrbw_time_num]);
191 ddr_bw_val[0][ddrbw_eff] = temp64;
192 ddr_bw_ch0->ddr_percent = temp64;
193 ddr_bw_ch0->ddr_time =
194 ddr_bw_val[0][ddrbw_time_num] / (dfi_freq * 1000);
196 ddr_bw_ch0->ddr_wr = (((u64)
197 (ddr_bw_val[0][ddrbw_wr_num] +
198 ddr_bw_val[1][ddrbw_wr_num]) * 8 * 4) *
199 dfi_freq) / ddr_bw_val[0][ddrbw_time_num];
200 ddr_bw_ch0->ddr_rd = (((u64)
201 (ddr_bw_val[0][ddrbw_rd_num] +
202 ddr_bw_val[1][ddrbw_rd_num]) * 8 * 4) *
203 dfi_freq) / ddr_bw_val[0][ddrbw_time_num];
204 ddr_bw_ch0->ddr_act = ddr_bw_val[0][ddrbw_act_num];
205 ddr_bw_ch0->ddr_total = ddr_freq * 2 * 4;
207 regmap_read(ddr_data->msch_regs, 0x1400 + 0x178, &tmp32);
208 regmap_read(ddr_data->msch_regs, 0x1400 + 0x164,
210 ddr_bw_ch0->cpum += (tmp32 << 16);
211 regmap_read(ddr_data->msch_regs, 0x1800 + 0x178, &tmp32);
212 regmap_read(ddr_data->msch_regs, 0x1800 + 0x164,
214 ddr_bw_ch0->gpu += (tmp32 << 16);
215 ddr_bw_ch0->peri = 0;
216 regmap_read(ddr_data->msch_regs, 0x2000 + 0x178, &tmp32);
217 regmap_read(ddr_data->msch_regs, 0x2000 + 0x164,
219 ddr_bw_ch0->video += (tmp32 << 16);
220 regmap_read(ddr_data->msch_regs, 0x2400 + 0x178, &tmp32);
221 regmap_read(ddr_data->msch_regs, 0x2400 + 0x164,
223 ddr_bw_ch0->vio0 += (tmp32 << 16);
224 regmap_read(ddr_data->msch_regs, 0x2800 + 0x178, &tmp32);
225 regmap_read(ddr_data->msch_regs, 0x2800 + 0x164,
227 ddr_bw_ch0->vio1 += (tmp32 << 16);
228 ddr_bw_ch0->vio2 = 0;
232 (u64) ddr_bw_ch0->cpum * dfi_freq /
233 ddr_bw_val[0][ddrbw_time_num];
235 (u64) ddr_bw_ch0->gpu * dfi_freq /
236 ddr_bw_val[0][ddrbw_time_num];
238 (u64) ddr_bw_ch0->peri * dfi_freq /
239 ddr_bw_val[0][ddrbw_time_num];
241 (u64) ddr_bw_ch0->video * dfi_freq /
242 ddr_bw_val[0][ddrbw_time_num];
244 (u64) ddr_bw_ch0->vio0 * dfi_freq /
245 ddr_bw_val[0][ddrbw_time_num];
247 (u64) ddr_bw_ch0->vio1 * dfi_freq /
248 ddr_bw_val[0][ddrbw_time_num];
250 (u64) ddr_bw_ch0->vio2 * dfi_freq /
251 ddr_bw_val[0][ddrbw_time_num];
257 static void ddr_init(u32 dram_speed_bin, u32 freq)
261 struct rk_lcdc_driver *lcdc_dev = NULL;
263 lcdc_dev = rk_get_lcdc_drv("lcdc0");
264 if (lcdc_dev == NULL)
267 lcdc_type = (u32)lcdc_dev->cur_screen->type;
268 printk(KERN_DEBUG pr_fmt("In Func:%s,dram_speed_bin:%d,freq:%d,lcdc_type:%d\n"),
269 __func__, dram_speed_bin, freq, lcdc_type);
270 if (scpi_ddr_init(dram_speed_bin, freq, lcdc_type))
271 pr_info("ddr init error\n");
273 printk(KERN_DEBUG pr_fmt("%s out\n"), __func__);
276 static int ddr_init_resume(struct platform_device *pdev)
278 ddr_init(DDR3_DEFAULT, 0);
282 static int __init rockchip_ddr_probe(struct platform_device *pdev)
284 struct device_node *np;
286 np = pdev->dev.of_node;
288 devm_kzalloc(&pdev->dev, sizeof(struct rockchip_ddr), GFP_KERNEL);
290 dev_err(&pdev->dev, "no memory for state\n");
294 ddr_data->ddrpctl_regs =
295 syscon_regmap_lookup_by_phandle(np, "rockchip,ddrpctl");
296 if (IS_ERR(ddr_data->ddrpctl_regs)) {
297 dev_err(&pdev->dev, "%s: could not find ddrpctl dt node\n",
304 syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
305 if (IS_ERR(ddr_data->grf_regs)) {
306 dev_err(&pdev->dev, "%s: could not find grf dt node\n",
311 ddr_data->msch_regs =
312 syscon_regmap_lookup_by_phandle(np, "rockchip,msch");
313 if (IS_ERR(ddr_data->msch_regs)) {
314 dev_err(&pdev->dev, "%s: could not find msch dt node\n",
319 platform_set_drvdata(pdev, ddr_data);
320 ddr_change_freq = _ddr_change_freq;
321 ddr_round_rate = _ddr_round_rate;
322 ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
323 ddr_bandwidth_get = _ddr_bandwidth_get;
324 ddr_recalc_rate = _ddr_recalc_rate;
325 ddr_init(DDR3_DEFAULT, 0);
326 pr_info("%s: success\n", __func__);
330 static const struct of_device_id rockchip_ddr_of_match[] __refdata = {
331 {.compatible = "rockchip,rk3368-ddr", .data = NULL,},
335 static struct platform_driver rockchip_ddr_driver = {
337 .resume = ddr_init_resume,
338 #endif /* CONFIG_PM */
340 .name = "rockchip_ddr",
341 .of_match_table = rockchip_ddr_of_match,
345 static int __init rockchip_ddr_init(void)
347 pr_info("rockchip_ddr_init\n");
348 return platform_driver_probe(&rockchip_ddr_driver, rockchip_ddr_probe);
351 device_initcall(rockchip_ddr_init);