2 * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, you can access it online at
15 * http://www.gnu.org/licenses/gpl-2.0.html.
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21 #include <linux/of_address.h>
22 #include <linux/platform_device.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
26 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/clk.h>
30 #include <linux/delay.h>
32 #include <asm/cacheflush.h>
33 #include <asm/tlbflush.h>
34 #include <linux/cpu.h>
35 #include <dt-bindings/clock/ddr.h>
36 #include <linux/rockchip/common.h>
37 #include <linux/rockchip/cpu.h>
38 #include <linux/rockchip/cru.h>
39 #include <linux/rockchip/dvfs.h>
40 #include <linux/rockchip/grf.h>
41 #include <linux/rockchip/iomap.h>
42 #include <linux/rockchip/pmu.h>
43 #include <linux/rk_fb.h>
44 #include <linux/scpi_protocol.h>
46 #define GRF_DDRC0_CON0 0x600
47 #define GRF_SOC_STATUS5 0x494
48 #define DDR_PCTL_TOGCNT_1U 0xc0
50 enum ddr_bandwidth_id {
60 struct regmap *ddrpctl_regs;
61 struct regmap *msch_regs;
62 struct regmap *grf_regs;
65 static struct rockchip_ddr *ddr_data = NULL;
67 static int _ddr_change_freq(u32 n_mhz)
71 printk(KERN_DEBUG pr_fmt("In func %s,freq=%dMHz\n"), __func__, n_mhz);
72 if (scpi_ddr_set_clk_rate(n_mhz))
73 pr_info("set ddr freq timeout\n");
74 ret = scpi_ddr_get_clk_rate();
75 printk(KERN_DEBUG pr_fmt("Func %s out,freq=%dMHz\n"), __func__, ret);
79 static long _ddr_round_rate(u32 n_mhz)
81 return (n_mhz / 12) * 12;
84 static int _ddr_recalc_rate(void)
86 return (1000000 * scpi_ddr_get_clk_rate());
89 static void _ddr_set_auto_self_refresh(bool en)
91 if (scpi_ddr_set_auto_self_refresh(en))
92 printk(KERN_DEBUG pr_fmt("ddr set auto selfrefresh error\n"));
95 static void ddr_monitor_start(void)
100 for (i = 1; i < 3; i++) {
101 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x8,
103 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0xc,
105 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x138,
107 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x14c,
109 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x160,
111 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x174,
114 /* video, vio0, vio1 probe */
115 for (i = 0; i < 3; i++) {
116 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x8,
118 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0xc,
120 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x138,
122 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x14c,
124 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x160,
126 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x174,
130 regmap_write(ddr_data->grf_regs, GRF_DDRC0_CON0,
131 ((0x3 << 5) << 16) | 0x3 << 5);
134 /* trigger statistic */
135 for (i = 1; i < 3; i++)
136 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x28,
138 for (i = 0; i < 3; i++)
139 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x28,
143 static void ddr_monitor_stop(void)
146 regmap_write(ddr_data->grf_regs, GRF_DDRC0_CON0,
147 ((0x3 << 5) << 16) | 0x0 << 5);
150 static void _ddr_bandwidth_get(struct ddr_bw_info *ddr_bw_ch0,
151 struct ddr_bw_info *ddr_bw_ch1)
153 u32 ddr_bw_val[2][ddrbw_id_end], ddr_freq, dfi_freq;
163 for (j = 0; j < 2; j++) {
164 for (i = 0; i < ddrbw_eff; i++) {
165 regmap_read(ddr_data->grf_regs,
166 GRF_SOC_STATUS5 + 4 * i + j * 16,
170 if (!ddr_bw_val[0][ddrbw_time_num])
173 regmap_read(ddr_data->ddrpctl_regs, DDR_PCTL_TOGCNT_1U,
176 dfi_freq = ddr_freq / 2;
178 temp64 = ((u64) ddr_bw_val[0][0] + ddr_bw_val[0][1]
179 + ddr_bw_val[1][0] + ddr_bw_val[1][1]) * 2 * 100;
180 do_div(temp64, ddr_bw_val[0][ddrbw_time_num]);
181 ddr_bw_val[0][ddrbw_eff] = temp64;
182 ddr_bw_ch0->ddr_percent = temp64;
183 ddr_bw_ch0->ddr_time =
184 ddr_bw_val[0][ddrbw_time_num] / (dfi_freq * 1000);
186 ddr_bw_ch0->ddr_wr = (((u64)
187 (ddr_bw_val[0][ddrbw_wr_num] +
188 ddr_bw_val[1][ddrbw_wr_num]) * 8 * 4) *
189 dfi_freq) / ddr_bw_val[0][ddrbw_time_num];
190 ddr_bw_ch0->ddr_rd = (((u64)
191 (ddr_bw_val[0][ddrbw_rd_num] +
192 ddr_bw_val[1][ddrbw_rd_num]) * 8 * 4) *
193 dfi_freq) / ddr_bw_val[0][ddrbw_time_num];
194 ddr_bw_ch0->ddr_act = ddr_bw_val[0][ddrbw_act_num];
195 ddr_bw_ch0->ddr_total = ddr_freq * 2 * 4;
197 regmap_read(ddr_data->msch_regs, 0x1400 + 0x178, &tmp32);
198 regmap_read(ddr_data->msch_regs, 0x1400 + 0x164,
200 ddr_bw_ch0->cpum += (tmp32 << 16);
201 regmap_read(ddr_data->msch_regs, 0x1800 + 0x178, &tmp32);
202 regmap_read(ddr_data->msch_regs, 0x1800 + 0x164,
204 ddr_bw_ch0->gpu += (tmp32 << 16);
205 ddr_bw_ch0->peri = 0;
206 regmap_read(ddr_data->msch_regs, 0x2000 + 0x178, &tmp32);
207 regmap_read(ddr_data->msch_regs, 0x2000 + 0x164,
209 ddr_bw_ch0->video += (tmp32 << 16);
210 regmap_read(ddr_data->msch_regs, 0x2400 + 0x178, &tmp32);
211 regmap_read(ddr_data->msch_regs, 0x2400 + 0x164,
213 ddr_bw_ch0->vio0 += (tmp32 << 16);
214 regmap_read(ddr_data->msch_regs, 0x2800 + 0x178, &tmp32);
215 regmap_read(ddr_data->msch_regs, 0x2800 + 0x164,
217 ddr_bw_ch0->vio1 += (tmp32 << 16);
218 ddr_bw_ch0->vio2 = 0;
222 (u64) ddr_bw_ch0->cpum * dfi_freq /
223 ddr_bw_val[0][ddrbw_time_num];
225 (u64) ddr_bw_ch0->gpu * dfi_freq /
226 ddr_bw_val[0][ddrbw_time_num];
228 (u64) ddr_bw_ch0->peri * dfi_freq /
229 ddr_bw_val[0][ddrbw_time_num];
231 (u64) ddr_bw_ch0->video * dfi_freq /
232 ddr_bw_val[0][ddrbw_time_num];
234 (u64) ddr_bw_ch0->vio0 * dfi_freq /
235 ddr_bw_val[0][ddrbw_time_num];
237 (u64) ddr_bw_ch0->vio1 * dfi_freq /
238 ddr_bw_val[0][ddrbw_time_num];
240 (u64) ddr_bw_ch0->vio2 * dfi_freq /
241 ddr_bw_val[0][ddrbw_time_num];
247 static void ddr_init(u32 dram_speed_bin, u32 freq)
249 printk(KERN_DEBUG pr_fmt("In Func:%s,dram_speed_bin:%d,freq:%d\n"),
250 __func__, dram_speed_bin, freq);
251 if (scpi_ddr_init(dram_speed_bin, freq))
252 pr_info("ddr init error\n");
254 printk(KERN_DEBUG pr_fmt("%s out\n"), __func__);
257 static int __init rockchip_ddr_probe(struct platform_device *pdev)
259 struct device_node *np;
261 np = pdev->dev.of_node;
263 devm_kzalloc(&pdev->dev, sizeof(struct rockchip_ddr), GFP_KERNEL);
265 dev_err(&pdev->dev, "no memory for state\n");
269 ddr_data->ddrpctl_regs =
270 syscon_regmap_lookup_by_phandle(np, "rockchip,ddrpctl");
271 if (IS_ERR(ddr_data->ddrpctl_regs)) {
272 dev_err(&pdev->dev, "%s: could not find ddrpctl dt node\n",
279 syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
280 if (IS_ERR(ddr_data->grf_regs)) {
281 dev_err(&pdev->dev, "%s: could not find grf dt node\n",
286 ddr_data->msch_regs =
287 syscon_regmap_lookup_by_phandle(np, "rockchip,msch");
288 if (IS_ERR(ddr_data->msch_regs)) {
289 dev_err(&pdev->dev, "%s: could not find msch dt node\n",
294 platform_set_drvdata(pdev, ddr_data);
295 ddr_change_freq = _ddr_change_freq;
296 ddr_round_rate = _ddr_round_rate;
297 ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
298 ddr_bandwidth_get = _ddr_bandwidth_get;
299 ddr_recalc_rate = _ddr_recalc_rate;
300 ddr_init(DDR3_DEFAULT, 0);
301 pr_info("%s: success\n", __func__);
305 static const struct of_device_id rockchip_ddr_of_match[] __refdata = {
306 {.compatible = "rockchip,rk3368-ddr", .data = NULL,},
310 static struct platform_driver rockchip_ddr_driver = {
312 .name = "rockchip_ddr",
313 .of_match_table = rockchip_ddr_of_match,
317 static int __init rockchip_ddr_init(void)
319 pr_info("rockchip_ddr_init\n");
320 return platform_driver_probe(&rockchip_ddr_driver, rockchip_ddr_probe);
323 device_initcall(rockchip_ddr_init);