2 * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, you can access it online at
15 * http://www.gnu.org/licenses/gpl-2.0.html.
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <dt-bindings/clock/ddr.h>
21 #include <linux/delay.h>
22 #include <linux/mfd/syscon.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
26 #include <linux/rk_fb.h>
27 #include <linux/rockchip/common.h>
28 #include <linux/rockchip/psci.h>
29 #include <linux/scpi_protocol.h>
30 #include <asm/compiler.h>
32 #define GRF_DDRC0_CON0 0x600
33 #define GRF_SOC_STATUS5 0x494
34 #define DDR_PCTL_TOGCNT_1U 0xc0
36 #define FIQ_CPU_TGT_BOOT 0x0 /* to booting cpu */
37 #define FIQ_NUM_FOR_DCF (143) /*NA irq map to fiq for dcf*/
40 #define DDR_VERSION "V1.03 20150910"
42 enum ddr_bandwidth_id {
55 u32 dram_dll_dis_freq;
57 u32 dram_odt_dis_freq;
71 struct regmap *ddrpctl_regs;
72 struct regmap *msch_regs;
73 struct regmap *grf_regs;
74 struct ddr_timing dram_timing;
77 static struct rockchip_ddr *ddr_data = NULL;
79 static int of_do_get_timings(struct device_node *np, struct ddr_timing *tim)
81 struct device_node *np_tim;
86 np_tim = of_parse_phandle(np, "rockchip,ddr_timing", 0);
90 ret |= of_property_read_u32(np_tim, "dram_spd_bin",
92 ret |= of_property_read_u32(np_tim, "sr_idle", &tim->sr_idle);
93 ret |= of_property_read_u32(np_tim, "pd_idle", &tim->pd_idle);
94 ret |= of_property_read_u32(np_tim, "dram_dll_disb_freq",
95 &tim->dram_dll_dis_freq);
96 ret |= of_property_read_u32(np_tim, "phy_dll_disb_freq",
97 &tim->phy_dll_dis_freq);
98 ret |= of_property_read_u32(np_tim, "dram_odt_disb_freq",
99 &tim->dram_odt_dis_freq);
100 ret |= of_property_read_u32(np_tim, "phy_odt_disb_freq",
101 &tim->phy_odt_dis_freq);
102 ret |= of_property_read_u32(np_tim, "ddr3_drv", &tim->ddr3_drv);
103 ret |= of_property_read_u32(np_tim, "ddr3_odt", &tim->ddr3_odt);
104 ret |= of_property_read_u32(np_tim, "lpddr3_drv", &tim->lpddr3_drv);
105 ret |= of_property_read_u32(np_tim, "lpddr3_odt", &tim->lpddr3_odt);
106 ret |= of_property_read_u32(np_tim, "lpddr2_drv", &tim->lpddr2_drv);
107 ret |= of_property_read_u32(np_tim, "phy_clk_drv", &tim->phy_clk_drv);
108 ret |= of_property_read_u32(np_tim, "phy_cmd_drv", &tim->phy_cmd_drv);
109 ret |= of_property_read_u32(np_tim, "phy_dqs_drv", &tim->phy_dqs_drv);
110 ret |= of_property_read_u32(np_tim, "phy_odt", &tim->phy_odt);
115 static int _ddr_recalc_rate(void)
119 regmap_read(ddr_data->ddrpctl_regs, DDR_PCTL_TOGCNT_1U,
121 ddr_freq = ddr_freq * 2 * 1000000;
125 static int _ddr_change_freq(u32 n_mhz)
129 struct rk_lcdc_driver *lcdc_dev = NULL;
131 printk(KERN_DEBUG pr_fmt("In func %s,freq=%dMHz\n"), __func__, n_mhz);
132 lcdc_dev = rk_get_lcdc_drv("lcdc0");
133 lcdc_type = lcdc_dev ? (u32)lcdc_dev->cur_screen->type : 0;
134 printk(KERN_DEBUG pr_fmt("lcdc type:%d\n"), lcdc_type);
135 if (scpi_ddr_set_clk_rate(n_mhz, lcdc_type))
136 pr_info("set ddr freq timeout\n");
137 ret = _ddr_recalc_rate() / 1000000;
138 printk(KERN_DEBUG pr_fmt("Func %s out,freq=%dMHz\n"), __func__, ret);
142 static long _ddr_round_rate(u32 n_mhz)
144 return (n_mhz / 12) * 12;
147 static void _ddr_set_auto_self_refresh(bool en)
149 if (scpi_ddr_set_auto_self_refresh(en))
150 printk(KERN_DEBUG pr_fmt("ddr set auto selfrefresh error\n"));
153 static void ddr_monitor_start(void)
157 /* cpum, gpu probe */
158 for (i = 1; i < 3; i++) {
159 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x8,
161 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0xc,
163 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x138,
165 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x14c,
167 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x160,
169 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x174,
172 /* video, vio0, vio1 probe */
173 for (i = 0; i < 3; i++) {
174 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x8,
176 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0xc,
178 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x138,
180 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x14c,
182 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x160,
184 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x174,
188 regmap_write(ddr_data->grf_regs, GRF_DDRC0_CON0,
189 ((0x3 << 5) << 16) | 0x3 << 5);
192 /* trigger statistic */
193 for (i = 1; i < 3; i++)
194 regmap_write(ddr_data->msch_regs, 0x1000 + (0x400 * i) + 0x28,
196 for (i = 0; i < 3; i++)
197 regmap_write(ddr_data->msch_regs, 0x2000 + (0x400 * i) + 0x28,
201 static void ddr_monitor_stop(void)
204 regmap_write(ddr_data->grf_regs, GRF_DDRC0_CON0,
205 ((0x3 << 5) << 16) | 0x0 << 5);
208 static void _ddr_bandwidth_get(struct ddr_bw_info *ddr_bw_ch0,
209 struct ddr_bw_info *ddr_bw_ch1)
211 u32 ddr_bw_val[2][ddrbw_id_end], ddr_freq, dfi_freq;
221 for (j = 0; j < 2; j++) {
222 for (i = 0; i < ddrbw_eff; i++) {
223 regmap_read(ddr_data->grf_regs,
224 GRF_SOC_STATUS5 + 4 * i + j * 16,
228 if (!ddr_bw_val[0][ddrbw_time_num])
231 regmap_read(ddr_data->ddrpctl_regs, DDR_PCTL_TOGCNT_1U,
234 dfi_freq = ddr_freq / 2;
236 temp64 = ((u64) ddr_bw_val[0][0] + ddr_bw_val[0][1]
237 + ddr_bw_val[1][0] + ddr_bw_val[1][1]) * 2 * 100;
238 do_div(temp64, ddr_bw_val[0][ddrbw_time_num]);
239 ddr_bw_val[0][ddrbw_eff] = temp64;
240 ddr_bw_ch0->ddr_percent = temp64;
241 ddr_bw_ch0->ddr_time =
242 ddr_bw_val[0][ddrbw_time_num] / (dfi_freq * 1000);
244 ddr_bw_ch0->ddr_wr = (((u64)
245 (ddr_bw_val[0][ddrbw_wr_num] +
246 ddr_bw_val[1][ddrbw_wr_num]) * 8 * 4) *
247 dfi_freq) / ddr_bw_val[0][ddrbw_time_num];
248 ddr_bw_ch0->ddr_rd = (((u64)
249 (ddr_bw_val[0][ddrbw_rd_num] +
250 ddr_bw_val[1][ddrbw_rd_num]) * 8 * 4) *
251 dfi_freq) / ddr_bw_val[0][ddrbw_time_num];
252 ddr_bw_ch0->ddr_act = ddr_bw_val[0][ddrbw_act_num];
253 ddr_bw_ch0->ddr_total = ddr_freq * 2 * 4;
255 regmap_read(ddr_data->msch_regs, 0x1400 + 0x178, &tmp32);
256 regmap_read(ddr_data->msch_regs, 0x1400 + 0x164,
258 ddr_bw_ch0->cpum += (tmp32 << 16);
259 regmap_read(ddr_data->msch_regs, 0x1800 + 0x178, &tmp32);
260 regmap_read(ddr_data->msch_regs, 0x1800 + 0x164,
262 ddr_bw_ch0->gpu += (tmp32 << 16);
263 ddr_bw_ch0->peri = 0;
264 regmap_read(ddr_data->msch_regs, 0x2000 + 0x178, &tmp32);
265 regmap_read(ddr_data->msch_regs, 0x2000 + 0x164,
267 ddr_bw_ch0->video += (tmp32 << 16);
268 regmap_read(ddr_data->msch_regs, 0x2400 + 0x178, &tmp32);
269 regmap_read(ddr_data->msch_regs, 0x2400 + 0x164,
271 ddr_bw_ch0->vio0 += (tmp32 << 16);
272 regmap_read(ddr_data->msch_regs, 0x2800 + 0x178, &tmp32);
273 regmap_read(ddr_data->msch_regs, 0x2800 + 0x164,
275 ddr_bw_ch0->vio1 += (tmp32 << 16);
276 ddr_bw_ch0->vio2 = 0;
280 (u64) ddr_bw_ch0->cpum * dfi_freq /
281 ddr_bw_val[0][ddrbw_time_num];
283 (u64) ddr_bw_ch0->gpu * dfi_freq /
284 ddr_bw_val[0][ddrbw_time_num];
286 (u64) ddr_bw_ch0->peri * dfi_freq /
287 ddr_bw_val[0][ddrbw_time_num];
289 (u64) ddr_bw_ch0->video * dfi_freq /
290 ddr_bw_val[0][ddrbw_time_num];
292 (u64) ddr_bw_ch0->vio0 * dfi_freq /
293 ddr_bw_val[0][ddrbw_time_num];
295 (u64) ddr_bw_ch0->vio1 * dfi_freq /
296 ddr_bw_val[0][ddrbw_time_num];
298 (u64) ddr_bw_ch0->vio2 * dfi_freq /
299 ddr_bw_val[0][ddrbw_time_num];
305 static void ddr_init(u32 dram_speed_bin, u32 freq, u32 addr_mcu_el3)
310 struct rk_lcdc_driver *lcdc_dev = NULL;
315 lcdc_dev = rk_get_lcdc_drv("lcdc0");
316 if (lcdc_dev == NULL)
319 lcdc_type = (u32)lcdc_dev->cur_screen->type;
320 printk(KERN_DEBUG pr_fmt("In Func:%s,dram_speed_bin:%d,freq:%d,lcdc_type:%d\n"),
321 __func__, dram_speed_bin, freq, lcdc_type);
322 if (scpi_ddr_init(dram_speed_bin, freq, lcdc_type, addr))
323 pr_info("ddr init error\n");
325 printk(KERN_DEBUG pr_fmt("%s out\n"), __func__);
328 static int ddr_init_resume(struct platform_device *pdev)
330 ddr_init(DDR3_DEFAULT, 0, 0);
333 #define RKTF_VER_MAJOR(ver) (((ver) >> 16) & 0xffff)
334 #define RKTF_VER_MINOR(ver) ((ver) & 0xffff)
336 #define RKTF_VLDVER_MAJOR (1)
337 #define RKTF_VLDVER_MINOR (5)
339 static int __init rockchip_tf_ver_check(void)
343 version = rockchip_psci_smc_get_tf_ver();
344 if (((RKTF_VER_MAJOR(version) == RKTF_VLDVER_MAJOR) &&
345 (RKTF_VER_MINOR(version) >= RKTF_VLDVER_MINOR)) ||
346 (RKTF_VER_MAJOR(version) > RKTF_VLDVER_MAJOR))
349 pr_err("read tf version 0x%x!\n", version);
353 pr_err("trusted firmware need to update to(%d.%d) or is invaild!\n",
354 RKTF_VLDVER_MAJOR, RKTF_VLDVER_MINOR);
361 static int __init rockchip_ddr_probe(struct platform_device *pdev)
364 struct device_node *np;
366 pr_info("Rockchip DDR Initialize, verision: "DDR_VERSION"\n");
367 np = pdev->dev.of_node;
369 devm_kzalloc(&pdev->dev, sizeof(struct rockchip_ddr), GFP_KERNEL);
371 dev_err(&pdev->dev, "no memory for state\n");
375 ddr_data->ddrpctl_regs =
376 syscon_regmap_lookup_by_phandle(np, "rockchip,ddrpctl");
377 if (IS_ERR(ddr_data->ddrpctl_regs)) {
378 dev_err(&pdev->dev, "%s: could not find ddrpctl dt node\n",
385 syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
386 if (IS_ERR(ddr_data->grf_regs)) {
387 dev_err(&pdev->dev, "%s: could not find grf dt node\n",
392 ddr_data->msch_regs =
393 syscon_regmap_lookup_by_phandle(np, "rockchip,msch");
394 if (IS_ERR(ddr_data->msch_regs)) {
395 dev_err(&pdev->dev, "%s: could not find msch dt node\n",
400 platform_set_drvdata(pdev, ddr_data);
401 ddr_change_freq = _ddr_change_freq;
402 ddr_round_rate = _ddr_round_rate;
403 ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
404 ddr_bandwidth_get = _ddr_bandwidth_get;
405 ddr_recalc_rate = _ddr_recalc_rate;
406 rockchip_tf_ver_check();
407 if (!of_do_get_timings(np, (struct ddr_timing *)&ddr_data->dram_timing)) {
408 if (scpi_ddr_send_timing((u32 *)&ddr_data->dram_timing,
409 sizeof(struct ddr_timing)))
410 pr_info("send ddr timing timeout\n");
412 pr_err("get ddr timing from dts error\n");
413 ddr_data->dram_timing.dram_spd_bin = DDR3_DEFAULT;
415 addr_mcu_el3 = rockchip_psci_smc_write(PSCI_SIP_EL3FIQ_CFG,
417 FIQ_CPU_TGT_BOOT, 0);
418 if ((addr_mcu_el3 == 0) || (addr_mcu_el3 > 0x80000))
419 pr_info("Trust version error, pls check trust version\n");
420 ddr_init(ddr_data->dram_timing.dram_spd_bin, 0, addr_mcu_el3);
421 pr_info("%s: success\n", __func__);
425 static const struct of_device_id rockchip_ddr_of_match[] __refdata = {
426 {.compatible = "rockchip,rk3368-ddr", .data = NULL,},
430 static struct platform_driver rockchip_ddr_driver = {
432 .resume = ddr_init_resume,
433 #endif /* CONFIG_PM */
435 .name = "rockchip_ddr",
436 .of_match_table = rockchip_ddr_of_match,
440 static int __init rockchip_ddr_init(void)
442 return platform_driver_probe(&rockchip_ddr_driver, rockchip_ddr_probe);
445 device_initcall(rockchip_ddr_init);