2 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
3 * Author: Lin Huang <hl@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/arm-smccc.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/devfreq.h>
19 #include <linux/devfreq-event.h>
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_opp.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/rwsem.h>
27 #include <linux/slab.h>
28 #include <linux/suspend.h>
30 #include <soc/rockchip/rkfb_dmc.h>
31 #include <soc/rockchip/rockchip_sip.h>
34 unsigned int ddr3_speed_bin;
37 unsigned int sr_mc_gate_idle;
38 unsigned int srpd_lite_idle;
39 unsigned int standby_idle;
40 unsigned int dram_dll_dis_freq;
41 unsigned int phy_dll_dis_freq;
42 unsigned int ddr3_odt_dis_freq;
43 unsigned int ddr3_drv;
44 unsigned int ddr3_odt;
45 unsigned int phy_ddr3_ca_drv;
46 unsigned int phy_ddr3_dq_drv;
47 unsigned int phy_ddr3_odt;
48 unsigned int lpddr3_odt_dis_freq;
49 unsigned int lpddr3_drv;
50 unsigned int lpddr3_odt;
51 unsigned int phy_lpddr3_ca_drv;
52 unsigned int phy_lpddr3_dq_drv;
53 unsigned int phy_lpddr3_odt;
54 unsigned int lpddr4_odt_dis_freq;
55 unsigned int lpddr4_drv;
56 unsigned int lpddr4_dq_odt;
57 unsigned int lpddr4_ca_odt;
58 unsigned int phy_lpddr4_ca_drv;
59 unsigned int phy_lpddr4_ck_cs_drv;
60 unsigned int phy_lpddr4_dq_drv;
61 unsigned int phy_lpddr4_odt;
64 struct rk3399_dmcfreq {
66 struct devfreq *devfreq;
67 struct devfreq_simple_ondemand_data ondemand_data;
69 struct devfreq_event_dev *edev;
71 struct dram_timing *timing;
74 * DDR Converser of Frequency (DCF) is used to implement DDR frequency
75 * conversion without the participation of CPU, we will implement and
76 * control it in arm trust firmware.
78 wait_queue_head_t wait_dcf_queue;
81 struct regulator *vdd_center;
82 unsigned long rate, target_rate;
83 unsigned long volt, target_volt;
86 static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
89 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
90 struct dev_pm_opp *opp;
91 unsigned long old_clk_rate = dmcfreq->rate;
92 unsigned long temp_rate, target_volt, target_rate;
96 opp = devfreq_recommended_opp(dev, freq, flags);
102 temp_rate = dev_pm_opp_get_freq(opp);
103 target_rate = clk_round_rate(dmcfreq->dmc_clk, temp_rate);
104 if ((long)target_rate <= 0)
105 target_rate = temp_rate;
106 target_volt = dev_pm_opp_get_voltage(opp);
110 if (dmcfreq->rate == target_rate) {
111 if (dmcfreq->volt == target_volt)
113 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
116 dev_err(dev, "Cannot to set voltage %lu uV\n",
123 mutex_lock(&dmcfreq->lock);
126 * If frequency scaling from low to high, adjust voltage first.
127 * If frequency scaling from high to low, adjust frequency first.
129 if (old_clk_rate < target_rate) {
130 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
133 dev_err(dev, "Cannot to set voltage %lu uV\n",
139 err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
141 dev_err(dev, "Cannot to set frequency %lu (%d)\n",
143 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
149 * Check the dpll rate,
150 * There only two result we will get,
151 * 1. Ddr frequency scaling fail, we still get the old rate.
152 * 2. Ddr frequency scaling sucessful, we get the rate we set.
154 dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
156 /* If get the incorrect rate, set voltage to old value. */
157 if (dmcfreq->rate != target_rate) {
158 dev_err(dev, "Get wrong ddr frequency, Request frequency %lu,\
159 Current frequency %lu\n", target_rate, dmcfreq->rate);
160 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
163 } else if (old_clk_rate > target_rate) {
164 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
167 dev_err(dev, "Cannot to set vol %lu uV\n", target_volt);
172 dmcfreq->volt = target_volt;
174 mutex_unlock(&dmcfreq->lock);
178 static int rk3399_dmcfreq_get_dev_status(struct device *dev,
179 struct devfreq_dev_status *stat)
181 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
182 struct devfreq_event_data edata;
185 ret = devfreq_event_get_event(dmcfreq->edev, &edata);
189 stat->current_frequency = dmcfreq->rate;
190 stat->busy_time = edata.load_count;
191 stat->total_time = edata.total_count;
196 static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
198 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
200 *freq = dmcfreq->rate;
205 static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
207 .target = rk3399_dmcfreq_target,
208 .get_dev_status = rk3399_dmcfreq_get_dev_status,
209 .get_cur_freq = rk3399_dmcfreq_get_cur_freq,
212 static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
214 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
217 ret = devfreq_event_disable_edev(dmcfreq->edev);
219 dev_err(dev, "failed to disable the devfreq-event devices\n");
223 ret = devfreq_suspend_device(dmcfreq->devfreq);
225 dev_err(dev, "failed to suspend the devfreq devices\n");
232 static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
234 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
237 ret = devfreq_event_enable_edev(dmcfreq->edev);
239 dev_err(dev, "failed to enable the devfreq-event devices\n");
243 ret = devfreq_resume_device(dmcfreq->devfreq);
245 dev_err(dev, "failed to resume the devfreq devices\n");
251 static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
252 rk3399_dmcfreq_resume);
254 static struct dram_timing *of_get_ddr_timings(struct device *dev,
255 struct device_node *np)
257 struct dram_timing *timing = NULL;
258 struct device_node *np_tim;
261 np_tim = of_parse_phandle(np, "ddr_timing", 0);
263 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
267 ret = of_property_read_u32(np_tim, "ddr3_speed_bin",
268 &timing->ddr3_speed_bin);
269 ret |= of_property_read_u32(np_tim, "pd_idle",
271 ret |= of_property_read_u32(np_tim, "sr_idle",
273 ret |= of_property_read_u32(np_tim, "sr_mc_gate_idle",
274 &timing->sr_mc_gate_idle);
275 ret |= of_property_read_u32(np_tim, "srpd_lite_idle",
276 &timing->srpd_lite_idle);
277 ret |= of_property_read_u32(np_tim, "standby_idle",
278 &timing->standby_idle);
279 ret |= of_property_read_u32(np_tim, "dram_dll_dis_freq",
280 &timing->dram_dll_dis_freq);
281 ret |= of_property_read_u32(np_tim, "phy_dll_dis_freq",
282 &timing->phy_dll_dis_freq);
283 ret |= of_property_read_u32(np_tim, "ddr3_odt_dis_freq",
284 &timing->ddr3_odt_dis_freq);
285 ret |= of_property_read_u32(np_tim, "ddr3_drv",
287 ret |= of_property_read_u32(np_tim, "ddr3_odt",
289 ret |= of_property_read_u32(np_tim, "phy_ddr3_ca_drv",
290 &timing->phy_ddr3_ca_drv);
291 ret |= of_property_read_u32(np_tim, "phy_ddr3_dq_drv",
292 &timing->phy_ddr3_dq_drv);
293 ret |= of_property_read_u32(np_tim, "phy_ddr3_odt",
294 &timing->phy_ddr3_odt);
295 ret |= of_property_read_u32(np_tim, "lpddr3_odt_dis_freq",
296 &timing->lpddr3_odt_dis_freq);
297 ret |= of_property_read_u32(np_tim, "lpddr3_drv",
298 &timing->lpddr3_drv);
299 ret |= of_property_read_u32(np_tim, "lpddr3_odt",
300 &timing->lpddr3_odt);
301 ret |= of_property_read_u32(np_tim, "phy_lpddr3_ca_drv",
302 &timing->phy_lpddr3_ca_drv);
303 ret |= of_property_read_u32(np_tim, "phy_lpddr3_dq_drv",
304 &timing->phy_lpddr3_dq_drv);
305 ret |= of_property_read_u32(np_tim, "phy_lpddr3_odt",
306 &timing->phy_lpddr3_odt);
307 ret |= of_property_read_u32(np_tim, "lpddr4_odt_dis_freq",
308 &timing->lpddr4_odt_dis_freq);
309 ret |= of_property_read_u32(np_tim, "lpddr4_drv",
310 &timing->lpddr4_drv);
311 ret |= of_property_read_u32(np_tim, "lpddr4_dq_odt",
312 &timing->lpddr4_dq_odt);
313 ret |= of_property_read_u32(np_tim, "lpddr4_ca_odt",
314 &timing->lpddr4_ca_odt);
315 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ca_drv",
316 &timing->phy_lpddr4_ca_drv);
317 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ck_cs_drv",
318 &timing->phy_lpddr4_ck_cs_drv);
319 ret |= of_property_read_u32(np_tim, "phy_lpddr4_dq_drv",
320 &timing->phy_lpddr4_dq_drv);
321 ret |= of_property_read_u32(np_tim, "phy_lpddr4_odt",
322 &timing->phy_lpddr4_odt);
324 devm_kfree(dev, timing);
333 devm_kfree(dev, timing);
340 static int of_get_opp_table(struct device *dev,
341 struct devfreq_dev_profile *devp)
345 unsigned long freq = 0;
346 struct dev_pm_opp *opp;
349 count = dev_pm_opp_get_opp_count(dev);
356 devp->freq_table = kmalloc_array(count, sizeof(devp->freq_table[0]),
358 if (!devp->freq_table)
362 for (i = 0; i < count; i++, freq++) {
363 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
367 devp->freq_table[i] = freq;
372 dev_warn(dev, "Unable to enumerate all OPPs (%d!=%d)\n",
379 static int rk3399_dmcfreq_probe(struct platform_device *pdev)
381 struct arm_smccc_res res;
382 struct device *dev = &pdev->dev;
383 struct device_node *np = pdev->dev.of_node;
384 struct rk3399_dmcfreq *data;
385 int ret, index, size;
387 struct devfreq_dev_profile *devp = &rk3399_devfreq_dmc_profile;
389 data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
393 mutex_init(&data->lock);
395 data->vdd_center = devm_regulator_get(dev, "center");
396 if (IS_ERR(data->vdd_center)) {
397 dev_err(dev, "Cannot get the regulator \"center\"\n");
398 return PTR_ERR(data->vdd_center);
401 data->dmc_clk = devm_clk_get(dev, "dmc_clk");
402 if (IS_ERR(data->dmc_clk)) {
403 dev_err(dev, "Cannot get the clk dmc_clk\n");
404 return PTR_ERR(data->dmc_clk);
407 data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
408 if (IS_ERR(data->edev))
409 return -EPROBE_DEFER;
411 ret = devfreq_event_enable_edev(data->edev);
413 dev_err(dev, "failed to enable devfreq-event devices\n");
418 * Get dram timing and pass it to arm trust firmware,
419 * the dram drvier in arm trust firmware will get these
420 * timing and to do dram initial.
422 data->timing = of_get_ddr_timings(dev, np);
424 timing = (uint32_t *)data->timing;
425 size = sizeof(struct dram_timing) / 4;
426 for (index = 0; index < size; index++) {
427 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
428 ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
431 dev_err(dev, "Failed to set dram param: %ld\n",
438 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
439 ROCKCHIP_SIP_CONFIG_DRAM_INIT,
443 * We add a devfreq driver to our parent since it has a device tree node
444 * with operating points.
446 if (dev_pm_opp_of_add_table(dev)) {
447 dev_err(dev, "Invalid operating-points in device tree.\n");
452 if (of_get_opp_table(dev, devp))
455 of_property_read_u32(np, "upthreshold",
456 &data->ondemand_data.upthreshold);
457 of_property_read_u32(np, "downdifferential",
458 &data->ondemand_data.downdifferential);
460 data->rate = clk_get_rate(data->dmc_clk);
461 data->volt = regulator_get_voltage(data->vdd_center);
463 devp->initial_freq = data->rate;
464 data->devfreq = devfreq_add_device(dev, devp,
466 &data->ondemand_data);
467 if (IS_ERR(data->devfreq))
468 return PTR_ERR(data->devfreq);
469 devm_devfreq_register_opp_notifier(dev, data->devfreq);
472 platform_set_drvdata(pdev, data);
474 if (vop_register_dmc())
475 dev_err(dev, "fail to register notify to vop.\n");
480 static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
481 { .compatible = "rockchip,rk3399-dmc" },
485 static struct platform_driver rk3399_dmcfreq_driver = {
486 .probe = rk3399_dmcfreq_probe,
488 .name = "rk3399-dmc-freq",
489 .pm = &rk3399_dmcfreq_pm,
490 .of_match_table = rk3399dmc_devfreq_of_match,
493 module_platform_driver(rk3399_dmcfreq_driver);
495 MODULE_LICENSE("GPL v2");
496 MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
497 MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");