drivers/devfreq/rockchip_dmc.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
   3  * Author: Lin Huang <hl@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <dt-bindings/clock/rockchip-ddr.h>
  16 #include <dt-bindings/display/rk_fb.h>
  17 #include <drm/drmP.h>
  18 #include <linux/arm-smccc.h>
  19 #include <linux/clk.h>
  20 #include <linux/delay.h>
  21 #include <linux/devfreq.h>
  22 #include <linux/devfreq-event.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/of.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_opp.h>
  28 #include <linux/regulator/consumer.h>
  29 #include <linux/rockchip/rockchip_sip.h>
  30 #include <linux/rwsem.h>
  31 #include <linux/slab.h>
  32 #include <linux/suspend.h>
  33
  34 #include <soc/rockchip/rkfb_dmc.h>
  35 #include <soc/rockchip/rockchip_dmc.h>
  36 #include <soc/rockchip/rockchip_sip.h>
  37 #include <soc/rockchip/scpi.h>
  38 #include <uapi/drm/drm_mode.h>
  39
  40 #define FIQ_INIT_HANDLER        (0x1)
  41 #define FIQ_CPU_TGT_BOOT        (0x0) /* to booting cpu */
  42 #define FIQ_NUM_FOR_DCF         (143) /* NA irq map to fiq for dcf */
  43 #define DTS_PAR_OFFSET          (4096)
  44
  45 struct init_params {
  46         /* these parameters, not use in RK322xh */
  47         u32 hz;
  48         u32 lcdc_type;
  49         u32 vop;
  50         u32 addr_mcu_el3;
  51         u32 vop_dclk_mode;
  52         /* if need, add parameter after */
  53 };
  54
  55 char *rk3288_dts_timing[] = {
  56         "ddr3_speed_bin",
  57         "pd_idle",
  58         "sr_idle",
  59         "auto_pd_dis_freq",
  60         "auto_sr_dis_freq",
  61         "ddr3_dll_dis_freq",
  62         "phy_dll_dis_freq",
  63         "ddr3_odt_dis_freq",
  64         "ddr3_drv",
  65         "ddr3_odt",
  66         "phy_ddr3_drv",
  67         "phy_ddr3_odt",
  68         "lpddr2_drv",
  69         "phy_lpddr2_drv",
  70         "lpddr3_odt_dis_freq",
  71         "lpddr3_drv",
  72         "lpddr3_odt",
  73         "phy_lpddr3_drv",
  74         "phy_lpddr3_odt"
  75 };
  76
  77 struct rk3288_ddr_dts_config_timing {
  78         unsigned int ddr3_speed_bin;
  79         unsigned int pd_idle;
  80         unsigned int sr_idle;
  81
  82         unsigned int auto_pd_dis_freq;
  83         unsigned int auto_sr_dis_freq;
  84         /* for ddr3 only */
  85         unsigned int ddr3_dll_dis_freq;
  86         unsigned int phy_dll_dis_freq;
  87
  88         unsigned int ddr3_odt_dis_freq;
  89         unsigned int ddr3_drv;
  90         unsigned int ddr3_odt;
  91         unsigned int phy_ddr3_drv;
  92         unsigned int phy_ddr3_odt;
  93
  94         unsigned int lpddr2_drv;
  95         unsigned int phy_lpddr2_drv;
  96         unsigned int lpddr3_odt_dis_freq;
  97         unsigned int lpddr3_drv;
  98         unsigned int lpddr3_odt;
  99         unsigned int phy_lpddr3_drv;
 100         unsigned int phy_lpddr3_odt;
 101
 102         unsigned int available;
 103 };
 104
 105 struct rk3368_dram_timing {
 106         u32 dram_spd_bin;
 107         u32 sr_idle;
 108         u32 pd_idle;
 109         u32 dram_dll_dis_freq;
 110         u32 phy_dll_dis_freq;
 111         u32 dram_odt_dis_freq;
 112         u32 phy_odt_dis_freq;
 113         u32 ddr3_drv;
 114         u32 ddr3_odt;
 115         u32 lpddr3_drv;
 116         u32 lpddr3_odt;
 117         u32 lpddr2_drv;
 118         u32 phy_clk_drv;
 119         u32 phy_cmd_drv;
 120         u32 phy_dqs_drv;
 121         u32 phy_odt;
 122 };
 123
 124 struct rk3399_dram_timing {
 125         unsigned int ddr3_speed_bin;
 126         unsigned int pd_idle;
 127         unsigned int sr_idle;
 128         unsigned int sr_mc_gate_idle;
 129         unsigned int srpd_lite_idle;
 130         unsigned int standby_idle;
 131         unsigned int dram_dll_dis_freq;
 132         unsigned int phy_dll_dis_freq;
 133         unsigned int ddr3_odt_dis_freq;
 134         unsigned int ddr3_drv;
 135         unsigned int ddr3_odt;
 136         unsigned int phy_ddr3_ca_drv;
 137         unsigned int phy_ddr3_dq_drv;
 138         unsigned int phy_ddr3_odt;
 139         unsigned int lpddr3_odt_dis_freq;
 140         unsigned int lpddr3_drv;
 141         unsigned int lpddr3_odt;
 142         unsigned int phy_lpddr3_ca_drv;
 143         unsigned int phy_lpddr3_dq_drv;
 144         unsigned int phy_lpddr3_odt;
 145         unsigned int lpddr4_odt_dis_freq;
 146         unsigned int lpddr4_drv;
 147         unsigned int lpddr4_dq_odt;
 148         unsigned int lpddr4_ca_odt;
 149         unsigned int phy_lpddr4_ca_drv;
 150         unsigned int phy_lpddr4_ck_cs_drv;
 151         unsigned int phy_lpddr4_dq_drv;
 152         unsigned int phy_lpddr4_odt;
 153 };
 154
 155 struct rockchip_dmcfreq {
 156         struct device *dev;
 157         struct devfreq *devfreq;
 158         struct devfreq_simple_ondemand_data ondemand_data;
 159         struct clk *dmc_clk;
 160         struct devfreq_event_dev *edev;
 161         struct mutex lock; /* scaling frequency lock */
 162         struct dram_timing *timing;
 163         struct regulator *vdd_center;
 164         unsigned long rate, target_rate;
 165         unsigned long volt, target_volt;
 166 };
 167
 168 static int rockchip_dmcfreq_target(struct device *dev, unsigned long *freq,
 169                                    u32 flags)
 170 {
 171         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 172         struct dev_pm_opp *opp;
 173         unsigned long old_clk_rate = dmcfreq->rate;
 174         unsigned long temp_rate, target_volt, target_rate;
 175         int err;
 176
 177         rcu_read_lock();
 178         opp = devfreq_recommended_opp(dev, freq, flags);
 179         if (IS_ERR(opp)) {
 180                 rcu_read_unlock();
 181                 return PTR_ERR(opp);
 182         }
 183
 184         temp_rate = dev_pm_opp_get_freq(opp);
 185         target_rate = clk_round_rate(dmcfreq->dmc_clk, temp_rate);
 186         if ((long)target_rate <= 0)
 187                 target_rate = temp_rate;
 188         target_volt = dev_pm_opp_get_voltage(opp);
 189
 190         rcu_read_unlock();
 191
 192         if (dmcfreq->rate == target_rate) {
 193                 if (dmcfreq->volt == target_volt)
 194                         return 0;
 195                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 196                                             INT_MAX);
 197                 if (err) {
 198                         dev_err(dev, "Cannot set voltage %lu uV\n",
 199                                 target_volt);
 200                         return err;
 201                 }
 202         }
 203
 204         mutex_lock(&dmcfreq->lock);
 205
 206         /*
 207          * If frequency scaling from low to high, adjust voltage first.
 208          * If frequency scaling from high to low, adjust frequency first.
 209          */
 210         if (old_clk_rate < target_rate) {
 211                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 212                                             INT_MAX);
 213                 if (err) {
 214                         dev_err(dev, "Cannot set voltage %lu uV\n",
 215                                 target_volt);
 216                         goto out;
 217                 }
 218         }
 219
 220         err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
 221         if (err) {
 222                 dev_err(dev, "Cannot set frequency %lu (%d)\n",
 223                         target_rate, err);
 224                 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
 225                                       INT_MAX);
 226                 goto out;
 227         }
 228
 229         /*
 230          * Check the dpll rate,
 231          * There only two result we will get,
 232          * 1. Ddr frequency scaling fail, we still get the old rate.
 233          * 2. Ddr frequency scaling sucessful, we get the rate we set.
 234          */
 235         dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
 236
 237         /* If get the incorrect rate, set voltage to old value. */
 238         if (dmcfreq->rate != target_rate) {
 239                 dev_err(dev, "Get wrong frequency, Request %lu, Current %lu\n",
 240                         target_rate, dmcfreq->rate);
 241                 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
 242                                       INT_MAX);
 243                 goto out;
 244         } else if (old_clk_rate > target_rate) {
 245                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 246                                             INT_MAX);
 247                 if (err) {
 248                         dev_err(dev, "Cannot set vol %lu uV\n", target_volt);
 249                         goto out;
 250                 }
 251         }
 252
 253         dmcfreq->volt = target_volt;
 254 out:
 255         mutex_unlock(&dmcfreq->lock);
 256         return err;
 257 }
 258
 259 static int rockchip_dmcfreq_get_dev_status(struct device *dev,
 260                                            struct devfreq_dev_status *stat)
 261 {
 262         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 263         struct devfreq_event_data edata;
 264         int ret = 0;
 265
 266         ret = devfreq_event_get_event(dmcfreq->edev, &edata);
 267         if (ret < 0)
 268                 return ret;
 269
 270         stat->current_frequency = dmcfreq->rate;
 271         stat->busy_time = edata.load_count;
 272         stat->total_time = edata.total_count;
 273
 274         return ret;
 275 }
 276
 277 static int rockchip_dmcfreq_get_cur_freq(struct device *dev,
 278                                          unsigned long *freq)
 279 {
 280         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 281
 282         *freq = dmcfreq->rate;
 283
 284         return 0;
 285 }
 286
 287 static struct devfreq_dev_profile rockchip_devfreq_dmc_profile = {
 288         .polling_ms     = 50,
 289         .target         = rockchip_dmcfreq_target,
 290         .get_dev_status = rockchip_dmcfreq_get_dev_status,
 291         .get_cur_freq   = rockchip_dmcfreq_get_cur_freq,
 292 };
 293
 294 static __maybe_unused int rockchip_dmcfreq_suspend(struct device *dev)
 295 {
 296         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 297         int ret = 0;
 298
 299         ret = devfreq_event_disable_edev(dmcfreq->edev);
 300         if (ret < 0) {
 301                 dev_err(dev, "failed to disable the devfreq-event devices\n");
 302                 return ret;
 303         }
 304
 305         ret = devfreq_suspend_device(dmcfreq->devfreq);
 306         if (ret < 0) {
 307                 dev_err(dev, "failed to suspend the devfreq devices\n");
 308                 return ret;
 309         }
 310
 311         return 0;
 312 }
 313
 314 static __maybe_unused int rockchip_dmcfreq_resume(struct device *dev)
 315 {
 316         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 317         int ret = 0;
 318
 319         ret = devfreq_event_enable_edev(dmcfreq->edev);
 320         if (ret < 0) {
 321                 dev_err(dev, "failed to enable the devfreq-event devices\n");
 322                 return ret;
 323         }
 324
 325         ret = devfreq_resume_device(dmcfreq->devfreq);
 326         if (ret < 0) {
 327                 dev_err(dev, "failed to resume the devfreq devices\n");
 328                 return ret;
 329         }
 330         return ret;
 331 }
 332
 333 static SIMPLE_DEV_PM_OPS(rockchip_dmcfreq_pm, rockchip_dmcfreq_suspend,
 334                          rockchip_dmcfreq_resume);
 335
 336 static int rockchip_dmcfreq_init_freq_table(struct device *dev,
 337                                             struct devfreq_dev_profile *devp)
 338 {
 339         int count;
 340         int i = 0;
 341         unsigned long freq = 0;
 342         struct dev_pm_opp *opp;
 343
 344         rcu_read_lock();
 345         count = dev_pm_opp_get_opp_count(dev);
 346         if (count < 0) {
 347                 rcu_read_unlock();
 348                 return count;
 349         }
 350         rcu_read_unlock();
 351
 352         devp->freq_table = kmalloc_array(count, sizeof(devp->freq_table[0]),
 353                                 GFP_KERNEL);
 354         if (!devp->freq_table)
 355                 return -ENOMEM;
 356
 357         rcu_read_lock();
 358         for (i = 0; i < count; i++, freq++) {
 359                 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
 360                 if (IS_ERR(opp))
 361                         break;
 362
 363                 devp->freq_table[i] = freq;
 364         }
 365         rcu_read_unlock();
 366
 367         if (count != i)
 368                 dev_warn(dev, "Unable to enumerate all OPPs (%d!=%d)\n",
 369                          count, i);
 370
 371         devp->max_state = i;
 372         return 0;
 373 }
 374
 375 static void of_get_rk3288_timings(struct device *dev,
 376                                   struct device_node *np, uint32_t *timing)
 377 {
 378         struct device_node *np_tim;
 379         u32 *p;
 380         struct rk3288_ddr_dts_config_timing *dts_timing;
 381         struct init_params *init_timing;
 382         int ret = 0;
 383         u32 i;
 384
 385         init_timing = (struct init_params *)timing;
 386
 387         if (of_property_read_u32(np, "vop-dclk-mode",
 388                                  &init_timing->vop_dclk_mode))
 389                 init_timing->vop_dclk_mode = 0;
 390
 391         p = timing + DTS_PAR_OFFSET / 4;
 392         np_tim = of_parse_phandle(np, "rockchip,ddr_timing", 0);
 393         if (!np_tim) {
 394                 ret = -EINVAL;
 395                 goto end;
 396         }
 397         for (i = 0; i < ARRAY_SIZE(rk3288_dts_timing); i++) {
 398                 ret |= of_property_read_u32(np_tim, rk3288_dts_timing[i],
 399                                         p + i);
 400         }
 401 end:
 402         dts_timing =
 403                 (struct rk3288_ddr_dts_config_timing *)(timing +
 404                                                         DTS_PAR_OFFSET / 4);
 405         if (!ret) {
 406                 dts_timing->available = 1;
 407         } else {
 408                 dts_timing->available = 0;
 409                 dev_err(dev, "of_get_ddr_timings: fail\n");
 410         }
 411
 412         of_node_put(np_tim);
 413 }
 414
 415 static struct rk3368_dram_timing *of_get_rk3368_timings(struct device *dev,
 416                                                         struct device_node *np)
 417 {
 418         struct rk3368_dram_timing *timing = NULL;
 419         struct device_node *np_tim;
 420         int ret;
 421
 422         np_tim = of_parse_phandle(np, "ddr_timing", 0);
 423         if (np_tim) {
 424                 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
 425                 if (!timing)
 426                         goto err;
 427
 428                 ret |= of_property_read_u32(np_tim, "dram_spd_bin",
 429                                             &timing->dram_spd_bin);
 430                 ret |= of_property_read_u32(np_tim, "sr_idle",
 431                                             &timing->sr_idle);
 432                 ret |= of_property_read_u32(np_tim, "pd_idle",
 433                                             &timing->pd_idle);
 434                 ret |= of_property_read_u32(np_tim, "dram_dll_disb_freq",
 435                                             &timing->dram_dll_dis_freq);
 436                 ret |= of_property_read_u32(np_tim, "phy_dll_disb_freq",
 437                                             &timing->phy_dll_dis_freq);
 438                 ret |= of_property_read_u32(np_tim, "dram_odt_disb_freq",
 439                                             &timing->dram_odt_dis_freq);
 440                 ret |= of_property_read_u32(np_tim, "phy_odt_disb_freq",
 441                                             &timing->phy_odt_dis_freq);
 442                 ret |= of_property_read_u32(np_tim, "ddr3_drv",
 443                                             &timing->ddr3_drv);
 444                 ret |= of_property_read_u32(np_tim, "ddr3_odt",
 445                                             &timing->ddr3_odt);
 446                 ret |= of_property_read_u32(np_tim, "lpddr3_drv",
 447                                             &timing->lpddr3_drv);
 448                 ret |= of_property_read_u32(np_tim, "lpddr3_odt",
 449                                             &timing->lpddr3_odt);
 450                 ret |= of_property_read_u32(np_tim, "lpddr2_drv",
 451                                             &timing->lpddr2_drv);
 452                 ret |= of_property_read_u32(np_tim, "phy_clk_drv",
 453                                             &timing->phy_clk_drv);
 454                 ret |= of_property_read_u32(np_tim, "phy_cmd_drv",
 455                                             &timing->phy_cmd_drv);
 456                 ret |= of_property_read_u32(np_tim, "phy_dqs_drv",
 457                                             &timing->phy_dqs_drv);
 458                 ret |= of_property_read_u32(np_tim, "phy_odt",
 459                                             &timing->phy_odt);
 460                 if (ret) {
 461                         devm_kfree(dev, timing);
 462                         goto err;
 463                 }
 464                 of_node_put(np_tim);
 465                 return timing;
 466         }
 467
 468 err:
 469         if (timing) {
 470                 devm_kfree(dev, timing);
 471                 timing = NULL;
 472         }
 473         of_node_put(np_tim);
 474         return timing;
 475 }
 476
 477 static int rk_drm_get_lcdc_type(void)
 478 {
 479         struct drm_device *drm;
 480         u32 lcdc_type = 0;
 481
 482         drm = drm_device_get_by_name("rockchip");
 483         if (drm) {
 484                 struct drm_connector *conn;
 485
 486                 mutex_lock(&drm->mode_config.mutex);
 487                 drm_for_each_connector(conn, drm) {
 488                         if (conn->encoder) {
 489                                 lcdc_type = conn->connector_type;
 490                                 break;
 491                         }
 492                 }
 493                 mutex_unlock(&drm->mode_config.mutex);
 494         }
 495         switch (lcdc_type) {
 496         case DRM_MODE_CONNECTOR_LVDS:
 497                 lcdc_type = SCREEN_LVDS;
 498                 break;
 499         case DRM_MODE_CONNECTOR_DisplayPort:
 500                 lcdc_type = SCREEN_DP;
 501                 break;
 502         case DRM_MODE_CONNECTOR_HDMIA:
 503         case DRM_MODE_CONNECTOR_HDMIB:
 504                 lcdc_type = SCREEN_HDMI;
 505                 break;
 506         case DRM_MODE_CONNECTOR_TV:
 507                 lcdc_type = SCREEN_TVOUT;
 508                 break;
 509         case DRM_MODE_CONNECTOR_eDP:
 510                 lcdc_type = SCREEN_EDP;
 511                 break;
 512         case DRM_MODE_CONNECTOR_DSI:
 513                 lcdc_type = SCREEN_MIPI;
 514                 break;
 515         default:
 516                 lcdc_type = SCREEN_NULL;
 517                 break;
 518         }
 519
 520         return lcdc_type;
 521 }
 522
 523 static int rk3288_dmc_init(struct platform_device *pdev)
 524 {
 525         struct device *dev = &pdev->dev;
 526         struct clk *pclk_phy, *pclk_upctl, *dmc_clk;
 527         struct arm_smccc_res res;
 528         struct init_params *init_param;
 529         struct drm_device *drm = drm_device_get_by_name("rockchip");
 530         int ret;
 531
 532         if (!drm) {
 533                 dev_err(dev, "Get drm_device fail\n");
 534                 return -EPROBE_DEFER;
 535         }
 536
 537         dmc_clk = devm_clk_get(dev, "dmc_clk");
 538         if (IS_ERR(dmc_clk)) {
 539                 dev_err(dev, "Cannot get the clk dmc_clk\n");
 540                 return PTR_ERR(pclk_phy);
 541         };
 542         ret = clk_prepare_enable(dmc_clk);
 543         if (ret < 0) {
 544                 dev_err(dev, "failed to prepare/enable dmc_clk\n");
 545                 return ret;
 546         }
 547
 548         pclk_phy = devm_clk_get(dev, "pclk_phy0");
 549         if (IS_ERR(pclk_phy)) {
 550                 dev_err(dev, "Cannot get the clk pclk_phy0\n");
 551                 return PTR_ERR(pclk_phy);
 552         };
 553         ret = clk_prepare_enable(pclk_phy);
 554         if (ret < 0) {
 555                 dev_err(dev, "failed to prepare/enable pclk_phy0\n");
 556                 return ret;
 557         }
 558         pclk_upctl = devm_clk_get(dev, "pclk_upctl0");
 559         if (IS_ERR(pclk_phy)) {
 560                 dev_err(dev, "Cannot get the clk pclk_upctl0\n");
 561                 return PTR_ERR(pclk_upctl);
 562         };
 563         ret = clk_prepare_enable(pclk_upctl);
 564         if (ret < 0) {
 565                 dev_err(dev, "failed to prepare/enable pclk_upctl1\n");
 566                 return ret;
 567         }
 568
 569         pclk_phy = devm_clk_get(dev, "pclk_phy1");
 570         if (IS_ERR(pclk_phy)) {
 571                 dev_err(dev, "Cannot get the clk pclk_phy1\n");
 572                 return PTR_ERR(pclk_phy);
 573         };
 574         ret = clk_prepare_enable(pclk_phy);
 575         if (ret < 0) {
 576                 dev_err(dev, "failed to prepare/enable pclk_phy1\n");
 577                 return ret;
 578         }
 579         pclk_upctl = devm_clk_get(dev, "pclk_upctl1");
 580         if (IS_ERR(pclk_phy)) {
 581                 dev_err(dev, "Cannot get the clk pclk_upctl1\n");
 582                 return PTR_ERR(pclk_upctl);
 583         };
 584         ret = clk_prepare_enable(pclk_upctl);
 585         if (ret < 0) {
 586                 dev_err(dev, "failed to prepare/enable pclk_upctl1\n");
 587                 return ret;
 588         }
 589
 590         res = sip_smc_request_share_mem(DIV_ROUND_UP(sizeof(
 591                                         struct rk3288_ddr_dts_config_timing),
 592                                         4096) + 1, SHARE_PAGE_TYPE_DDR);
 593         if (res.a0) {
 594                 dev_err(&pdev->dev, "no ATF memory for init\n");
 595                 return -ENOMEM;
 596         }
 597
 598         init_param = (struct init_params *)res.a1;
 599         of_get_rk3288_timings(&pdev->dev, pdev->dev.of_node,
 600                               (uint32_t *)init_param);
 601
 602         init_param->hz = 0;
 603         init_param->lcdc_type = rk_drm_get_lcdc_type();
 604         res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
 605                            ROCKCHIP_SIP_CONFIG_DRAM_INIT);
 606
 607         if (res.a0) {
 608                 dev_err(&pdev->dev, "rockchip_sip_config_dram_init error:%lx\n",
 609                         res.a0);
 610                 return -ENOMEM;
 611         }
 612
 613         return 0;
 614 }
 615
 616 static int rk3368_dmc_init(struct platform_device *pdev)
 617 {
 618         struct device *dev = &pdev->dev;
 619         struct device_node *np = pdev->dev.of_node;
 620         struct arm_smccc_res res;
 621         struct rk3368_dram_timing *dram_timing;
 622         struct clk *pclk_phy, *pclk_upctl;
 623         int ret;
 624         u32 dram_spd_bin;
 625         u32 addr_mcu_el3;
 626         u32 dclk_mode;
 627         u32 lcdc_type;
 628
 629         pclk_phy = devm_clk_get(dev, "pclk_phy");
 630         if (IS_ERR(pclk_phy)) {
 631                 dev_err(dev, "Cannot get the clk pclk_phy\n");
 632                 return PTR_ERR(pclk_phy);
 633         };
 634         ret = clk_prepare_enable(pclk_phy);
 635         if (ret < 0) {
 636                 dev_err(dev, "failed to prepare/enable pclk_phy\n");
 637                 return ret;
 638         }
 639         pclk_upctl = devm_clk_get(dev, "pclk_upctl");
 640         if (IS_ERR(pclk_phy)) {
 641                 dev_err(dev, "Cannot get the clk pclk_upctl\n");
 642                 return PTR_ERR(pclk_upctl);
 643         };
 644         ret = clk_prepare_enable(pclk_upctl);
 645         if (ret < 0) {
 646                 dev_err(dev, "failed to prepare/enable pclk_upctl\n");
 647                 return ret;
 648         }
 649
 650         /*
 651          * Get dram timing and pass it to arm trust firmware,
 652          * the dram drvier in arm trust firmware will get these
 653          * timing and to do dram initial.
 654          */
 655         dram_timing = of_get_rk3368_timings(dev, np);
 656         if (dram_timing) {
 657                 dram_spd_bin = dram_timing->dram_spd_bin;
 658                 if (scpi_ddr_send_timing((u32 *)dram_timing,
 659                                          sizeof(struct rk3368_dram_timing)))
 660                         dev_err(dev, "send ddr timing timeout\n");
 661         } else {
 662                 dev_err(dev, "get ddr timing from dts error\n");
 663                 dram_spd_bin = DDR3_DEFAULT;
 664         }
 665
 666         res = sip_smc_mcu_el3fiq(FIQ_INIT_HANDLER,
 667                                  FIQ_NUM_FOR_DCF,
 668                                  FIQ_CPU_TGT_BOOT);
 669         if ((res.a0) || (res.a1 == 0) || (res.a1 > 0x80000))
 670                 dev_err(dev, "Trust version error, pls check trust version\n");
 671         addr_mcu_el3 = res.a1;
 672
 673         if (of_property_read_u32(np, "vop-dclk-mode", &dclk_mode) == 0)
 674                 scpi_ddr_dclk_mode(dclk_mode);
 675
 676         lcdc_type = 7;
 677
 678         if (scpi_ddr_init(dram_spd_bin, 0, lcdc_type,
 679                           addr_mcu_el3))
 680                 dev_err(dev, "ddr init error\n");
 681         else
 682                 dev_dbg(dev, ("%s out\n"), __func__);
 683
 684         return 0;
 685 }
 686
 687 static struct rk3399_dram_timing *of_get_rk3399_timings(struct device *dev,
 688                                                         struct device_node *np)
 689 {
 690         struct rk3399_dram_timing *timing = NULL;
 691         struct device_node *np_tim;
 692         int ret;
 693
 694         np_tim = of_parse_phandle(np, "ddr_timing", 0);
 695         if (np_tim) {
 696                 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
 697                 if (!timing)
 698                         goto err;
 699
 700                 ret = of_property_read_u32(np_tim, "ddr3_speed_bin",
 701                                            &timing->ddr3_speed_bin);
 702                 ret |= of_property_read_u32(np_tim, "pd_idle",
 703                                             &timing->pd_idle);
 704                 ret |= of_property_read_u32(np_tim, "sr_idle",
 705                                             &timing->sr_idle);
 706                 ret |= of_property_read_u32(np_tim, "sr_mc_gate_idle",
 707                                             &timing->sr_mc_gate_idle);
 708                 ret |= of_property_read_u32(np_tim, "srpd_lite_idle",
 709                                             &timing->srpd_lite_idle);
 710                 ret |= of_property_read_u32(np_tim, "standby_idle",
 711                                             &timing->standby_idle);
 712                 ret |= of_property_read_u32(np_tim, "dram_dll_dis_freq",
 713                                             &timing->dram_dll_dis_freq);
 714                 ret |= of_property_read_u32(np_tim, "phy_dll_dis_freq",
 715                                             &timing->phy_dll_dis_freq);
 716                 ret |= of_property_read_u32(np_tim, "ddr3_odt_dis_freq",
 717                                             &timing->ddr3_odt_dis_freq);
 718                 ret |= of_property_read_u32(np_tim, "ddr3_drv",
 719                                             &timing->ddr3_drv);
 720                 ret |= of_property_read_u32(np_tim, "ddr3_odt",
 721                                             &timing->ddr3_odt);
 722                 ret |= of_property_read_u32(np_tim, "phy_ddr3_ca_drv",
 723                                             &timing->phy_ddr3_ca_drv);
 724                 ret |= of_property_read_u32(np_tim, "phy_ddr3_dq_drv",
 725                                             &timing->phy_ddr3_dq_drv);
 726                 ret |= of_property_read_u32(np_tim, "phy_ddr3_odt",
 727                                             &timing->phy_ddr3_odt);
 728                 ret |= of_property_read_u32(np_tim, "lpddr3_odt_dis_freq",
 729                                             &timing->lpddr3_odt_dis_freq);
 730                 ret |= of_property_read_u32(np_tim, "lpddr3_drv",
 731                                             &timing->lpddr3_drv);
 732                 ret |= of_property_read_u32(np_tim, "lpddr3_odt",
 733                                             &timing->lpddr3_odt);
 734                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_ca_drv",
 735                                             &timing->phy_lpddr3_ca_drv);
 736                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_dq_drv",
 737                                             &timing->phy_lpddr3_dq_drv);
 738                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_odt",
 739                                             &timing->phy_lpddr3_odt);
 740                 ret |= of_property_read_u32(np_tim, "lpddr4_odt_dis_freq",
 741                                             &timing->lpddr4_odt_dis_freq);
 742                 ret |= of_property_read_u32(np_tim, "lpddr4_drv",
 743                                             &timing->lpddr4_drv);
 744                 ret |= of_property_read_u32(np_tim, "lpddr4_dq_odt",
 745                                             &timing->lpddr4_dq_odt);
 746                 ret |= of_property_read_u32(np_tim, "lpddr4_ca_odt",
 747                                             &timing->lpddr4_ca_odt);
 748                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ca_drv",
 749                                             &timing->phy_lpddr4_ca_drv);
 750                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ck_cs_drv",
 751                                             &timing->phy_lpddr4_ck_cs_drv);
 752                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_dq_drv",
 753                                             &timing->phy_lpddr4_dq_drv);
 754                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_odt",
 755                                             &timing->phy_lpddr4_odt);
 756                 if (ret) {
 757                         devm_kfree(dev, timing);
 758                         goto err;
 759                 }
 760                 of_node_put(np_tim);
 761                 return timing;
 762         }
 763
 764 err:
 765         if (timing) {
 766                 devm_kfree(dev, timing);
 767                 timing = NULL;
 768         }
 769         of_node_put(np_tim);
 770         return timing;
 771 }
 772
 773 static int rk3399_dmc_init(struct platform_device *pdev)
 774 {
 775         struct device *dev = &pdev->dev;
 776         struct device_node *np = pdev->dev.of_node;
 777         struct arm_smccc_res res;
 778         struct rk3399_dram_timing *dram_timing;
 779         int index, size;
 780         u32 *timing;
 781
 782         /*
 783          * Get dram timing and pass it to arm trust firmware,
 784          * the dram drvier in arm trust firmware will get these
 785          * timing and to do dram initial.
 786          */
 787         dram_timing = of_get_rk3399_timings(dev, np);
 788         if (dram_timing) {
 789                 timing = (u32 *)dram_timing;
 790                 size = sizeof(struct rk3399_dram_timing) / 4;
 791                 for (index = 0; index < size; index++) {
 792                         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
 793                                       ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
 794                                       0, 0, 0, 0, &res);
 795                         if (res.a0) {
 796                                 dev_err(dev, "Failed to set dram param: %ld\n",
 797                                         res.a0);
 798                                 return -EINVAL;
 799                         }
 800                 }
 801         }
 802
 803         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
 804                       ROCKCHIP_SIP_CONFIG_DRAM_INIT,
 805                       0, 0, 0, 0, &res);
 806
 807         return 0;
 808 }
 809
 810 static const struct of_device_id rockchip_dmcfreq_of_match[] = {
 811         { .compatible = "rockchip,rk3288-dmc", .data = rk3288_dmc_init },
 812         { .compatible = "rockchip,rk3368-dmc", .data = rk3368_dmc_init },
 813         { .compatible = "rockchip,rk3399-dmc", .data = rk3399_dmc_init },
 814         { },
 815 };
 816 MODULE_DEVICE_TABLE(of, rockchip_dmcfreq_of_match);
 817
 818 static int rockchip_dmcfreq_probe(struct platform_device *pdev)
 819 {
 820         struct device *dev = &pdev->dev;
 821         struct device_node *np = pdev->dev.of_node;
 822         struct rockchip_dmcfreq *data;
 823         struct devfreq_dev_profile *devp = &rockchip_devfreq_dmc_profile;
 824         const struct of_device_id *match;
 825         int (*init)(struct platform_device *pdev,
 826                     struct rockchip_dmcfreq *data);
 827         int ret;
 828
 829         data = devm_kzalloc(dev, sizeof(struct rockchip_dmcfreq), GFP_KERNEL);
 830         if (!data)
 831                 return -ENOMEM;
 832
 833         mutex_init(&data->lock);
 834
 835         data->vdd_center = devm_regulator_get(dev, "center");
 836         if (IS_ERR(data->vdd_center)) {
 837                 dev_err(dev, "Cannot get the regulator \"center\"\n");
 838                 return PTR_ERR(data->vdd_center);
 839         }
 840
 841         data->dmc_clk = devm_clk_get(dev, "dmc_clk");
 842         if (IS_ERR(data->dmc_clk)) {
 843                 dev_err(dev, "Cannot get the clk dmc_clk\n");
 844                 return PTR_ERR(data->dmc_clk);
 845         };
 846
 847         data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
 848         if (IS_ERR(data->edev))
 849                 return -EPROBE_DEFER;
 850
 851         ret = devfreq_event_enable_edev(data->edev);
 852         if (ret < 0) {
 853                 dev_err(dev, "failed to enable devfreq-event devices\n");
 854                 return ret;
 855         }
 856
 857         match = of_match_node(rockchip_dmcfreq_of_match, pdev->dev.of_node);
 858         if (match) {
 859                 init = match->data;
 860                 if (init) {
 861                         ret = init(pdev, data);
 862                         if (ret)
 863                                 return ret;
 864                 }
 865         }
 866
 867         /*
 868          * We add a devfreq driver to our parent since it has a device tree node
 869          * with operating points.
 870          */
 871         if (dev_pm_opp_of_add_table(dev)) {
 872                 dev_err(dev, "Invalid operating-points in device tree.\n");
 873                 return -EINVAL;
 874         }
 875
 876         if (rockchip_dmcfreq_init_freq_table(dev, devp))
 877                 return -EFAULT;
 878
 879         of_property_read_u32(np, "upthreshold",
 880                              &data->ondemand_data.upthreshold);
 881         of_property_read_u32(np, "downdifferential",
 882                              &data->ondemand_data.downdifferential);
 883
 884         data->rate = clk_get_rate(data->dmc_clk);
 885         data->volt = regulator_get_voltage(data->vdd_center);
 886
 887         devp->initial_freq = data->rate;
 888         data->devfreq = devm_devfreq_add_device(dev, devp,
 889                                            "simple_ondemand",
 890                                            &data->ondemand_data);
 891         if (IS_ERR(data->devfreq))
 892                 return PTR_ERR(data->devfreq);
 893         devm_devfreq_register_opp_notifier(dev, data->devfreq);
 894
 895         data->devfreq->min_freq = devp->freq_table[0];
 896         data->devfreq->max_freq =
 897                 devp->freq_table[devp->max_state ? devp->max_state - 1 : 0];
 898
 899         data->dev = dev;
 900         platform_set_drvdata(pdev, data);
 901
 902         if (rockchip_drm_register_notifier_to_dmc(data->devfreq))
 903                 dev_err(dev, "drm fail to register notifier to dmc\n");
 904
 905         if (rockchip_pm_register_notify_to_dmc(data->devfreq))
 906                 dev_err(dev, "pd fail to register notify to dmc\n");
 907
 908         if (vop_register_dmc())
 909                 dev_err(dev, "fail to register notify to vop.\n");
 910
 911         return 0;
 912 }
 913
 914 static struct platform_driver rockchip_dmcfreq_driver = {
 915         .probe  = rockchip_dmcfreq_probe,
 916         .driver = {
 917                 .name   = "rockchip-dmc",
 918                 .pm     = &rockchip_dmcfreq_pm,
 919                 .of_match_table = rockchip_dmcfreq_of_match,
 920         },
 921 };
 922 module_platform_driver(rockchip_dmcfreq_driver);
 923
 924 MODULE_LICENSE("GPL v2");
 925 MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
 926 MODULE_DESCRIPTION("rockchip dmcfreq driver with devfreq framework");