drivers/devfreq/rockchip_dmc.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
   3  * Author: Lin Huang <hl@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <dt-bindings/clock/rockchip-ddr.h>
  16 #include <dt-bindings/display/rk_fb.h>
  17 #include <dt-bindings/soc/rockchip-system-status.h>
  18 #include <drm/drmP.h>
  19 #include <linux/arm-smccc.h>
  20 #include <linux/clk.h>
  21 #include <linux/cpu.h>
  22 #include <linux/cpufreq.h>
  23 #include <linux/delay.h>
  24 #include <linux/devfreq.h>
  25 #include <linux/devfreq-event.h>
  26 #include <linux/fb.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/module.h>
  29 #include <linux/of.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/pm_opp.h>
  32 #include <linux/reboot.h>
  33 #include <linux/regulator/consumer.h>
  34 #include <linux/rockchip/rockchip_sip.h>
  35 #include <linux/rwsem.h>
  36 #include <linux/slab.h>
  37 #include <linux/string.h>
  38 #include <linux/suspend.h>
  39
  40 #include <soc/rockchip/rkfb_dmc.h>
  41 #include <soc/rockchip/rockchip_dmc.h>
  42 #include <soc/rockchip/rockchip_sip.h>
  43 #include <soc/rockchip/rockchip-system-status.h>
  44 #include <soc/rockchip/scpi.h>
  45 #include <uapi/drm/drm_mode.h>
  46
  47 #include "governor.h"
  48
  49 #define system_status_to_dmcfreq(nb) container_of(nb, struct rockchip_dmcfreq, \
  50                                                   system_status_nb)
  51 #define reboot_to_dmcfreq(nb) container_of(nb, struct rockchip_dmcfreq, \
  52                                            reboot_nb)
  53
  54 #define VIDEO_1080P_SIZE        (1920 * 1080)
  55 #define FIQ_INIT_HANDLER        (0x1)
  56 #define FIQ_CPU_TGT_BOOT        (0x0) /* to booting cpu */
  57 #define FIQ_NUM_FOR_DCF         (143) /* NA irq map to fiq for dcf */
  58 #define DTS_PAR_OFFSET          (4096)
  59
  60 struct video_info {
  61         unsigned int width;
  62         unsigned int height;
  63         unsigned int ishevc;
  64         unsigned int videoFramerate;
  65         unsigned int streamBitrate;
  66         struct list_head node;
  67 };
  68
  69 struct share_params {
  70         u32 hz;
  71         u32 lcdc_type;
  72         u32 vop;
  73         u32 vop_dclk_mode;
  74         u32 sr_idle_en;
  75         u32 addr_mcu_el3;
  76         /*
  77          * 1: need to wait flag1
  78          * 0: never wait flag1
  79          */
  80         u32 wait_flag1;
  81         /*
  82          * 1: need to wait flag1
  83          * 0: never wait flag1
  84          */
  85         u32 wait_flag0;
  86          /* if need, add parameter after */
  87 };
  88
  89 static struct share_params *ddr_psci_param;
  90
  91 char *rk3288_dts_timing[] = {
  92         "ddr3_speed_bin",
  93         "pd_idle",
  94         "sr_idle",
  95
  96         "auto_pd_dis_freq",
  97         "auto_sr_dis_freq",
  98         /* for ddr3 only */
  99         "ddr3_dll_dis_freq",
 100         "phy_dll_dis_freq",
 101
 102         "ddr3_odt_dis_freq",
 103         "phy_ddr3_odt_dis_freq",
 104         "ddr3_drv",
 105         "ddr3_odt",
 106         "phy_ddr3_drv",
 107         "phy_ddr3_odt",
 108
 109         "lpddr2_drv",
 110         "phy_lpddr2_drv",
 111
 112         "lpddr3_odt_dis_freq",
 113         "phy_lpddr3_odt_dis_freq",
 114         "lpddr3_drv",
 115         "lpddr3_odt",
 116         "phy_lpddr3_drv",
 117         "phy_lpddr3_odt"
 118 };
 119
 120 struct rk3288_ddr_dts_config_timing {
 121         unsigned int ddr3_speed_bin;
 122         unsigned int pd_idle;
 123         unsigned int sr_idle;
 124
 125         unsigned int auto_pd_dis_freq;
 126         unsigned int auto_sr_dis_freq;
 127         /* for ddr3 only */
 128         unsigned int ddr3_dll_dis_freq;
 129         unsigned int phy_dll_dis_freq;
 130
 131         unsigned int ddr3_odt_dis_freq;
 132         unsigned int phy_ddr3_odt_dis_freq;
 133         unsigned int ddr3_drv;
 134         unsigned int ddr3_odt;
 135         unsigned int phy_ddr3_drv;
 136         unsigned int phy_ddr3_odt;
 137
 138         unsigned int lpddr2_drv;
 139         unsigned int phy_lpddr2_drv;
 140
 141         unsigned int lpddr3_odt_dis_freq;
 142         unsigned int phy_lpddr3_odt_dis_freq;
 143         unsigned int lpddr3_drv;
 144         unsigned int lpddr3_odt;
 145         unsigned int phy_lpddr3_drv;
 146         unsigned int phy_lpddr3_odt;
 147
 148         unsigned int available;
 149 };
 150
 151 struct rk3368_dram_timing {
 152         u32 dram_spd_bin;
 153         u32 sr_idle;
 154         u32 pd_idle;
 155         u32 dram_dll_dis_freq;
 156         u32 phy_dll_dis_freq;
 157         u32 dram_odt_dis_freq;
 158         u32 phy_odt_dis_freq;
 159         u32 ddr3_drv;
 160         u32 ddr3_odt;
 161         u32 lpddr3_drv;
 162         u32 lpddr3_odt;
 163         u32 lpddr2_drv;
 164         u32 phy_clk_drv;
 165         u32 phy_cmd_drv;
 166         u32 phy_dqs_drv;
 167         u32 phy_odt;
 168 };
 169
 170 struct rk3399_dram_timing {
 171         unsigned int ddr3_speed_bin;
 172         unsigned int pd_idle;
 173         unsigned int sr_idle;
 174         unsigned int sr_mc_gate_idle;
 175         unsigned int srpd_lite_idle;
 176         unsigned int standby_idle;
 177         unsigned int dram_dll_dis_freq;
 178         unsigned int phy_dll_dis_freq;
 179         unsigned int ddr3_odt_dis_freq;
 180         unsigned int ddr3_drv;
 181         unsigned int ddr3_odt;
 182         unsigned int phy_ddr3_ca_drv;
 183         unsigned int phy_ddr3_dq_drv;
 184         unsigned int phy_ddr3_odt;
 185         unsigned int lpddr3_odt_dis_freq;
 186         unsigned int lpddr3_drv;
 187         unsigned int lpddr3_odt;
 188         unsigned int phy_lpddr3_ca_drv;
 189         unsigned int phy_lpddr3_dq_drv;
 190         unsigned int phy_lpddr3_odt;
 191         unsigned int lpddr4_odt_dis_freq;
 192         unsigned int lpddr4_drv;
 193         unsigned int lpddr4_dq_odt;
 194         unsigned int lpddr4_ca_odt;
 195         unsigned int phy_lpddr4_ca_drv;
 196         unsigned int phy_lpddr4_ck_cs_drv;
 197         unsigned int phy_lpddr4_dq_drv;
 198         unsigned int phy_lpddr4_odt;
 199 };
 200
 201 struct rockchip_dmcfreq {
 202         struct device *dev;
 203         struct devfreq *devfreq;
 204         struct devfreq_simple_ondemand_data ondemand_data;
 205         struct clk *dmc_clk;
 206         struct devfreq_event_dev *edev;
 207         struct mutex lock; /* scaling frequency lock */
 208         struct dram_timing *timing;
 209         struct regulator *vdd_center;
 210         struct notifier_block system_status_nb;
 211         struct notifier_block reboot_nb;
 212         struct notifier_block fb_nb;
 213         struct list_head video_info_list;
 214
 215         unsigned long rate, target_rate;
 216         unsigned long volt, target_volt;
 217
 218         unsigned long normal_rate;
 219         unsigned long video_1080p_rate;
 220         unsigned long video_4k_rate;
 221         unsigned long video_4k_10b_rate;
 222         unsigned long performance_rate;
 223         unsigned long dualview_rate;
 224         unsigned long hdmi_rate;
 225         unsigned long idle_rate;
 226         unsigned long suspend_rate;
 227         unsigned long reboot_rate;
 228         unsigned long boost_rate;
 229         unsigned long isp_rate;
 230         unsigned long low_power_rate;
 231
 232         unsigned int min_cpu_freq;
 233         unsigned int auto_min_freq;
 234         unsigned int auto_freq_en;
 235         unsigned int aotu_self_refresh;
 236
 237         int (*set_auto_self_refresh)(u32 en);
 238 };
 239
 240 static int rockchip_dmcfreq_target(struct device *dev, unsigned long *freq,
 241                                    u32 flags)
 242 {
 243         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 244         struct dev_pm_opp *opp;
 245         struct cpufreq_policy *policy;
 246         unsigned long old_clk_rate = dmcfreq->rate;
 247         unsigned long temp_rate, target_volt, target_rate;
 248         unsigned int cpu_cur, cpufreq_cur;
 249         int err;
 250
 251         rcu_read_lock();
 252         opp = devfreq_recommended_opp(dev, freq, flags);
 253         if (IS_ERR(opp)) {
 254                 rcu_read_unlock();
 255                 return PTR_ERR(opp);
 256         }
 257
 258         temp_rate = dev_pm_opp_get_freq(opp);
 259         target_rate = clk_round_rate(dmcfreq->dmc_clk, temp_rate);
 260         if ((long)target_rate <= 0)
 261                 target_rate = temp_rate;
 262         target_volt = dev_pm_opp_get_voltage(opp);
 263
 264         rcu_read_unlock();
 265
 266         if (dmcfreq->rate == target_rate) {
 267                 if (dmcfreq->volt == target_volt)
 268                         return 0;
 269                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 270                                             INT_MAX);
 271                 if (err) {
 272                         dev_err(dev, "Cannot set voltage %lu uV\n",
 273                                 target_volt);
 274                         return err;
 275                 }
 276         }
 277
 278         mutex_lock(&dmcfreq->lock);
 279
 280         /*
 281          * We need to prevent cpu hotplug from happening while a dmc freq rate
 282          * change is happening.
 283          *
 284          * Do this before taking the policy rwsem to avoid deadlocks between the
 285          * mutex that is locked/unlocked in cpu_hotplug_disable/enable. And it
 286          * can also avoid deadlocks between the mutex that is locked/unlocked
 287          * in get/put_online_cpus (such as store_scaling_max_freq()).
 288          */
 289         get_online_cpus();
 290
 291         /*
 292          * Go to specified cpufreq and block other cpufreq changes since
 293          * set_rate needs to complete during vblank.
 294          */
 295         cpu_cur = smp_processor_id();
 296         policy = cpufreq_cpu_get(cpu_cur);
 297         if (!policy) {
 298                 dev_err(dev, "cpu%d policy NULL\n", cpu_cur);
 299                 goto cpufreq;
 300         }
 301         down_write(&policy->rwsem);
 302         cpufreq_cur = cpufreq_quick_get(cpu_cur);
 303
 304         /* If we're thermally throttled; don't change; */
 305         if (dmcfreq->min_cpu_freq && cpufreq_cur < dmcfreq->min_cpu_freq) {
 306                 if (policy->max >= dmcfreq->min_cpu_freq)
 307                         __cpufreq_driver_target(policy, dmcfreq->min_cpu_freq,
 308                                                 CPUFREQ_RELATION_L);
 309                 else
 310                         dev_dbg(dev, "CPU may too slow for DMC (%d MHz)\n",
 311                                 policy->max);
 312         }
 313
 314         /*
 315          * If frequency scaling from low to high, adjust voltage first.
 316          * If frequency scaling from high to low, adjust frequency first.
 317          */
 318         if (old_clk_rate < target_rate) {
 319                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 320                                             INT_MAX);
 321                 if (err) {
 322                         dev_err(dev, "Cannot set voltage %lu uV\n",
 323                                 target_volt);
 324                         goto out;
 325                 }
 326         }
 327
 328         err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
 329         if (err) {
 330                 dev_err(dev, "Cannot set frequency %lu (%d)\n",
 331                         target_rate, err);
 332                 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
 333                                       INT_MAX);
 334                 goto out;
 335         }
 336
 337         /*
 338          * Check the dpll rate,
 339          * There only two result we will get,
 340          * 1. Ddr frequency scaling fail, we still get the old rate.
 341          * 2. Ddr frequency scaling sucessful, we get the rate we set.
 342          */
 343         dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
 344
 345         /* If get the incorrect rate, set voltage to old value. */
 346         if (dmcfreq->rate != target_rate) {
 347                 dev_err(dev, "Get wrong frequency, Request %lu, Current %lu\n",
 348                         target_rate, dmcfreq->rate);
 349                 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
 350                                       INT_MAX);
 351                 goto out;
 352         } else if (old_clk_rate > target_rate) {
 353                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 354                                             INT_MAX);
 355                 if (err) {
 356                         dev_err(dev, "Cannot set vol %lu uV\n", target_volt);
 357                         goto out;
 358                 }
 359         }
 360
 361         dmcfreq->volt = target_volt;
 362 out:
 363         __cpufreq_driver_target(policy, cpufreq_cur, CPUFREQ_RELATION_L);
 364         up_write(&policy->rwsem);
 365         cpufreq_cpu_put(policy);
 366 cpufreq:
 367         put_online_cpus();
 368         mutex_unlock(&dmcfreq->lock);
 369         return err;
 370 }
 371
 372 static int rockchip_dmcfreq_get_dev_status(struct device *dev,
 373                                            struct devfreq_dev_status *stat)
 374 {
 375         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 376         struct devfreq_event_data edata;
 377         int ret = 0;
 378
 379         ret = devfreq_event_get_event(dmcfreq->edev, &edata);
 380         if (ret < 0)
 381                 return ret;
 382
 383         stat->current_frequency = dmcfreq->rate;
 384         stat->busy_time = edata.load_count;
 385         stat->total_time = edata.total_count;
 386
 387         return ret;
 388 }
 389
 390 static int rockchip_dmcfreq_get_cur_freq(struct device *dev,
 391                                          unsigned long *freq)
 392 {
 393         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 394
 395         *freq = dmcfreq->rate;
 396
 397         return 0;
 398 }
 399
 400 static struct devfreq_dev_profile rockchip_devfreq_dmc_profile = {
 401         .polling_ms     = 50,
 402         .target         = rockchip_dmcfreq_target,
 403         .get_dev_status = rockchip_dmcfreq_get_dev_status,
 404         .get_cur_freq   = rockchip_dmcfreq_get_cur_freq,
 405 };
 406
 407 static __maybe_unused int rockchip_dmcfreq_suspend(struct device *dev)
 408 {
 409         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 410         int ret = 0;
 411
 412         ret = devfreq_event_disable_edev(dmcfreq->edev);
 413         if (ret < 0) {
 414                 dev_err(dev, "failed to disable the devfreq-event devices\n");
 415                 return ret;
 416         }
 417
 418         ret = devfreq_suspend_device(dmcfreq->devfreq);
 419         if (ret < 0) {
 420                 dev_err(dev, "failed to suspend the devfreq devices\n");
 421                 return ret;
 422         }
 423
 424         return 0;
 425 }
 426
 427 static __maybe_unused int rockchip_dmcfreq_resume(struct device *dev)
 428 {
 429         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 430         int ret = 0;
 431
 432         ret = devfreq_event_enable_edev(dmcfreq->edev);
 433         if (ret < 0) {
 434                 dev_err(dev, "failed to enable the devfreq-event devices\n");
 435                 return ret;
 436         }
 437
 438         ret = devfreq_resume_device(dmcfreq->devfreq);
 439         if (ret < 0) {
 440                 dev_err(dev, "failed to resume the devfreq devices\n");
 441                 return ret;
 442         }
 443         return ret;
 444 }
 445
 446 static SIMPLE_DEV_PM_OPS(rockchip_dmcfreq_pm, rockchip_dmcfreq_suspend,
 447                          rockchip_dmcfreq_resume);
 448
 449 static int rockchip_dmcfreq_init_freq_table(struct device *dev,
 450                                             struct devfreq_dev_profile *devp)
 451 {
 452         int count;
 453         int i = 0;
 454         unsigned long freq = 0;
 455         struct dev_pm_opp *opp;
 456
 457         rcu_read_lock();
 458         count = dev_pm_opp_get_opp_count(dev);
 459         if (count < 0) {
 460                 rcu_read_unlock();
 461                 return count;
 462         }
 463         rcu_read_unlock();
 464
 465         devp->freq_table = kmalloc_array(count, sizeof(devp->freq_table[0]),
 466                                 GFP_KERNEL);
 467         if (!devp->freq_table)
 468                 return -ENOMEM;
 469
 470         rcu_read_lock();
 471         for (i = 0; i < count; i++, freq++) {
 472                 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
 473                 if (IS_ERR(opp))
 474                         break;
 475
 476                 devp->freq_table[i] = freq;
 477         }
 478         rcu_read_unlock();
 479
 480         if (count != i)
 481                 dev_warn(dev, "Unable to enumerate all OPPs (%d!=%d)\n",
 482                          count, i);
 483
 484         devp->max_state = i;
 485         return 0;
 486 }
 487
 488 static void of_get_rk3288_timings(struct device *dev,
 489                                   struct device_node *np, uint32_t *timing)
 490 {
 491         struct device_node *np_tim;
 492         u32 *p;
 493         struct rk3288_ddr_dts_config_timing *dts_timing;
 494         struct share_params *init_timing;
 495         int ret = 0;
 496         u32 i;
 497
 498         init_timing = (struct share_params *)timing;
 499
 500         if (of_property_read_u32(np, "vop-dclk-mode",
 501                                  &init_timing->vop_dclk_mode))
 502                 init_timing->vop_dclk_mode = 0;
 503
 504         p = timing + DTS_PAR_OFFSET / 4;
 505         np_tim = of_parse_phandle(np, "rockchip,ddr_timing", 0);
 506         if (!np_tim) {
 507                 ret = -EINVAL;
 508                 goto end;
 509         }
 510         for (i = 0; i < ARRAY_SIZE(rk3288_dts_timing); i++) {
 511                 ret |= of_property_read_u32(np_tim, rk3288_dts_timing[i],
 512                                         p + i);
 513         }
 514 end:
 515         dts_timing =
 516                 (struct rk3288_ddr_dts_config_timing *)(timing +
 517                                                         DTS_PAR_OFFSET / 4);
 518         if (!ret) {
 519                 dts_timing->available = 1;
 520         } else {
 521                 dts_timing->available = 0;
 522                 dev_err(dev, "of_get_ddr_timings: fail\n");
 523         }
 524
 525         of_node_put(np_tim);
 526 }
 527
 528 static struct rk3368_dram_timing *of_get_rk3368_timings(struct device *dev,
 529                                                         struct device_node *np)
 530 {
 531         struct rk3368_dram_timing *timing = NULL;
 532         struct device_node *np_tim;
 533         int ret;
 534
 535         np_tim = of_parse_phandle(np, "ddr_timing", 0);
 536         if (np_tim) {
 537                 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
 538                 if (!timing)
 539                         goto err;
 540
 541                 ret |= of_property_read_u32(np_tim, "dram_spd_bin",
 542                                             &timing->dram_spd_bin);
 543                 ret |= of_property_read_u32(np_tim, "sr_idle",
 544                                             &timing->sr_idle);
 545                 ret |= of_property_read_u32(np_tim, "pd_idle",
 546                                             &timing->pd_idle);
 547                 ret |= of_property_read_u32(np_tim, "dram_dll_disb_freq",
 548                                             &timing->dram_dll_dis_freq);
 549                 ret |= of_property_read_u32(np_tim, "phy_dll_disb_freq",
 550                                             &timing->phy_dll_dis_freq);
 551                 ret |= of_property_read_u32(np_tim, "dram_odt_disb_freq",
 552                                             &timing->dram_odt_dis_freq);
 553                 ret |= of_property_read_u32(np_tim, "phy_odt_disb_freq",
 554                                             &timing->phy_odt_dis_freq);
 555                 ret |= of_property_read_u32(np_tim, "ddr3_drv",
 556                                             &timing->ddr3_drv);
 557                 ret |= of_property_read_u32(np_tim, "ddr3_odt",
 558                                             &timing->ddr3_odt);
 559                 ret |= of_property_read_u32(np_tim, "lpddr3_drv",
 560                                             &timing->lpddr3_drv);
 561                 ret |= of_property_read_u32(np_tim, "lpddr3_odt",
 562                                             &timing->lpddr3_odt);
 563                 ret |= of_property_read_u32(np_tim, "lpddr2_drv",
 564                                             &timing->lpddr2_drv);
 565                 ret |= of_property_read_u32(np_tim, "phy_clk_drv",
 566                                             &timing->phy_clk_drv);
 567                 ret |= of_property_read_u32(np_tim, "phy_cmd_drv",
 568                                             &timing->phy_cmd_drv);
 569                 ret |= of_property_read_u32(np_tim, "phy_dqs_drv",
 570                                             &timing->phy_dqs_drv);
 571                 ret |= of_property_read_u32(np_tim, "phy_odt",
 572                                             &timing->phy_odt);
 573                 if (ret) {
 574                         devm_kfree(dev, timing);
 575                         goto err;
 576                 }
 577                 of_node_put(np_tim);
 578                 return timing;
 579         }
 580
 581 err:
 582         if (timing) {
 583                 devm_kfree(dev, timing);
 584                 timing = NULL;
 585         }
 586         of_node_put(np_tim);
 587         return timing;
 588 }
 589
 590 static int rk_drm_get_lcdc_type(void)
 591 {
 592         struct drm_device *drm;
 593         u32 lcdc_type = 0;
 594
 595         drm = drm_device_get_by_name("rockchip");
 596         if (drm) {
 597                 struct drm_connector *conn;
 598
 599                 mutex_lock(&drm->mode_config.mutex);
 600                 drm_for_each_connector(conn, drm) {
 601                         if (conn->encoder) {
 602                                 lcdc_type = conn->connector_type;
 603                                 break;
 604                         }
 605                 }
 606                 mutex_unlock(&drm->mode_config.mutex);
 607         }
 608         switch (lcdc_type) {
 609         case DRM_MODE_CONNECTOR_LVDS:
 610                 lcdc_type = SCREEN_LVDS;
 611                 break;
 612         case DRM_MODE_CONNECTOR_DisplayPort:
 613                 lcdc_type = SCREEN_DP;
 614                 break;
 615         case DRM_MODE_CONNECTOR_HDMIA:
 616         case DRM_MODE_CONNECTOR_HDMIB:
 617                 lcdc_type = SCREEN_HDMI;
 618                 break;
 619         case DRM_MODE_CONNECTOR_TV:
 620                 lcdc_type = SCREEN_TVOUT;
 621                 break;
 622         case DRM_MODE_CONNECTOR_eDP:
 623                 lcdc_type = SCREEN_EDP;
 624                 break;
 625         case DRM_MODE_CONNECTOR_DSI:
 626                 lcdc_type = SCREEN_MIPI;
 627                 break;
 628         default:
 629                 lcdc_type = SCREEN_NULL;
 630                 break;
 631         }
 632
 633         return lcdc_type;
 634 }
 635
 636 static int rockchip_ddr_set_auto_self_refresh(uint32_t en)
 637 {
 638         struct arm_smccc_res res;
 639
 640         ddr_psci_param->sr_idle_en = en;
 641         res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
 642                            ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR);
 643
 644         return res.a0;
 645 }
 646
 647 static int rk3288_dmc_init(struct platform_device *pdev,
 648                            struct rockchip_dmcfreq *dmcfreq)
 649 {
 650         struct device *dev = &pdev->dev;
 651         struct clk *pclk_phy, *pclk_upctl, *dmc_clk;
 652         struct arm_smccc_res res;
 653         struct drm_device *drm = drm_device_get_by_name("rockchip");
 654         int ret;
 655
 656         if (!drm) {
 657                 dev_err(dev, "Get drm_device fail\n");
 658                 return -EPROBE_DEFER;
 659         }
 660
 661         dmc_clk = devm_clk_get(dev, "dmc_clk");
 662         if (IS_ERR(dmc_clk)) {
 663                 dev_err(dev, "Cannot get the clk dmc_clk\n");
 664                 return PTR_ERR(dmc_clk);
 665         }
 666         ret = clk_prepare_enable(dmc_clk);
 667         if (ret < 0) {
 668                 dev_err(dev, "failed to prepare/enable dmc_clk\n");
 669                 return ret;
 670         }
 671
 672         pclk_phy = devm_clk_get(dev, "pclk_phy0");
 673         if (IS_ERR(pclk_phy)) {
 674                 dev_err(dev, "Cannot get the clk pclk_phy0\n");
 675                 return PTR_ERR(pclk_phy);
 676         }
 677         ret = clk_prepare_enable(pclk_phy);
 678         if (ret < 0) {
 679                 dev_err(dev, "failed to prepare/enable pclk_phy0\n");
 680                 return ret;
 681         }
 682         pclk_upctl = devm_clk_get(dev, "pclk_upctl0");
 683         if (IS_ERR(pclk_upctl)) {
 684                 dev_err(dev, "Cannot get the clk pclk_upctl0\n");
 685                 return PTR_ERR(pclk_upctl);
 686         }
 687         ret = clk_prepare_enable(pclk_upctl);
 688         if (ret < 0) {
 689                 dev_err(dev, "failed to prepare/enable pclk_upctl1\n");
 690                 return ret;
 691         }
 692
 693         pclk_phy = devm_clk_get(dev, "pclk_phy1");
 694         if (IS_ERR(pclk_phy)) {
 695                 dev_err(dev, "Cannot get the clk pclk_phy1\n");
 696                 return PTR_ERR(pclk_phy);
 697         }
 698         ret = clk_prepare_enable(pclk_phy);
 699         if (ret < 0) {
 700                 dev_err(dev, "failed to prepare/enable pclk_phy1\n");
 701                 return ret;
 702         }
 703         pclk_upctl = devm_clk_get(dev, "pclk_upctl1");
 704         if (IS_ERR(pclk_upctl)) {
 705                 dev_err(dev, "Cannot get the clk pclk_upctl1\n");
 706                 return PTR_ERR(pclk_upctl);
 707         }
 708         ret = clk_prepare_enable(pclk_upctl);
 709         if (ret < 0) {
 710                 dev_err(dev, "failed to prepare/enable pclk_upctl1\n");
 711                 return ret;
 712         }
 713
 714         res = sip_smc_request_share_mem(DIV_ROUND_UP(sizeof(
 715                                         struct rk3288_ddr_dts_config_timing),
 716                                         4096) + 1, SHARE_PAGE_TYPE_DDR);
 717         if (res.a0) {
 718                 dev_err(&pdev->dev, "no ATF memory for init\n");
 719                 return -ENOMEM;
 720         }
 721
 722         ddr_psci_param = (struct share_params *)res.a1;
 723         of_get_rk3288_timings(&pdev->dev, pdev->dev.of_node,
 724                               (uint32_t *)ddr_psci_param);
 725
 726         ddr_psci_param->hz = 0;
 727         ddr_psci_param->lcdc_type = rk_drm_get_lcdc_type();
 728         res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
 729                            ROCKCHIP_SIP_CONFIG_DRAM_INIT);
 730
 731         if (res.a0) {
 732                 dev_err(&pdev->dev, "rockchip_sip_config_dram_init error:%lx\n",
 733                         res.a0);
 734                 return -ENOMEM;
 735         }
 736
 737         dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
 738
 739         return 0;
 740 }
 741
 742 static int rk3368_dmc_init(struct platform_device *pdev,
 743                            struct rockchip_dmcfreq *dmcfreq)
 744 {
 745         struct device *dev = &pdev->dev;
 746         struct device_node *np = pdev->dev.of_node;
 747         struct arm_smccc_res res;
 748         struct rk3368_dram_timing *dram_timing;
 749         struct clk *pclk_phy, *pclk_upctl;
 750         struct drm_device *drm = drm_device_get_by_name("rockchip");
 751         int ret;
 752         u32 dram_spd_bin;
 753         u32 addr_mcu_el3;
 754         u32 dclk_mode;
 755         u32 lcdc_type;
 756
 757         if (!drm) {
 758                 dev_err(dev, "Get drm_device fail\n");
 759                 return -EPROBE_DEFER;
 760         }
 761
 762         pclk_phy = devm_clk_get(dev, "pclk_phy");
 763         if (IS_ERR(pclk_phy)) {
 764                 dev_err(dev, "Cannot get the clk pclk_phy\n");
 765                 return PTR_ERR(pclk_phy);
 766         }
 767         ret = clk_prepare_enable(pclk_phy);
 768         if (ret < 0) {
 769                 dev_err(dev, "failed to prepare/enable pclk_phy\n");
 770                 return ret;
 771         }
 772         pclk_upctl = devm_clk_get(dev, "pclk_upctl");
 773         if (IS_ERR(pclk_upctl)) {
 774                 dev_err(dev, "Cannot get the clk pclk_upctl\n");
 775                 return PTR_ERR(pclk_upctl);
 776         }
 777         ret = clk_prepare_enable(pclk_upctl);
 778         if (ret < 0) {
 779                 dev_err(dev, "failed to prepare/enable pclk_upctl\n");
 780                 return ret;
 781         }
 782
 783         /*
 784          * Get dram timing and pass it to arm trust firmware,
 785          * the dram drvier in arm trust firmware will get these
 786          * timing and to do dram initial.
 787          */
 788         dram_timing = of_get_rk3368_timings(dev, np);
 789         if (dram_timing) {
 790                 dram_spd_bin = dram_timing->dram_spd_bin;
 791                 if (scpi_ddr_send_timing((u32 *)dram_timing,
 792                                          sizeof(struct rk3368_dram_timing)))
 793                         dev_err(dev, "send ddr timing timeout\n");
 794         } else {
 795                 dev_err(dev, "get ddr timing from dts error\n");
 796                 dram_spd_bin = DDR3_DEFAULT;
 797         }
 798
 799         res = sip_smc_mcu_el3fiq(FIQ_INIT_HANDLER,
 800                                  FIQ_NUM_FOR_DCF,
 801                                  FIQ_CPU_TGT_BOOT);
 802         if ((res.a0) || (res.a1 == 0) || (res.a1 > 0x80000))
 803                 dev_err(dev, "Trust version error, pls check trust version\n");
 804         addr_mcu_el3 = res.a1;
 805
 806         if (of_property_read_u32(np, "vop-dclk-mode", &dclk_mode) == 0)
 807                 scpi_ddr_dclk_mode(dclk_mode);
 808
 809         lcdc_type = rk_drm_get_lcdc_type();
 810
 811         if (scpi_ddr_init(dram_spd_bin, 0, lcdc_type,
 812                           addr_mcu_el3))
 813                 dev_err(dev, "ddr init error\n");
 814         else
 815                 dev_dbg(dev, ("%s out\n"), __func__);
 816
 817         dmcfreq->set_auto_self_refresh = scpi_ddr_set_auto_self_refresh;
 818
 819         return 0;
 820 }
 821
 822 static struct rk3399_dram_timing *of_get_rk3399_timings(struct device *dev,
 823                                                         struct device_node *np)
 824 {
 825         struct rk3399_dram_timing *timing = NULL;
 826         struct device_node *np_tim;
 827         int ret;
 828
 829         np_tim = of_parse_phandle(np, "ddr_timing", 0);
 830         if (np_tim) {
 831                 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
 832                 if (!timing)
 833                         goto err;
 834
 835                 ret = of_property_read_u32(np_tim, "ddr3_speed_bin",
 836                                            &timing->ddr3_speed_bin);
 837                 ret |= of_property_read_u32(np_tim, "pd_idle",
 838                                             &timing->pd_idle);
 839                 ret |= of_property_read_u32(np_tim, "sr_idle",
 840                                             &timing->sr_idle);
 841                 ret |= of_property_read_u32(np_tim, "sr_mc_gate_idle",
 842                                             &timing->sr_mc_gate_idle);
 843                 ret |= of_property_read_u32(np_tim, "srpd_lite_idle",
 844                                             &timing->srpd_lite_idle);
 845                 ret |= of_property_read_u32(np_tim, "standby_idle",
 846                                             &timing->standby_idle);
 847                 ret |= of_property_read_u32(np_tim, "dram_dll_dis_freq",
 848                                             &timing->dram_dll_dis_freq);
 849                 ret |= of_property_read_u32(np_tim, "phy_dll_dis_freq",
 850                                             &timing->phy_dll_dis_freq);
 851                 ret |= of_property_read_u32(np_tim, "ddr3_odt_dis_freq",
 852                                             &timing->ddr3_odt_dis_freq);
 853                 ret |= of_property_read_u32(np_tim, "ddr3_drv",
 854                                             &timing->ddr3_drv);
 855                 ret |= of_property_read_u32(np_tim, "ddr3_odt",
 856                                             &timing->ddr3_odt);
 857                 ret |= of_property_read_u32(np_tim, "phy_ddr3_ca_drv",
 858                                             &timing->phy_ddr3_ca_drv);
 859                 ret |= of_property_read_u32(np_tim, "phy_ddr3_dq_drv",
 860                                             &timing->phy_ddr3_dq_drv);
 861                 ret |= of_property_read_u32(np_tim, "phy_ddr3_odt",
 862                                             &timing->phy_ddr3_odt);
 863                 ret |= of_property_read_u32(np_tim, "lpddr3_odt_dis_freq",
 864                                             &timing->lpddr3_odt_dis_freq);
 865                 ret |= of_property_read_u32(np_tim, "lpddr3_drv",
 866                                             &timing->lpddr3_drv);
 867                 ret |= of_property_read_u32(np_tim, "lpddr3_odt",
 868                                             &timing->lpddr3_odt);
 869                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_ca_drv",
 870                                             &timing->phy_lpddr3_ca_drv);
 871                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_dq_drv",
 872                                             &timing->phy_lpddr3_dq_drv);
 873                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_odt",
 874                                             &timing->phy_lpddr3_odt);
 875                 ret |= of_property_read_u32(np_tim, "lpddr4_odt_dis_freq",
 876                                             &timing->lpddr4_odt_dis_freq);
 877                 ret |= of_property_read_u32(np_tim, "lpddr4_drv",
 878                                             &timing->lpddr4_drv);
 879                 ret |= of_property_read_u32(np_tim, "lpddr4_dq_odt",
 880                                             &timing->lpddr4_dq_odt);
 881                 ret |= of_property_read_u32(np_tim, "lpddr4_ca_odt",
 882                                             &timing->lpddr4_ca_odt);
 883                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ca_drv",
 884                                             &timing->phy_lpddr4_ca_drv);
 885                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ck_cs_drv",
 886                                             &timing->phy_lpddr4_ck_cs_drv);
 887                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_dq_drv",
 888                                             &timing->phy_lpddr4_dq_drv);
 889                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_odt",
 890                                             &timing->phy_lpddr4_odt);
 891                 if (ret) {
 892                         devm_kfree(dev, timing);
 893                         goto err;
 894                 }
 895                 of_node_put(np_tim);
 896                 return timing;
 897         }
 898
 899 err:
 900         if (timing) {
 901                 devm_kfree(dev, timing);
 902                 timing = NULL;
 903         }
 904         of_node_put(np_tim);
 905         return timing;
 906 }
 907
 908 static int rk3399_dmc_init(struct platform_device *pdev)
 909 {
 910         struct device *dev = &pdev->dev;
 911         struct device_node *np = pdev->dev.of_node;
 912         struct arm_smccc_res res;
 913         struct rk3399_dram_timing *dram_timing;
 914         int index, size;
 915         u32 *timing;
 916
 917         /*
 918          * Get dram timing and pass it to arm trust firmware,
 919          * the dram drvier in arm trust firmware will get these
 920          * timing and to do dram initial.
 921          */
 922         dram_timing = of_get_rk3399_timings(dev, np);
 923         if (dram_timing) {
 924                 timing = (u32 *)dram_timing;
 925                 size = sizeof(struct rk3399_dram_timing) / 4;
 926                 for (index = 0; index < size; index++) {
 927                         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
 928                                       ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
 929                                       0, 0, 0, 0, &res);
 930                         if (res.a0) {
 931                                 dev_err(dev, "Failed to set dram param: %ld\n",
 932                                         res.a0);
 933                                 return -EINVAL;
 934                         }
 935                 }
 936         }
 937
 938         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
 939                       ROCKCHIP_SIP_CONFIG_DRAM_INIT,
 940                       0, 0, 0, 0, &res);
 941
 942         return 0;
 943 }
 944
 945 static const struct of_device_id rockchip_dmcfreq_of_match[] = {
 946         { .compatible = "rockchip,rk3288-dmc", .data = rk3288_dmc_init },
 947         { .compatible = "rockchip,rk3368-dmc", .data = rk3368_dmc_init },
 948         { .compatible = "rockchip,rk3399-dmc", .data = rk3399_dmc_init },
 949         { },
 950 };
 951 MODULE_DEVICE_TABLE(of, rockchip_dmcfreq_of_match);
 952
 953 static int rockchip_get_system_status_rate(struct device_node *np,
 954                                            char *porp_name,
 955                                            struct rockchip_dmcfreq *dmcfreq)
 956 {
 957         const struct property *prop;
 958         unsigned int status = 0, freq = 0;
 959         int count, i;
 960
 961         prop = of_find_property(np, porp_name, NULL);
 962         if (!prop)
 963                 return -EINVAL;
 964
 965         if (!prop->value)
 966                 return -ENODATA;
 967
 968         count = of_property_count_u32_elems(np, porp_name);
 969         if (count < 0)
 970                 return -EINVAL;
 971
 972         if (count % 2)
 973                 return -EINVAL;
 974
 975         for (i = 0; i < count / 2; i++) {
 976                 of_property_read_u32_index(np, porp_name, 2 * i,
 977                                            &status);
 978                 of_property_read_u32_index(np, porp_name, 2 * i + 1,
 979                                            &freq);
 980                 switch (status) {
 981                 case SYS_STATUS_NORMAL:
 982                         dmcfreq->normal_rate = freq * 1000;
 983                         break;
 984                 case SYS_STATUS_SUSPEND:
 985                         dmcfreq->suspend_rate = freq * 1000;
 986                         break;
 987                 case SYS_STATUS_VIDEO_1080P:
 988                         dmcfreq->video_1080p_rate = freq * 1000;
 989                         break;
 990                 case SYS_STATUS_VIDEO_4K:
 991                         dmcfreq->video_4k_rate = freq * 1000;
 992                         break;
 993                 case SYS_STATUS_VIDEO_4K_10B:
 994                         dmcfreq->video_4k_10b_rate = freq * 1000;
 995                         break;
 996                 case SYS_STATUS_PERFORMANCE:
 997                         dmcfreq->performance_rate = freq * 1000;
 998                         break;
 999                 case SYS_STATUS_LCDC0 & SYS_STATUS_LCDC1:
1000                         dmcfreq->dualview_rate = freq * 1000;
1001                         break;
1002                 case SYS_STATUS_HDMI:
1003                         dmcfreq->hdmi_rate = freq * 1000;
1004                         break;
1005                 case SYS_STATUS_IDLE:
1006                         dmcfreq->idle_rate = freq * 1000;
1007                         break;
1008                 case SYS_STATUS_REBOOT:
1009                         dmcfreq->reboot_rate = freq * 1000;
1010                         break;
1011                 case SYS_STATUS_BOOST:
1012                         dmcfreq->boost_rate = freq * 1000;
1013                         break;
1014                 case SYS_STATUS_ISP:
1015                         dmcfreq->isp_rate = freq * 1000;
1016                         break;
1017                 case SYS_STATUS_LOW_POWER:
1018                         dmcfreq->low_power_rate = freq * 1000;
1019                         break;
1020                 default:
1021                         break;
1022                 }
1023         }
1024
1025         return 0;
1026 }
1027
1028 static void rockchip_dmcfreq_update_status(struct rockchip_dmcfreq *dmcfreq,
1029                                            unsigned long status)
1030 {
1031         struct devfreq *df = dmcfreq->devfreq;
1032         struct devfreq_dev_profile *devp = df->profile;
1033         unsigned long min = devp->freq_table[0];
1034         unsigned long max =
1035                 devp->freq_table[devp->max_state ? devp->max_state - 1 : 0];
1036         unsigned long target_rate = 0;
1037         unsigned int refresh = false;
1038
1039         if (dmcfreq->reboot_rate && (status & SYS_STATUS_REBOOT)) {
1040                 target_rate = dmcfreq->reboot_rate;
1041                 goto next;
1042         }
1043
1044         if (dmcfreq->suspend_rate && (status & SYS_STATUS_SUSPEND)) {
1045                 if (dmcfreq->suspend_rate > target_rate) {
1046                         target_rate = dmcfreq->suspend_rate;
1047                         refresh = true;
1048                         goto next;
1049                 }
1050         }
1051
1052         if (dmcfreq->low_power_rate && (status & SYS_STATUS_LOW_POWER)) {
1053                 target_rate = dmcfreq->low_power_rate;
1054                 goto next;
1055         }
1056
1057         if (dmcfreq->performance_rate && (status & SYS_STATUS_PERFORMANCE)) {
1058                 if (dmcfreq->performance_rate > target_rate)
1059                         target_rate = dmcfreq->performance_rate;
1060         }
1061
1062         if (dmcfreq->dualview_rate && (status & SYS_STATUS_LCDC0) &&
1063             (status & SYS_STATUS_LCDC1)) {
1064                 if (dmcfreq->dualview_rate > target_rate)
1065                         target_rate = dmcfreq->dualview_rate;
1066         }
1067
1068         if (dmcfreq->hdmi_rate && (status & SYS_STATUS_HDMI)) {
1069                 if (dmcfreq->hdmi_rate > target_rate)
1070                         target_rate = dmcfreq->hdmi_rate;
1071         }
1072
1073         if (dmcfreq->video_4k_rate && (status & SYS_STATUS_VIDEO_4K)) {
1074                 if (dmcfreq->video_4k_rate > target_rate)
1075                         target_rate = dmcfreq->video_4k_rate;
1076         }
1077
1078         if (dmcfreq->video_4k_10b_rate && (status & SYS_STATUS_VIDEO_4K_10B)) {
1079                 if (dmcfreq->video_4k_10b_rate > target_rate)
1080                         target_rate = dmcfreq->video_4k_10b_rate;
1081         }
1082
1083         if (dmcfreq->video_1080p_rate && (status & SYS_STATUS_VIDEO_1080P)) {
1084                 if (dmcfreq->video_1080p_rate > target_rate)
1085                         target_rate = dmcfreq->video_1080p_rate;
1086         }
1087
1088         if (dmcfreq->isp_rate && (status & SYS_STATUS_ISP)) {
1089                 if (dmcfreq->isp_rate > target_rate)
1090                         target_rate = dmcfreq->isp_rate;
1091         }
1092
1093 next:
1094
1095         mutex_lock(&df->lock);
1096
1097         if (target_rate) {
1098                 df->min_freq = target_rate;
1099                 df->max_freq = target_rate;
1100         } else {
1101                 if (dmcfreq->auto_freq_en) {
1102                         if (dmcfreq->auto_min_freq)
1103                                 df->min_freq = dmcfreq->auto_min_freq * 1000;
1104                         else
1105                                 df->min_freq = min;
1106                         df->max_freq = max;
1107                 } else if (dmcfreq->normal_rate) {
1108                         df->min_freq = dmcfreq->normal_rate;
1109                         df->max_freq = dmcfreq->normal_rate;
1110                 }
1111         }
1112
1113         dev_dbg(&df->dev, "status=0x%x min=%lu max=%lu\n",
1114                 (unsigned int)status, df->min_freq, df->min_freq);
1115
1116         if (dmcfreq->aotu_self_refresh != refresh) {
1117                 if (dmcfreq->set_auto_self_refresh)
1118                         dmcfreq->set_auto_self_refresh(refresh);
1119                 dmcfreq->aotu_self_refresh = refresh;
1120         }
1121
1122         update_devfreq(df);
1123
1124         mutex_unlock(&df->lock);
1125 }
1126
1127 static int rockchip_dmcfreq_system_status_notifier(struct notifier_block *nb,
1128                                                    unsigned long val, void *ptr)
1129 {
1130         struct rockchip_dmcfreq *dmcfreq = system_status_to_dmcfreq(nb);
1131
1132         rockchip_dmcfreq_update_status(dmcfreq, val);
1133
1134         return NOTIFY_OK;
1135 }
1136
1137 static int rockchip_dmcfreq_reboot_notifier(struct notifier_block *nb,
1138                                             unsigned long action, void *ptr)
1139 {
1140         struct rockchip_dmcfreq *dmcfreq = reboot_to_dmcfreq(nb);
1141
1142         devfreq_monitor_stop(dmcfreq->devfreq);
1143         rockchip_set_system_status(SYS_STATUS_REBOOT);
1144
1145         return NOTIFY_OK;
1146 }
1147
1148 static int rockchip_dmcfreq_fb_notifier(struct notifier_block *nb,
1149                                         unsigned long action, void *ptr)
1150 {
1151         struct fb_event *event = ptr;
1152
1153         switch (action) {
1154         case FB_EARLY_EVENT_BLANK:
1155                 switch (*((int *)event->data)) {
1156                 case FB_BLANK_UNBLANK:
1157                         rockchip_clear_system_status(SYS_STATUS_SUSPEND);
1158                         break;
1159                 default:
1160                         break;
1161                 }
1162                 break;
1163         case FB_EVENT_BLANK:
1164                 switch (*((int *)event->data)) {
1165                 case FB_BLANK_POWERDOWN:
1166                         rockchip_set_system_status(SYS_STATUS_SUSPEND);
1167                         break;
1168                 default:
1169                         break;
1170                 }
1171                 break;
1172         default:
1173                 break;
1174         }
1175
1176         return NOTIFY_OK;
1177 }
1178
1179 static ssize_t rockchip_dmcfreq_status_show(struct device *dev,
1180                                             struct device_attribute *attr,
1181                                             char *buf)
1182 {
1183         unsigned int status = rockchip_get_system_status();
1184
1185         return sprintf(buf, "0x%x\n", status);
1186 }
1187
1188 static unsigned long rockchip_get_video_param(char **str)
1189 {
1190         char *p;
1191         unsigned long val = 0;
1192
1193         strsep(str, "=");
1194         p = strsep(str, ",");
1195         if (p) {
1196                 if (kstrtoul(p, 10, &val))
1197                         return 0;
1198         }
1199
1200         return val;
1201 }
1202
1203 /*
1204  * format:
1205  * 0,width=val,height=val,ishevc=val,videoFramerate=val,streamBitrate=val
1206  * 1,width=val,height=val,ishevc=val,videoFramerate=val,streamBitrate=val
1207  */
1208 static struct video_info *rockchip_parse_video_info(const char *buf)
1209 {
1210         struct video_info *video_info;
1211         const char *cp = buf;
1212         char *str;
1213         int ntokens = 0;
1214
1215         while ((cp = strpbrk(cp + 1, ",")))
1216                 ntokens++;
1217         if (ntokens != 5)
1218                 return NULL;
1219
1220         video_info = kzalloc(sizeof(*video_info), GFP_KERNEL);
1221         if (!video_info)
1222                 return NULL;
1223
1224         INIT_LIST_HEAD(&video_info->node);
1225
1226         str = kstrdup(buf, GFP_KERNEL);
1227         strsep(&str, ",");
1228         video_info->width = rockchip_get_video_param(&str);
1229         video_info->height = rockchip_get_video_param(&str);
1230         video_info->ishevc = rockchip_get_video_param(&str);
1231         video_info->videoFramerate = rockchip_get_video_param(&str);
1232         video_info->streamBitrate = rockchip_get_video_param(&str);
1233         pr_debug("%c,width=%d,height=%d,ishevc=%d,videoFramerate=%d,streamBitrate=%d\n",
1234                  buf[0],
1235                  video_info->width,
1236                  video_info->height,
1237                  video_info->ishevc,
1238                  video_info->videoFramerate,
1239                  video_info->streamBitrate);
1240         kfree(str);
1241
1242         return video_info;
1243 }
1244
1245 struct video_info *rockchip_find_video_info(struct rockchip_dmcfreq *dmcfreq,
1246                                             const char *buf)
1247 {
1248         struct video_info *info, *video_info;
1249
1250         video_info = rockchip_parse_video_info(buf);
1251
1252         if (!video_info)
1253                 return NULL;
1254
1255         list_for_each_entry(info, &dmcfreq->video_info_list, node) {
1256                 if ((info->width == video_info->width) &&
1257                     (info->height == video_info->height) &&
1258                     (info->ishevc == video_info->ishevc) &&
1259                     (info->videoFramerate == video_info->videoFramerate) &&
1260                     (info->streamBitrate == video_info->streamBitrate)) {
1261                         kfree(video_info);
1262                         return info;
1263                 }
1264         }
1265
1266         kfree(video_info);
1267
1268         return NULL;
1269 }
1270
1271 static void rockchip_add_video_info(struct rockchip_dmcfreq *dmcfreq,
1272                                     struct video_info *video_info)
1273 {
1274         if (video_info)
1275                 list_add(&video_info->node, &dmcfreq->video_info_list);
1276 }
1277
1278 static void rockchip_del_video_info(struct video_info *video_info)
1279 {
1280         if (video_info) {
1281                 list_del(&video_info->node);
1282                 kfree(video_info);
1283         }
1284 }
1285
1286 static void rockchip_update_video_info(struct rockchip_dmcfreq *dmcfreq)
1287 {
1288         struct video_info *video_info;
1289         int max_res = 0, max_stream_bitrate = 0, res = 0;
1290
1291         if (list_empty(&dmcfreq->video_info_list)) {
1292                 rockchip_clear_system_status(SYS_STATUS_VIDEO);
1293                 return;
1294         }
1295
1296         list_for_each_entry(video_info, &dmcfreq->video_info_list, node) {
1297                 res = video_info->width * video_info->height;
1298                 if (res > max_res)
1299                         max_res = res;
1300                 if (video_info->streamBitrate > max_stream_bitrate)
1301                         max_stream_bitrate = video_info->streamBitrate;
1302         }
1303
1304         if (max_res <= VIDEO_1080P_SIZE) {
1305                 rockchip_set_system_status(SYS_STATUS_VIDEO_1080P);
1306         } else {
1307                 if (max_stream_bitrate == 10)
1308                         rockchip_set_system_status(SYS_STATUS_VIDEO_4K_10B);
1309                 else
1310                         rockchip_set_system_status(SYS_STATUS_VIDEO_4K);
1311         }
1312 }
1313
1314 static ssize_t rockchip_dmcfreq_status_store(struct device *dev,
1315                                              struct device_attribute *attr,
1316                                              const char *buf,
1317                                              size_t count)
1318 {
1319         struct devfreq *devfreq = to_devfreq(dev);
1320         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(devfreq->dev.parent);
1321         struct video_info *video_info;
1322
1323         if (!count)
1324                 return -EINVAL;
1325
1326         switch (buf[0]) {
1327         case '0':
1328                 /* clear video flag */
1329                 video_info = rockchip_find_video_info(dmcfreq, buf);
1330                 if (video_info) {
1331                         rockchip_del_video_info(video_info);
1332                         rockchip_update_video_info(dmcfreq);
1333                 }
1334                 break;
1335         case '1':
1336                 /* set video flag */
1337                 video_info = rockchip_parse_video_info(buf);
1338                 if (video_info) {
1339                         rockchip_add_video_info(dmcfreq, video_info);
1340                         rockchip_update_video_info(dmcfreq);
1341                 }
1342                 break;
1343         case 'L':
1344                 /* clear low power flag */
1345                 rockchip_clear_system_status(SYS_STATUS_LOW_POWER);
1346                 break;
1347         case 'l':
1348                 /* set low power flag */
1349                 rockchip_set_system_status(SYS_STATUS_LOW_POWER);
1350                 break;
1351         case 'p':
1352                 /* set performance flag */
1353                 rockchip_set_system_status(SYS_STATUS_PERFORMANCE);
1354                 break;
1355         case 'n':
1356                 /* clear performance flag */
1357                 rockchip_clear_system_status(SYS_STATUS_PERFORMANCE);
1358                 break;
1359         default:
1360                 break;
1361         }
1362
1363         return count;
1364 }
1365
1366 static DEVICE_ATTR(system_status, 0644, rockchip_dmcfreq_status_show,
1367                    rockchip_dmcfreq_status_store);
1368
1369 static int rockchip_dmcfreq_probe(struct platform_device *pdev)
1370 {
1371         struct device *dev = &pdev->dev;
1372         struct device_node *np = pdev->dev.of_node;
1373         struct rockchip_dmcfreq *data;
1374         struct devfreq_dev_profile *devp = &rockchip_devfreq_dmc_profile;
1375         const struct of_device_id *match;
1376         int (*init)(struct platform_device *pdev,
1377                     struct rockchip_dmcfreq *data);
1378         int ret;
1379
1380         data = devm_kzalloc(dev, sizeof(struct rockchip_dmcfreq), GFP_KERNEL);
1381         if (!data)
1382                 return -ENOMEM;
1383
1384         mutex_init(&data->lock);
1385         INIT_LIST_HEAD(&data->video_info_list);
1386
1387         data->vdd_center = devm_regulator_get(dev, "center");
1388         if (IS_ERR(data->vdd_center)) {
1389                 dev_err(dev, "Cannot get the regulator \"center\"\n");
1390                 return PTR_ERR(data->vdd_center);
1391         }
1392
1393         data->dmc_clk = devm_clk_get(dev, "dmc_clk");
1394         if (IS_ERR(data->dmc_clk)) {
1395                 dev_err(dev, "Cannot get the clk dmc_clk\n");
1396                 return PTR_ERR(data->dmc_clk);
1397         }
1398
1399         data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
1400         if (IS_ERR(data->edev))
1401                 return -EPROBE_DEFER;
1402
1403         ret = devfreq_event_enable_edev(data->edev);
1404         if (ret < 0) {
1405                 dev_err(dev, "failed to enable devfreq-event devices\n");
1406                 return ret;
1407         }
1408
1409         match = of_match_node(rockchip_dmcfreq_of_match, pdev->dev.of_node);
1410         if (match) {
1411                 init = match->data;
1412                 if (init) {
1413                         ret = init(pdev, data);
1414                         if (ret)
1415                                 return ret;
1416                 }
1417         }
1418
1419         /*
1420          * We add a devfreq driver to our parent since it has a device tree node
1421          * with operating points.
1422          */
1423         if (dev_pm_opp_of_add_table(dev)) {
1424                 dev_err(dev, "Invalid operating-points in device tree.\n");
1425                 return -EINVAL;
1426         }
1427
1428         if (rockchip_dmcfreq_init_freq_table(dev, devp))
1429                 return -EFAULT;
1430
1431         of_property_read_u32(np, "upthreshold",
1432                              &data->ondemand_data.upthreshold);
1433         of_property_read_u32(np, "downdifferential",
1434                              &data->ondemand_data.downdifferential);
1435         of_property_read_u32(np, "min-cpu-freq", &data->min_cpu_freq);
1436         if (rockchip_get_system_status_rate(np, "system-status-freq", data))
1437                 dev_err(dev, "failed to get system status rate\n");
1438         of_property_read_u32(np, "auto-min-freq", &data->auto_min_freq);
1439         of_property_read_u32(np, "auto-freq-en", &data->auto_freq_en);
1440
1441         data->rate = clk_get_rate(data->dmc_clk);
1442         data->volt = regulator_get_voltage(data->vdd_center);
1443
1444         devp->initial_freq = data->rate;
1445
1446         data->devfreq = devm_devfreq_add_device(dev, devp,
1447                                                 "simple_ondemand",
1448                                                 &data->ondemand_data);
1449         if (IS_ERR(data->devfreq))
1450                 return PTR_ERR(data->devfreq);
1451
1452         devm_devfreq_register_opp_notifier(dev, data->devfreq);
1453
1454         data->devfreq->min_freq = devp->freq_table[0];
1455         data->devfreq->max_freq =
1456                 devp->freq_table[devp->max_state ? devp->max_state - 1 : 0];
1457
1458         data->dev = dev;
1459         platform_set_drvdata(pdev, data);
1460
1461         if (rockchip_drm_register_notifier_to_dmc(data->devfreq))
1462                 dev_err(dev, "drm fail to register notifier to dmc\n");
1463
1464         if (rockchip_pm_register_notify_to_dmc(data->devfreq))
1465                 dev_err(dev, "pd fail to register notify to dmc\n");
1466
1467         if (vop_register_dmc())
1468                 dev_err(dev, "fail to register notify to vop.\n");
1469
1470         data->system_status_nb.notifier_call =
1471                 rockchip_dmcfreq_system_status_notifier;
1472         ret = rockchip_register_system_status_notifier(&data->system_status_nb);
1473         if (ret)
1474                 dev_err(dev, "failed to register system_status nb\n");
1475
1476         data->reboot_nb.notifier_call = rockchip_dmcfreq_reboot_notifier;
1477         ret = register_reboot_notifier(&data->reboot_nb);
1478         if (ret)
1479                 dev_err(dev, "failed to register reboot nb\n");
1480
1481         data->fb_nb.notifier_call = rockchip_dmcfreq_fb_notifier;
1482         ret = fb_register_client(&data->fb_nb);
1483         if (ret)
1484                 dev_err(dev, "failed to register fb nb\n");
1485
1486         ret = sysfs_create_file(&data->devfreq->dev.kobj,
1487                                 &dev_attr_system_status.attr);
1488         if (ret)
1489                 dev_err(dev, "failed to register system_status sysfs file\n");
1490
1491         rockchip_set_system_status(SYS_STATUS_NORMAL);
1492
1493         return 0;
1494 }
1495
1496 static struct platform_driver rockchip_dmcfreq_driver = {
1497         .probe  = rockchip_dmcfreq_probe,
1498         .driver = {
1499                 .name   = "rockchip-dmc",
1500                 .pm     = &rockchip_dmcfreq_pm,
1501                 .of_match_table = rockchip_dmcfreq_of_match,
1502         },
1503 };
1504 module_platform_driver(rockchip_dmcfreq_driver);
1505
1506 MODULE_LICENSE("GPL v2");
1507 MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
1508 MODULE_DESCRIPTION("rockchip dmcfreq driver with devfreq framework");