2 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
3 * Author: Lin Huang <hl@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <dt-bindings/clock/rockchip-ddr.h>
16 #include <dt-bindings/display/rk_fb.h>
18 #include <linux/arm-smccc.h>
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/devfreq.h>
22 #include <linux/devfreq-event.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_opp.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/rockchip/rockchip_sip.h>
30 #include <linux/rwsem.h>
31 #include <linux/slab.h>
32 #include <linux/suspend.h>
34 #include <soc/rockchip/rkfb_dmc.h>
35 #include <soc/rockchip/rockchip_dmc.h>
36 #include <soc/rockchip/rockchip_sip.h>
37 #include <soc/rockchip/scpi.h>
38 #include <uapi/drm/drm_mode.h>
40 #define FIQ_INIT_HANDLER (0x1)
41 #define FIQ_CPU_TGT_BOOT (0x0) /* to booting cpu */
42 #define FIQ_NUM_FOR_DCF (143) /* NA irq map to fiq for dcf */
43 #define DTS_PAR_OFFSET (4096)
46 /* these parameters, not use in RK322xh */
52 /* if need, add parameter after */
55 char *rk3288_dts_timing[] = {
70 "lpddr3_odt_dis_freq",
77 struct rk3288_ddr_dts_config_timing {
78 unsigned int ddr3_speed_bin;
82 unsigned int auto_pd_dis_freq;
83 unsigned int auto_sr_dis_freq;
85 unsigned int ddr3_dll_dis_freq;
86 unsigned int phy_dll_dis_freq;
88 unsigned int ddr3_odt_dis_freq;
89 unsigned int ddr3_drv;
90 unsigned int ddr3_odt;
91 unsigned int phy_ddr3_drv;
92 unsigned int phy_ddr3_odt;
94 unsigned int lpddr2_drv;
95 unsigned int phy_lpddr2_drv;
96 unsigned int lpddr3_odt_dis_freq;
97 unsigned int lpddr3_drv;
98 unsigned int lpddr3_odt;
99 unsigned int phy_lpddr3_drv;
100 unsigned int phy_lpddr3_odt;
102 unsigned int available;
105 struct rk3368_dram_timing {
109 u32 dram_dll_dis_freq;
110 u32 phy_dll_dis_freq;
111 u32 dram_odt_dis_freq;
112 u32 phy_odt_dis_freq;
124 struct rk3399_dram_timing {
125 unsigned int ddr3_speed_bin;
126 unsigned int pd_idle;
127 unsigned int sr_idle;
128 unsigned int sr_mc_gate_idle;
129 unsigned int srpd_lite_idle;
130 unsigned int standby_idle;
131 unsigned int dram_dll_dis_freq;
132 unsigned int phy_dll_dis_freq;
133 unsigned int ddr3_odt_dis_freq;
134 unsigned int ddr3_drv;
135 unsigned int ddr3_odt;
136 unsigned int phy_ddr3_ca_drv;
137 unsigned int phy_ddr3_dq_drv;
138 unsigned int phy_ddr3_odt;
139 unsigned int lpddr3_odt_dis_freq;
140 unsigned int lpddr3_drv;
141 unsigned int lpddr3_odt;
142 unsigned int phy_lpddr3_ca_drv;
143 unsigned int phy_lpddr3_dq_drv;
144 unsigned int phy_lpddr3_odt;
145 unsigned int lpddr4_odt_dis_freq;
146 unsigned int lpddr4_drv;
147 unsigned int lpddr4_dq_odt;
148 unsigned int lpddr4_ca_odt;
149 unsigned int phy_lpddr4_ca_drv;
150 unsigned int phy_lpddr4_ck_cs_drv;
151 unsigned int phy_lpddr4_dq_drv;
152 unsigned int phy_lpddr4_odt;
155 struct rockchip_dmcfreq {
157 struct devfreq *devfreq;
158 struct devfreq_simple_ondemand_data ondemand_data;
160 struct devfreq_event_dev *edev;
161 struct mutex lock; /* scaling frequency lock */
162 struct dram_timing *timing;
163 struct regulator *vdd_center;
164 unsigned long rate, target_rate;
165 unsigned long volt, target_volt;
168 static int rockchip_dmcfreq_target(struct device *dev, unsigned long *freq,
171 struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
172 struct dev_pm_opp *opp;
173 unsigned long old_clk_rate = dmcfreq->rate;
174 unsigned long temp_rate, target_volt, target_rate;
178 opp = devfreq_recommended_opp(dev, freq, flags);
184 temp_rate = dev_pm_opp_get_freq(opp);
185 target_rate = clk_round_rate(dmcfreq->dmc_clk, temp_rate);
186 if ((long)target_rate <= 0)
187 target_rate = temp_rate;
188 target_volt = dev_pm_opp_get_voltage(opp);
192 if (dmcfreq->rate == target_rate) {
193 if (dmcfreq->volt == target_volt)
195 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
198 dev_err(dev, "Cannot set voltage %lu uV\n",
204 mutex_lock(&dmcfreq->lock);
207 * If frequency scaling from low to high, adjust voltage first.
208 * If frequency scaling from high to low, adjust frequency first.
210 if (old_clk_rate < target_rate) {
211 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
214 dev_err(dev, "Cannot set voltage %lu uV\n",
220 err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
222 dev_err(dev, "Cannot set frequency %lu (%d)\n",
224 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
230 * Check the dpll rate,
231 * There only two result we will get,
232 * 1. Ddr frequency scaling fail, we still get the old rate.
233 * 2. Ddr frequency scaling sucessful, we get the rate we set.
235 dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
237 /* If get the incorrect rate, set voltage to old value. */
238 if (dmcfreq->rate != target_rate) {
239 dev_err(dev, "Get wrong frequency, Request %lu, Current %lu\n",
240 target_rate, dmcfreq->rate);
241 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
244 } else if (old_clk_rate > target_rate) {
245 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
248 dev_err(dev, "Cannot set vol %lu uV\n", target_volt);
253 dmcfreq->volt = target_volt;
255 mutex_unlock(&dmcfreq->lock);
259 static int rockchip_dmcfreq_get_dev_status(struct device *dev,
260 struct devfreq_dev_status *stat)
262 struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
263 struct devfreq_event_data edata;
266 ret = devfreq_event_get_event(dmcfreq->edev, &edata);
270 stat->current_frequency = dmcfreq->rate;
271 stat->busy_time = edata.load_count;
272 stat->total_time = edata.total_count;
277 static int rockchip_dmcfreq_get_cur_freq(struct device *dev,
280 struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
282 *freq = dmcfreq->rate;
287 static struct devfreq_dev_profile rockchip_devfreq_dmc_profile = {
289 .target = rockchip_dmcfreq_target,
290 .get_dev_status = rockchip_dmcfreq_get_dev_status,
291 .get_cur_freq = rockchip_dmcfreq_get_cur_freq,
294 static __maybe_unused int rockchip_dmcfreq_suspend(struct device *dev)
296 struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
299 ret = devfreq_event_disable_edev(dmcfreq->edev);
301 dev_err(dev, "failed to disable the devfreq-event devices\n");
305 ret = devfreq_suspend_device(dmcfreq->devfreq);
307 dev_err(dev, "failed to suspend the devfreq devices\n");
314 static __maybe_unused int rockchip_dmcfreq_resume(struct device *dev)
316 struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
319 ret = devfreq_event_enable_edev(dmcfreq->edev);
321 dev_err(dev, "failed to enable the devfreq-event devices\n");
325 ret = devfreq_resume_device(dmcfreq->devfreq);
327 dev_err(dev, "failed to resume the devfreq devices\n");
333 static SIMPLE_DEV_PM_OPS(rockchip_dmcfreq_pm, rockchip_dmcfreq_suspend,
334 rockchip_dmcfreq_resume);
336 static int rockchip_dmcfreq_init_freq_table(struct device *dev,
337 struct devfreq_dev_profile *devp)
341 unsigned long freq = 0;
342 struct dev_pm_opp *opp;
345 count = dev_pm_opp_get_opp_count(dev);
352 devp->freq_table = kmalloc_array(count, sizeof(devp->freq_table[0]),
354 if (!devp->freq_table)
358 for (i = 0; i < count; i++, freq++) {
359 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
363 devp->freq_table[i] = freq;
368 dev_warn(dev, "Unable to enumerate all OPPs (%d!=%d)\n",
375 static void of_get_rk3288_timings(struct device *dev,
376 struct device_node *np, uint32_t *timing)
378 struct device_node *np_tim;
380 struct rk3288_ddr_dts_config_timing *dts_timing;
381 struct init_params *init_timing;
385 init_timing = (struct init_params *)timing;
387 if (of_property_read_u32(np, "vop-dclk-mode",
388 &init_timing->vop_dclk_mode))
389 init_timing->vop_dclk_mode = 0;
391 p = timing + DTS_PAR_OFFSET / 4;
392 np_tim = of_parse_phandle(np, "rockchip,ddr_timing", 0);
397 for (i = 0; i < ARRAY_SIZE(rk3288_dts_timing); i++) {
398 ret |= of_property_read_u32(np_tim, rk3288_dts_timing[i],
403 (struct rk3288_ddr_dts_config_timing *)(timing +
406 dts_timing->available = 1;
408 dts_timing->available = 0;
409 dev_err(dev, "of_get_ddr_timings: fail\n");
415 static struct rk3368_dram_timing *of_get_rk3368_timings(struct device *dev,
416 struct device_node *np)
418 struct rk3368_dram_timing *timing = NULL;
419 struct device_node *np_tim;
422 np_tim = of_parse_phandle(np, "ddr_timing", 0);
424 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
428 ret |= of_property_read_u32(np_tim, "dram_spd_bin",
429 &timing->dram_spd_bin);
430 ret |= of_property_read_u32(np_tim, "sr_idle",
432 ret |= of_property_read_u32(np_tim, "pd_idle",
434 ret |= of_property_read_u32(np_tim, "dram_dll_disb_freq",
435 &timing->dram_dll_dis_freq);
436 ret |= of_property_read_u32(np_tim, "phy_dll_disb_freq",
437 &timing->phy_dll_dis_freq);
438 ret |= of_property_read_u32(np_tim, "dram_odt_disb_freq",
439 &timing->dram_odt_dis_freq);
440 ret |= of_property_read_u32(np_tim, "phy_odt_disb_freq",
441 &timing->phy_odt_dis_freq);
442 ret |= of_property_read_u32(np_tim, "ddr3_drv",
444 ret |= of_property_read_u32(np_tim, "ddr3_odt",
446 ret |= of_property_read_u32(np_tim, "lpddr3_drv",
447 &timing->lpddr3_drv);
448 ret |= of_property_read_u32(np_tim, "lpddr3_odt",
449 &timing->lpddr3_odt);
450 ret |= of_property_read_u32(np_tim, "lpddr2_drv",
451 &timing->lpddr2_drv);
452 ret |= of_property_read_u32(np_tim, "phy_clk_drv",
453 &timing->phy_clk_drv);
454 ret |= of_property_read_u32(np_tim, "phy_cmd_drv",
455 &timing->phy_cmd_drv);
456 ret |= of_property_read_u32(np_tim, "phy_dqs_drv",
457 &timing->phy_dqs_drv);
458 ret |= of_property_read_u32(np_tim, "phy_odt",
461 devm_kfree(dev, timing);
470 devm_kfree(dev, timing);
477 static int rk_drm_get_lcdc_type(void)
479 struct drm_device *drm;
482 drm = drm_device_get_by_name("rockchip");
484 struct drm_connector *conn;
486 mutex_lock(&drm->mode_config.mutex);
487 drm_for_each_connector(conn, drm) {
489 lcdc_type = conn->connector_type;
493 mutex_unlock(&drm->mode_config.mutex);
496 case DRM_MODE_CONNECTOR_LVDS:
497 lcdc_type = SCREEN_LVDS;
499 case DRM_MODE_CONNECTOR_DisplayPort:
500 lcdc_type = SCREEN_DP;
502 case DRM_MODE_CONNECTOR_HDMIA:
503 case DRM_MODE_CONNECTOR_HDMIB:
504 lcdc_type = SCREEN_HDMI;
506 case DRM_MODE_CONNECTOR_TV:
507 lcdc_type = SCREEN_TVOUT;
509 case DRM_MODE_CONNECTOR_eDP:
510 lcdc_type = SCREEN_EDP;
512 case DRM_MODE_CONNECTOR_DSI:
513 lcdc_type = SCREEN_MIPI;
516 lcdc_type = SCREEN_NULL;
523 static int rk3288_dmc_init(struct platform_device *pdev)
525 struct device *dev = &pdev->dev;
526 struct clk *pclk_phy, *pclk_upctl, *dmc_clk;
527 struct arm_smccc_res res;
528 struct init_params *init_param;
529 struct drm_device *drm = drm_device_get_by_name("rockchip");
533 dev_err(dev, "Get drm_device fail\n");
534 return -EPROBE_DEFER;
537 dmc_clk = devm_clk_get(dev, "dmc_clk");
538 if (IS_ERR(dmc_clk)) {
539 dev_err(dev, "Cannot get the clk dmc_clk\n");
540 return PTR_ERR(pclk_phy);
542 ret = clk_prepare_enable(dmc_clk);
544 dev_err(dev, "failed to prepare/enable dmc_clk\n");
548 pclk_phy = devm_clk_get(dev, "pclk_phy0");
549 if (IS_ERR(pclk_phy)) {
550 dev_err(dev, "Cannot get the clk pclk_phy0\n");
551 return PTR_ERR(pclk_phy);
553 ret = clk_prepare_enable(pclk_phy);
555 dev_err(dev, "failed to prepare/enable pclk_phy0\n");
558 pclk_upctl = devm_clk_get(dev, "pclk_upctl0");
559 if (IS_ERR(pclk_phy)) {
560 dev_err(dev, "Cannot get the clk pclk_upctl0\n");
561 return PTR_ERR(pclk_upctl);
563 ret = clk_prepare_enable(pclk_upctl);
565 dev_err(dev, "failed to prepare/enable pclk_upctl1\n");
569 pclk_phy = devm_clk_get(dev, "pclk_phy1");
570 if (IS_ERR(pclk_phy)) {
571 dev_err(dev, "Cannot get the clk pclk_phy1\n");
572 return PTR_ERR(pclk_phy);
574 ret = clk_prepare_enable(pclk_phy);
576 dev_err(dev, "failed to prepare/enable pclk_phy1\n");
579 pclk_upctl = devm_clk_get(dev, "pclk_upctl1");
580 if (IS_ERR(pclk_phy)) {
581 dev_err(dev, "Cannot get the clk pclk_upctl1\n");
582 return PTR_ERR(pclk_upctl);
584 ret = clk_prepare_enable(pclk_upctl);
586 dev_err(dev, "failed to prepare/enable pclk_upctl1\n");
590 res = sip_smc_request_share_mem(DIV_ROUND_UP(sizeof(
591 struct rk3288_ddr_dts_config_timing),
592 4096) + 1, SHARE_PAGE_TYPE_DDR);
594 dev_err(&pdev->dev, "no ATF memory for init\n");
598 init_param = (struct init_params *)res.a1;
599 of_get_rk3288_timings(&pdev->dev, pdev->dev.of_node,
600 (uint32_t *)init_param);
603 init_param->lcdc_type = rk_drm_get_lcdc_type();
604 res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
605 ROCKCHIP_SIP_CONFIG_DRAM_INIT);
608 dev_err(&pdev->dev, "rockchip_sip_config_dram_init error:%lx\n",
616 static int rk3368_dmc_init(struct platform_device *pdev)
618 struct device *dev = &pdev->dev;
619 struct device_node *np = pdev->dev.of_node;
620 struct arm_smccc_res res;
621 struct rk3368_dram_timing *dram_timing;
622 struct clk *pclk_phy, *pclk_upctl;
629 pclk_phy = devm_clk_get(dev, "pclk_phy");
630 if (IS_ERR(pclk_phy)) {
631 dev_err(dev, "Cannot get the clk pclk_phy\n");
632 return PTR_ERR(pclk_phy);
634 ret = clk_prepare_enable(pclk_phy);
636 dev_err(dev, "failed to prepare/enable pclk_phy\n");
639 pclk_upctl = devm_clk_get(dev, "pclk_upctl");
640 if (IS_ERR(pclk_phy)) {
641 dev_err(dev, "Cannot get the clk pclk_upctl\n");
642 return PTR_ERR(pclk_upctl);
644 ret = clk_prepare_enable(pclk_upctl);
646 dev_err(dev, "failed to prepare/enable pclk_upctl\n");
651 * Get dram timing and pass it to arm trust firmware,
652 * the dram drvier in arm trust firmware will get these
653 * timing and to do dram initial.
655 dram_timing = of_get_rk3368_timings(dev, np);
657 dram_spd_bin = dram_timing->dram_spd_bin;
658 if (scpi_ddr_send_timing((u32 *)dram_timing,
659 sizeof(struct rk3368_dram_timing)))
660 dev_err(dev, "send ddr timing timeout\n");
662 dev_err(dev, "get ddr timing from dts error\n");
663 dram_spd_bin = DDR3_DEFAULT;
666 res = sip_smc_mcu_el3fiq(FIQ_INIT_HANDLER,
669 if ((res.a0) || (res.a1 == 0) || (res.a1 > 0x80000))
670 dev_err(dev, "Trust version error, pls check trust version\n");
671 addr_mcu_el3 = res.a1;
673 if (of_property_read_u32(np, "vop-dclk-mode", &dclk_mode) == 0)
674 scpi_ddr_dclk_mode(dclk_mode);
678 if (scpi_ddr_init(dram_spd_bin, 0, lcdc_type,
680 dev_err(dev, "ddr init error\n");
682 dev_dbg(dev, ("%s out\n"), __func__);
687 static struct rk3399_dram_timing *of_get_rk3399_timings(struct device *dev,
688 struct device_node *np)
690 struct rk3399_dram_timing *timing = NULL;
691 struct device_node *np_tim;
694 np_tim = of_parse_phandle(np, "ddr_timing", 0);
696 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
700 ret = of_property_read_u32(np_tim, "ddr3_speed_bin",
701 &timing->ddr3_speed_bin);
702 ret |= of_property_read_u32(np_tim, "pd_idle",
704 ret |= of_property_read_u32(np_tim, "sr_idle",
706 ret |= of_property_read_u32(np_tim, "sr_mc_gate_idle",
707 &timing->sr_mc_gate_idle);
708 ret |= of_property_read_u32(np_tim, "srpd_lite_idle",
709 &timing->srpd_lite_idle);
710 ret |= of_property_read_u32(np_tim, "standby_idle",
711 &timing->standby_idle);
712 ret |= of_property_read_u32(np_tim, "dram_dll_dis_freq",
713 &timing->dram_dll_dis_freq);
714 ret |= of_property_read_u32(np_tim, "phy_dll_dis_freq",
715 &timing->phy_dll_dis_freq);
716 ret |= of_property_read_u32(np_tim, "ddr3_odt_dis_freq",
717 &timing->ddr3_odt_dis_freq);
718 ret |= of_property_read_u32(np_tim, "ddr3_drv",
720 ret |= of_property_read_u32(np_tim, "ddr3_odt",
722 ret |= of_property_read_u32(np_tim, "phy_ddr3_ca_drv",
723 &timing->phy_ddr3_ca_drv);
724 ret |= of_property_read_u32(np_tim, "phy_ddr3_dq_drv",
725 &timing->phy_ddr3_dq_drv);
726 ret |= of_property_read_u32(np_tim, "phy_ddr3_odt",
727 &timing->phy_ddr3_odt);
728 ret |= of_property_read_u32(np_tim, "lpddr3_odt_dis_freq",
729 &timing->lpddr3_odt_dis_freq);
730 ret |= of_property_read_u32(np_tim, "lpddr3_drv",
731 &timing->lpddr3_drv);
732 ret |= of_property_read_u32(np_tim, "lpddr3_odt",
733 &timing->lpddr3_odt);
734 ret |= of_property_read_u32(np_tim, "phy_lpddr3_ca_drv",
735 &timing->phy_lpddr3_ca_drv);
736 ret |= of_property_read_u32(np_tim, "phy_lpddr3_dq_drv",
737 &timing->phy_lpddr3_dq_drv);
738 ret |= of_property_read_u32(np_tim, "phy_lpddr3_odt",
739 &timing->phy_lpddr3_odt);
740 ret |= of_property_read_u32(np_tim, "lpddr4_odt_dis_freq",
741 &timing->lpddr4_odt_dis_freq);
742 ret |= of_property_read_u32(np_tim, "lpddr4_drv",
743 &timing->lpddr4_drv);
744 ret |= of_property_read_u32(np_tim, "lpddr4_dq_odt",
745 &timing->lpddr4_dq_odt);
746 ret |= of_property_read_u32(np_tim, "lpddr4_ca_odt",
747 &timing->lpddr4_ca_odt);
748 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ca_drv",
749 &timing->phy_lpddr4_ca_drv);
750 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ck_cs_drv",
751 &timing->phy_lpddr4_ck_cs_drv);
752 ret |= of_property_read_u32(np_tim, "phy_lpddr4_dq_drv",
753 &timing->phy_lpddr4_dq_drv);
754 ret |= of_property_read_u32(np_tim, "phy_lpddr4_odt",
755 &timing->phy_lpddr4_odt);
757 devm_kfree(dev, timing);
766 devm_kfree(dev, timing);
773 static int rk3399_dmc_init(struct platform_device *pdev)
775 struct device *dev = &pdev->dev;
776 struct device_node *np = pdev->dev.of_node;
777 struct arm_smccc_res res;
778 struct rk3399_dram_timing *dram_timing;
783 * Get dram timing and pass it to arm trust firmware,
784 * the dram drvier in arm trust firmware will get these
785 * timing and to do dram initial.
787 dram_timing = of_get_rk3399_timings(dev, np);
789 timing = (u32 *)dram_timing;
790 size = sizeof(struct rk3399_dram_timing) / 4;
791 for (index = 0; index < size; index++) {
792 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
793 ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
796 dev_err(dev, "Failed to set dram param: %ld\n",
803 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
804 ROCKCHIP_SIP_CONFIG_DRAM_INIT,
810 static const struct of_device_id rockchip_dmcfreq_of_match[] = {
811 { .compatible = "rockchip,rk3288-dmc", .data = rk3288_dmc_init },
812 { .compatible = "rockchip,rk3368-dmc", .data = rk3368_dmc_init },
813 { .compatible = "rockchip,rk3399-dmc", .data = rk3399_dmc_init },
816 MODULE_DEVICE_TABLE(of, rockchip_dmcfreq_of_match);
818 static int rockchip_dmcfreq_probe(struct platform_device *pdev)
820 struct device *dev = &pdev->dev;
821 struct device_node *np = pdev->dev.of_node;
822 struct rockchip_dmcfreq *data;
823 struct devfreq_dev_profile *devp = &rockchip_devfreq_dmc_profile;
824 const struct of_device_id *match;
825 int (*init)(struct platform_device *pdev,
826 struct rockchip_dmcfreq *data);
829 data = devm_kzalloc(dev, sizeof(struct rockchip_dmcfreq), GFP_KERNEL);
833 mutex_init(&data->lock);
835 data->vdd_center = devm_regulator_get(dev, "center");
836 if (IS_ERR(data->vdd_center)) {
837 dev_err(dev, "Cannot get the regulator \"center\"\n");
838 return PTR_ERR(data->vdd_center);
841 data->dmc_clk = devm_clk_get(dev, "dmc_clk");
842 if (IS_ERR(data->dmc_clk)) {
843 dev_err(dev, "Cannot get the clk dmc_clk\n");
844 return PTR_ERR(data->dmc_clk);
847 data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
848 if (IS_ERR(data->edev))
849 return -EPROBE_DEFER;
851 ret = devfreq_event_enable_edev(data->edev);
853 dev_err(dev, "failed to enable devfreq-event devices\n");
857 match = of_match_node(rockchip_dmcfreq_of_match, pdev->dev.of_node);
861 ret = init(pdev, data);
868 * We add a devfreq driver to our parent since it has a device tree node
869 * with operating points.
871 if (dev_pm_opp_of_add_table(dev)) {
872 dev_err(dev, "Invalid operating-points in device tree.\n");
876 if (rockchip_dmcfreq_init_freq_table(dev, devp))
879 of_property_read_u32(np, "upthreshold",
880 &data->ondemand_data.upthreshold);
881 of_property_read_u32(np, "downdifferential",
882 &data->ondemand_data.downdifferential);
884 data->rate = clk_get_rate(data->dmc_clk);
885 data->volt = regulator_get_voltage(data->vdd_center);
887 devp->initial_freq = data->rate;
888 data->devfreq = devm_devfreq_add_device(dev, devp,
890 &data->ondemand_data);
891 if (IS_ERR(data->devfreq))
892 return PTR_ERR(data->devfreq);
893 devm_devfreq_register_opp_notifier(dev, data->devfreq);
895 data->devfreq->min_freq = devp->freq_table[0];
896 data->devfreq->max_freq =
897 devp->freq_table[devp->max_state ? devp->max_state - 1 : 0];
900 platform_set_drvdata(pdev, data);
902 if (rockchip_drm_register_notifier_to_dmc(data->devfreq))
903 dev_err(dev, "drm fail to register notifier to dmc\n");
905 if (rockchip_pm_register_notify_to_dmc(data->devfreq))
906 dev_err(dev, "pd fail to register notify to dmc\n");
908 if (vop_register_dmc())
909 dev_err(dev, "fail to register notify to vop.\n");
914 static struct platform_driver rockchip_dmcfreq_driver = {
915 .probe = rockchip_dmcfreq_probe,
917 .name = "rockchip-dmc",
918 .pm = &rockchip_dmcfreq_pm,
919 .of_match_table = rockchip_dmcfreq_of_match,
922 module_platform_driver(rockchip_dmcfreq_driver);
924 MODULE_LICENSE("GPL v2");
925 MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
926 MODULE_DESCRIPTION("rockchip dmcfreq driver with devfreq framework");