drivers/devfreq/rockchip_dmc.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
   3  * Author: Lin Huang <hl@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <dt-bindings/clock/rockchip-ddr.h>
  16 #include <linux/arm-smccc.h>
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/devfreq.h>
  20 #include <linux/devfreq-event.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_opp.h>
  26 #include <linux/regulator/consumer.h>
  27 #include <linux/rockchip/rockchip_sip.h>
  28 #include <linux/rwsem.h>
  29 #include <linux/slab.h>
  30 #include <linux/suspend.h>
  31
  32 #include <soc/rockchip/rkfb_dmc.h>
  33 #include <soc/rockchip/rockchip_dmc.h>
  34 #include <soc/rockchip/rockchip_sip.h>
  35 #include <soc/rockchip/scpi.h>
  36
  37 #define FIQ_INIT_HANDLER        (0x1)
  38 #define FIQ_CPU_TGT_BOOT        (0x0) /* to booting cpu */
  39 #define FIQ_NUM_FOR_DCF         (143) /* NA irq map to fiq for dcf */
  40
  41 struct rk3368_dram_timing {
  42         u32 dram_spd_bin;
  43         u32 sr_idle;
  44         u32 pd_idle;
  45         u32 dram_dll_dis_freq;
  46         u32 phy_dll_dis_freq;
  47         u32 dram_odt_dis_freq;
  48         u32 phy_odt_dis_freq;
  49         u32 ddr3_drv;
  50         u32 ddr3_odt;
  51         u32 lpddr3_drv;
  52         u32 lpddr3_odt;
  53         u32 lpddr2_drv;
  54         u32 phy_clk_drv;
  55         u32 phy_cmd_drv;
  56         u32 phy_dqs_drv;
  57         u32 phy_odt;
  58 };
  59
  60 struct rk3399_dram_timing {
  61         unsigned int ddr3_speed_bin;
  62         unsigned int pd_idle;
  63         unsigned int sr_idle;
  64         unsigned int sr_mc_gate_idle;
  65         unsigned int srpd_lite_idle;
  66         unsigned int standby_idle;
  67         unsigned int dram_dll_dis_freq;
  68         unsigned int phy_dll_dis_freq;
  69         unsigned int ddr3_odt_dis_freq;
  70         unsigned int ddr3_drv;
  71         unsigned int ddr3_odt;
  72         unsigned int phy_ddr3_ca_drv;
  73         unsigned int phy_ddr3_dq_drv;
  74         unsigned int phy_ddr3_odt;
  75         unsigned int lpddr3_odt_dis_freq;
  76         unsigned int lpddr3_drv;
  77         unsigned int lpddr3_odt;
  78         unsigned int phy_lpddr3_ca_drv;
  79         unsigned int phy_lpddr3_dq_drv;
  80         unsigned int phy_lpddr3_odt;
  81         unsigned int lpddr4_odt_dis_freq;
  82         unsigned int lpddr4_drv;
  83         unsigned int lpddr4_dq_odt;
  84         unsigned int lpddr4_ca_odt;
  85         unsigned int phy_lpddr4_ca_drv;
  86         unsigned int phy_lpddr4_ck_cs_drv;
  87         unsigned int phy_lpddr4_dq_drv;
  88         unsigned int phy_lpddr4_odt;
  89 };
  90
  91 struct rockchip_dmcfreq {
  92         struct device *dev;
  93         struct devfreq *devfreq;
  94         struct devfreq_simple_ondemand_data ondemand_data;
  95         struct clk *dmc_clk;
  96         struct devfreq_event_dev *edev;
  97         struct mutex lock; /* scaling frequency lock */
  98         struct dram_timing *timing;
  99         struct regulator *vdd_center;
 100         unsigned long rate, target_rate;
 101         unsigned long volt, target_volt;
 102 };
 103
 104 static int rockchip_dmcfreq_target(struct device *dev, unsigned long *freq,
 105                                    u32 flags)
 106 {
 107         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 108         struct dev_pm_opp *opp;
 109         unsigned long old_clk_rate = dmcfreq->rate;
 110         unsigned long temp_rate, target_volt, target_rate;
 111         int err;
 112
 113         rcu_read_lock();
 114         opp = devfreq_recommended_opp(dev, freq, flags);
 115         if (IS_ERR(opp)) {
 116                 rcu_read_unlock();
 117                 return PTR_ERR(opp);
 118         }
 119
 120         temp_rate = dev_pm_opp_get_freq(opp);
 121         target_rate = clk_round_rate(dmcfreq->dmc_clk, temp_rate);
 122         if ((long)target_rate <= 0)
 123                 target_rate = temp_rate;
 124         target_volt = dev_pm_opp_get_voltage(opp);
 125
 126         rcu_read_unlock();
 127
 128         if (dmcfreq->rate == target_rate) {
 129                 if (dmcfreq->volt == target_volt)
 130                         return 0;
 131                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 132                                             INT_MAX);
 133                 if (err) {
 134                         dev_err(dev, "Cannot set voltage %lu uV\n",
 135                                 target_volt);
 136                         goto out;
 137                 }
 138         }
 139
 140         mutex_lock(&dmcfreq->lock);
 141
 142         /*
 143          * If frequency scaling from low to high, adjust voltage first.
 144          * If frequency scaling from high to low, adjust frequency first.
 145          */
 146         if (old_clk_rate < target_rate) {
 147                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 148                                             INT_MAX);
 149                 if (err) {
 150                         dev_err(dev, "Cannot set voltage %lu uV\n",
 151                                 target_volt);
 152                         goto out;
 153                 }
 154         }
 155
 156         err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
 157         if (err) {
 158                 dev_err(dev, "Cannot set frequency %lu (%d)\n",
 159                         target_rate, err);
 160                 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
 161                                       INT_MAX);
 162                 goto out;
 163         }
 164
 165         /*
 166          * Check the dpll rate,
 167          * There only two result we will get,
 168          * 1. Ddr frequency scaling fail, we still get the old rate.
 169          * 2. Ddr frequency scaling sucessful, we get the rate we set.
 170          */
 171         dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
 172
 173         /* If get the incorrect rate, set voltage to old value. */
 174         if (dmcfreq->rate != target_rate) {
 175                 dev_err(dev, "Get wrong frequency, Request %lu, Current %lu\n",
 176                         target_rate, dmcfreq->rate);
 177                 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
 178                                       INT_MAX);
 179                 goto out;
 180         } else if (old_clk_rate > target_rate) {
 181                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 182                                             INT_MAX);
 183                 if (err) {
 184                         dev_err(dev, "Cannot set vol %lu uV\n", target_volt);
 185                         goto out;
 186                 }
 187         }
 188
 189         dmcfreq->volt = target_volt;
 190 out:
 191         mutex_unlock(&dmcfreq->lock);
 192         return err;
 193 }
 194
 195 static int rockchip_dmcfreq_get_dev_status(struct device *dev,
 196                                            struct devfreq_dev_status *stat)
 197 {
 198         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 199         struct devfreq_event_data edata;
 200         int ret = 0;
 201
 202         ret = devfreq_event_get_event(dmcfreq->edev, &edata);
 203         if (ret < 0)
 204                 return ret;
 205
 206         stat->current_frequency = dmcfreq->rate;
 207         stat->busy_time = edata.load_count;
 208         stat->total_time = edata.total_count;
 209
 210         return ret;
 211 }
 212
 213 static int rockchip_dmcfreq_get_cur_freq(struct device *dev,
 214                                          unsigned long *freq)
 215 {
 216         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 217
 218         *freq = dmcfreq->rate;
 219
 220         return 0;
 221 }
 222
 223 static struct devfreq_dev_profile rockchip_devfreq_dmc_profile = {
 224         .polling_ms     = 50,
 225         .target         = rockchip_dmcfreq_target,
 226         .get_dev_status = rockchip_dmcfreq_get_dev_status,
 227         .get_cur_freq   = rockchip_dmcfreq_get_cur_freq,
 228 };
 229
 230 static __maybe_unused int rockchip_dmcfreq_suspend(struct device *dev)
 231 {
 232         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 233         int ret = 0;
 234
 235         ret = devfreq_event_disable_edev(dmcfreq->edev);
 236         if (ret < 0) {
 237                 dev_err(dev, "failed to disable the devfreq-event devices\n");
 238                 return ret;
 239         }
 240
 241         ret = devfreq_suspend_device(dmcfreq->devfreq);
 242         if (ret < 0) {
 243                 dev_err(dev, "failed to suspend the devfreq devices\n");
 244                 return ret;
 245         }
 246
 247         return 0;
 248 }
 249
 250 static __maybe_unused int rockchip_dmcfreq_resume(struct device *dev)
 251 {
 252         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 253         int ret = 0;
 254
 255         ret = devfreq_event_enable_edev(dmcfreq->edev);
 256         if (ret < 0) {
 257                 dev_err(dev, "failed to enable the devfreq-event devices\n");
 258                 return ret;
 259         }
 260
 261         ret = devfreq_resume_device(dmcfreq->devfreq);
 262         if (ret < 0) {
 263                 dev_err(dev, "failed to resume the devfreq devices\n");
 264                 return ret;
 265         }
 266         return ret;
 267 }
 268
 269 static SIMPLE_DEV_PM_OPS(rockchip_dmcfreq_pm, rockchip_dmcfreq_suspend,
 270                          rockchip_dmcfreq_resume);
 271
 272 static int rockchip_dmcfreq_init_freq_table(struct device *dev,
 273                                             struct devfreq_dev_profile *devp)
 274 {
 275         int count;
 276         int i = 0;
 277         unsigned long freq = 0;
 278         struct dev_pm_opp *opp;
 279
 280         rcu_read_lock();
 281         count = dev_pm_opp_get_opp_count(dev);
 282         if (count < 0) {
 283                 rcu_read_unlock();
 284                 return count;
 285         }
 286         rcu_read_unlock();
 287
 288         devp->freq_table = kmalloc_array(count, sizeof(devp->freq_table[0]),
 289                                 GFP_KERNEL);
 290         if (!devp->freq_table)
 291                 return -ENOMEM;
 292
 293         rcu_read_lock();
 294         for (i = 0; i < count; i++, freq++) {
 295                 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
 296                 if (IS_ERR(opp))
 297                         break;
 298
 299                 devp->freq_table[i] = freq;
 300         }
 301         rcu_read_unlock();
 302
 303         if (count != i)
 304                 dev_warn(dev, "Unable to enumerate all OPPs (%d!=%d)\n",
 305                          count, i);
 306
 307         devp->max_state = i;
 308         return 0;
 309 }
 310
 311 static struct rk3368_dram_timing *of_get_rk3368_timings(struct device *dev,
 312                                                         struct device_node *np)
 313 {
 314         struct rk3368_dram_timing *timing = NULL;
 315         struct device_node *np_tim;
 316         int ret;
 317
 318         np_tim = of_parse_phandle(np, "ddr_timing", 0);
 319         if (np_tim) {
 320                 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
 321                 if (!timing)
 322                         goto err;
 323
 324                 ret |= of_property_read_u32(np_tim, "dram_spd_bin",
 325                                             &timing->dram_spd_bin);
 326                 ret |= of_property_read_u32(np_tim, "sr_idle",
 327                                             &timing->sr_idle);
 328                 ret |= of_property_read_u32(np_tim, "pd_idle",
 329                                             &timing->pd_idle);
 330                 ret |= of_property_read_u32(np_tim, "dram_dll_disb_freq",
 331                                             &timing->dram_dll_dis_freq);
 332                 ret |= of_property_read_u32(np_tim, "phy_dll_disb_freq",
 333                                             &timing->phy_dll_dis_freq);
 334                 ret |= of_property_read_u32(np_tim, "dram_odt_disb_freq",
 335                                             &timing->dram_odt_dis_freq);
 336                 ret |= of_property_read_u32(np_tim, "phy_odt_disb_freq",
 337                                             &timing->phy_odt_dis_freq);
 338                 ret |= of_property_read_u32(np_tim, "ddr3_drv",
 339                                             &timing->ddr3_drv);
 340                 ret |= of_property_read_u32(np_tim, "ddr3_odt",
 341                                             &timing->ddr3_odt);
 342                 ret |= of_property_read_u32(np_tim, "lpddr3_drv",
 343                                             &timing->lpddr3_drv);
 344                 ret |= of_property_read_u32(np_tim, "lpddr3_odt",
 345                                             &timing->lpddr3_odt);
 346                 ret |= of_property_read_u32(np_tim, "lpddr2_drv",
 347                                             &timing->lpddr2_drv);
 348                 ret |= of_property_read_u32(np_tim, "phy_clk_drv",
 349                                             &timing->phy_clk_drv);
 350                 ret |= of_property_read_u32(np_tim, "phy_cmd_drv",
 351                                             &timing->phy_cmd_drv);
 352                 ret |= of_property_read_u32(np_tim, "phy_dqs_drv",
 353                                             &timing->phy_dqs_drv);
 354                 ret |= of_property_read_u32(np_tim, "phy_odt",
 355                                             &timing->phy_odt);
 356                 if (ret) {
 357                         devm_kfree(dev, timing);
 358                         goto err;
 359                 }
 360                 of_node_put(np_tim);
 361                 return timing;
 362         }
 363
 364 err:
 365         if (timing) {
 366                 devm_kfree(dev, timing);
 367                 timing = NULL;
 368         }
 369         of_node_put(np_tim);
 370         return timing;
 371 }
 372
 373 static int rk3368_dmc_init(struct platform_device *pdev)
 374 {
 375         struct device *dev = &pdev->dev;
 376         struct device_node *np = pdev->dev.of_node;
 377         struct arm_smccc_res res;
 378         struct rk3368_dram_timing *dram_timing;
 379         struct clk *pclk_phy, *pclk_upctl;
 380         int ret;
 381         u32 dram_spd_bin;
 382         u32 addr_mcu_el3;
 383         u32 dclk_mode;
 384         u32 lcdc_type;
 385
 386         pclk_phy = devm_clk_get(dev, "pclk_phy");
 387         if (IS_ERR(pclk_phy)) {
 388                 dev_err(dev, "Cannot get the clk pclk_phy\n");
 389                 return PTR_ERR(pclk_phy);
 390         };
 391         ret = clk_prepare_enable(pclk_phy);
 392         if (ret < 0) {
 393                 dev_err(dev, "failed to prepare/enable pclk_phy\n");
 394                 return ret;
 395         }
 396         pclk_upctl = devm_clk_get(dev, "pclk_upctl");
 397         if (IS_ERR(pclk_phy)) {
 398                 dev_err(dev, "Cannot get the clk pclk_upctl\n");
 399                 return PTR_ERR(pclk_upctl);
 400         };
 401         ret = clk_prepare_enable(pclk_upctl);
 402         if (ret < 0) {
 403                 dev_err(dev, "failed to prepare/enable pclk_upctl\n");
 404                 return ret;
 405         }
 406
 407         /*
 408          * Get dram timing and pass it to arm trust firmware,
 409          * the dram drvier in arm trust firmware will get these
 410          * timing and to do dram initial.
 411          */
 412         dram_timing = of_get_rk3368_timings(dev, np);
 413         if (dram_timing) {
 414                 dram_spd_bin = dram_timing->dram_spd_bin;
 415                 if (scpi_ddr_send_timing((u32 *)dram_timing,
 416                                          sizeof(struct rk3368_dram_timing)))
 417                         dev_err(dev, "send ddr timing timeout\n");
 418         } else {
 419                 dev_err(dev, "get ddr timing from dts error\n");
 420                 dram_spd_bin = DDR3_DEFAULT;
 421         }
 422
 423         res = sip_smc_mcu_el3fiq(FIQ_INIT_HANDLER,
 424                                  FIQ_NUM_FOR_DCF,
 425                                  FIQ_CPU_TGT_BOOT);
 426         if ((res.a0) || (res.a1 == 0) || (res.a1 > 0x80000))
 427                 dev_err(dev, "Trust version error, pls check trust version\n");
 428         addr_mcu_el3 = res.a1;
 429
 430         if (of_property_read_u32(np, "vop-dclk-mode", &dclk_mode) == 0)
 431                 scpi_ddr_dclk_mode(dclk_mode);
 432
 433         lcdc_type = 7;
 434
 435         if (scpi_ddr_init(dram_spd_bin, 0, lcdc_type,
 436                           addr_mcu_el3))
 437                 dev_err(dev, "ddr init error\n");
 438         else
 439                 dev_dbg(dev, ("%s out\n"), __func__);
 440
 441         return 0;
 442 }
 443
 444 static struct rk3399_dram_timing *of_get_rk3399_timings(struct device *dev,
 445                                                         struct device_node *np)
 446 {
 447         struct rk3399_dram_timing *timing = NULL;
 448         struct device_node *np_tim;
 449         int ret;
 450
 451         np_tim = of_parse_phandle(np, "ddr_timing", 0);
 452         if (np_tim) {
 453                 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
 454                 if (!timing)
 455                         goto err;
 456
 457                 ret = of_property_read_u32(np_tim, "ddr3_speed_bin",
 458                                            &timing->ddr3_speed_bin);
 459                 ret |= of_property_read_u32(np_tim, "pd_idle",
 460                                             &timing->pd_idle);
 461                 ret |= of_property_read_u32(np_tim, "sr_idle",
 462                                             &timing->sr_idle);
 463                 ret |= of_property_read_u32(np_tim, "sr_mc_gate_idle",
 464                                             &timing->sr_mc_gate_idle);
 465                 ret |= of_property_read_u32(np_tim, "srpd_lite_idle",
 466                                             &timing->srpd_lite_idle);
 467                 ret |= of_property_read_u32(np_tim, "standby_idle",
 468                                             &timing->standby_idle);
 469                 ret |= of_property_read_u32(np_tim, "dram_dll_dis_freq",
 470                                             &timing->dram_dll_dis_freq);
 471                 ret |= of_property_read_u32(np_tim, "phy_dll_dis_freq",
 472                                             &timing->phy_dll_dis_freq);
 473                 ret |= of_property_read_u32(np_tim, "ddr3_odt_dis_freq",
 474                                             &timing->ddr3_odt_dis_freq);
 475                 ret |= of_property_read_u32(np_tim, "ddr3_drv",
 476                                             &timing->ddr3_drv);
 477                 ret |= of_property_read_u32(np_tim, "ddr3_odt",
 478                                             &timing->ddr3_odt);
 479                 ret |= of_property_read_u32(np_tim, "phy_ddr3_ca_drv",
 480                                             &timing->phy_ddr3_ca_drv);
 481                 ret |= of_property_read_u32(np_tim, "phy_ddr3_dq_drv",
 482                                             &timing->phy_ddr3_dq_drv);
 483                 ret |= of_property_read_u32(np_tim, "phy_ddr3_odt",
 484                                             &timing->phy_ddr3_odt);
 485                 ret |= of_property_read_u32(np_tim, "lpddr3_odt_dis_freq",
 486                                             &timing->lpddr3_odt_dis_freq);
 487                 ret |= of_property_read_u32(np_tim, "lpddr3_drv",
 488                                             &timing->lpddr3_drv);
 489                 ret |= of_property_read_u32(np_tim, "lpddr3_odt",
 490                                             &timing->lpddr3_odt);
 491                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_ca_drv",
 492                                             &timing->phy_lpddr3_ca_drv);
 493                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_dq_drv",
 494                                             &timing->phy_lpddr3_dq_drv);
 495                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_odt",
 496                                             &timing->phy_lpddr3_odt);
 497                 ret |= of_property_read_u32(np_tim, "lpddr4_odt_dis_freq",
 498                                             &timing->lpddr4_odt_dis_freq);
 499                 ret |= of_property_read_u32(np_tim, "lpddr4_drv",
 500                                             &timing->lpddr4_drv);
 501                 ret |= of_property_read_u32(np_tim, "lpddr4_dq_odt",
 502                                             &timing->lpddr4_dq_odt);
 503                 ret |= of_property_read_u32(np_tim, "lpddr4_ca_odt",
 504                                             &timing->lpddr4_ca_odt);
 505                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ca_drv",
 506                                             &timing->phy_lpddr4_ca_drv);
 507                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ck_cs_drv",
 508                                             &timing->phy_lpddr4_ck_cs_drv);
 509                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_dq_drv",
 510                                             &timing->phy_lpddr4_dq_drv);
 511                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_odt",
 512                                             &timing->phy_lpddr4_odt);
 513                 if (ret) {
 514                         devm_kfree(dev, timing);
 515                         goto err;
 516                 }
 517                 of_node_put(np_tim);
 518                 return timing;
 519         }
 520
 521 err:
 522         if (timing) {
 523                 devm_kfree(dev, timing);
 524                 timing = NULL;
 525         }
 526         of_node_put(np_tim);
 527         return timing;
 528 }
 529
 530 static int rk3399_dmc_init(struct platform_device *pdev)
 531 {
 532         struct device *dev = &pdev->dev;
 533         struct device_node *np = pdev->dev.of_node;
 534         struct arm_smccc_res res;
 535         struct rk3399_dram_timing *dram_timing;
 536         int index, size;
 537         u32 *timing;
 538
 539         /*
 540          * Get dram timing and pass it to arm trust firmware,
 541          * the dram drvier in arm trust firmware will get these
 542          * timing and to do dram initial.
 543          */
 544         dram_timing = of_get_rk3399_timings(dev, np);
 545         if (dram_timing) {
 546                 timing = (u32 *)dram_timing;
 547                 size = sizeof(struct rk3399_dram_timing) / 4;
 548                 for (index = 0; index < size; index++) {
 549                         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
 550                                       ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
 551                                       0, 0, 0, 0, &res);
 552                         if (res.a0) {
 553                                 dev_err(dev, "Failed to set dram param: %ld\n",
 554                                         res.a0);
 555                                 return -EINVAL;
 556                         }
 557                 }
 558         }
 559
 560         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
 561                       ROCKCHIP_SIP_CONFIG_DRAM_INIT,
 562                       0, 0, 0, 0, &res);
 563
 564         return 0;
 565 }
 566
 567 static const struct of_device_id rockchip_dmcfreq_of_match[] = {
 568         { .compatible = "rockchip,rk3368-dmc", .data = rk3368_dmc_init },
 569         { .compatible = "rockchip,rk3399-dmc", .data = rk3399_dmc_init },
 570         { },
 571 };
 572 MODULE_DEVICE_TABLE(of, rockchip_dmcfreq_of_match);
 573
 574 static int rockchip_dmcfreq_probe(struct platform_device *pdev)
 575 {
 576         struct device *dev = &pdev->dev;
 577         struct device_node *np = pdev->dev.of_node;
 578         struct rockchip_dmcfreq *data;
 579         struct devfreq_dev_profile *devp = &rockchip_devfreq_dmc_profile;
 580         const struct of_device_id *match;
 581         int (*init)(struct platform_device *pdev,
 582                     struct rockchip_dmcfreq *data);
 583         int ret;
 584
 585         data = devm_kzalloc(dev, sizeof(struct rockchip_dmcfreq), GFP_KERNEL);
 586         if (!data)
 587                 return -ENOMEM;
 588
 589         mutex_init(&data->lock);
 590
 591         data->vdd_center = devm_regulator_get(dev, "center");
 592         if (IS_ERR(data->vdd_center)) {
 593                 dev_err(dev, "Cannot get the regulator \"center\"\n");
 594                 return PTR_ERR(data->vdd_center);
 595         }
 596
 597         data->dmc_clk = devm_clk_get(dev, "dmc_clk");
 598         if (IS_ERR(data->dmc_clk)) {
 599                 dev_err(dev, "Cannot get the clk dmc_clk\n");
 600                 return PTR_ERR(data->dmc_clk);
 601         };
 602
 603         data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
 604         if (IS_ERR(data->edev))
 605                 return -EPROBE_DEFER;
 606
 607         ret = devfreq_event_enable_edev(data->edev);
 608         if (ret < 0) {
 609                 dev_err(dev, "failed to enable devfreq-event devices\n");
 610                 return ret;
 611         }
 612
 613         match = of_match_node(rockchip_dmcfreq_of_match, pdev->dev.of_node);
 614         if (match) {
 615                 init = match->data;
 616                 if (init) {
 617                         if (init(pdev, data))
 618                                 return -EINVAL;
 619                 }
 620         }
 621
 622         /*
 623          * We add a devfreq driver to our parent since it has a device tree node
 624          * with operating points.
 625          */
 626         if (dev_pm_opp_of_add_table(dev)) {
 627                 dev_err(dev, "Invalid operating-points in device tree.\n");
 628                 return -EINVAL;
 629         }
 630
 631         if (rockchip_dmcfreq_init_freq_table(dev, devp))
 632                 return -EFAULT;
 633
 634         of_property_read_u32(np, "upthreshold",
 635                              &data->ondemand_data.upthreshold);
 636         of_property_read_u32(np, "downdifferential",
 637                              &data->ondemand_data.downdifferential);
 638
 639         data->rate = clk_get_rate(data->dmc_clk);
 640         data->volt = regulator_get_voltage(data->vdd_center);
 641
 642         devp->initial_freq = data->rate;
 643         data->devfreq = devm_devfreq_add_device(dev, devp,
 644                                            "simple_ondemand",
 645                                            &data->ondemand_data);
 646         if (IS_ERR(data->devfreq))
 647                 return PTR_ERR(data->devfreq);
 648         devm_devfreq_register_opp_notifier(dev, data->devfreq);
 649
 650         data->devfreq->min_freq = devp->freq_table[0];
 651         data->devfreq->max_freq =
 652                 devp->freq_table[devp->max_state ? devp->max_state - 1 : 0];
 653
 654         data->dev = dev;
 655         platform_set_drvdata(pdev, data);
 656
 657         if (rockchip_pm_register_notify_to_dmc(data->devfreq))
 658                 dev_err(dev, "pd fail to register notify to dmc\n");
 659
 660         if (vop_register_dmc())
 661                 dev_err(dev, "fail to register notify to vop.\n");
 662
 663         return 0;
 664 }
 665
 666 static struct platform_driver rockchip_dmcfreq_driver = {
 667         .probe  = rockchip_dmcfreq_probe,
 668         .driver = {
 669                 .name   = "rockchip-dmc",
 670                 .pm     = &rockchip_dmcfreq_pm,
 671                 .of_match_table = rockchip_dmcfreq_of_match,
 672         },
 673 };
 674 module_platform_driver(rockchip_dmcfreq_driver);
 675
 676 MODULE_LICENSE("GPL v2");
 677 MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
 678 MODULE_DESCRIPTION("rockchip dmcfreq driver with devfreq framework");