drivers/devfreq/rockchip_dmc.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
   3  * Author: Lin Huang <hl@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <dt-bindings/clock/rockchip-ddr.h>
  16 #include <linux/arm-smccc.h>
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/devfreq.h>
  20 #include <linux/devfreq-event.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_opp.h>
  26 #include <linux/regulator/consumer.h>
  27 #include <linux/rockchip/rockchip_sip.h>
  28 #include <linux/rwsem.h>
  29 #include <linux/slab.h>
  30 #include <linux/suspend.h>
  31
  32 #include <soc/rockchip/rkfb_dmc.h>
  33 #include <soc/rockchip/rockchip_sip.h>
  34 #include <soc/rockchip/scpi.h>
  35
  36 #define FIQ_INIT_HANDLER        (0x1)
  37 #define FIQ_CPU_TGT_BOOT        (0x0) /* to booting cpu */
  38 #define FIQ_NUM_FOR_DCF         (143) /* NA irq map to fiq for dcf */
  39
  40 struct rk3368_dram_timing {
  41         u32 dram_spd_bin;
  42         u32 sr_idle;
  43         u32 pd_idle;
  44         u32 dram_dll_dis_freq;
  45         u32 phy_dll_dis_freq;
  46         u32 dram_odt_dis_freq;
  47         u32 phy_odt_dis_freq;
  48         u32 ddr3_drv;
  49         u32 ddr3_odt;
  50         u32 lpddr3_drv;
  51         u32 lpddr3_odt;
  52         u32 lpddr2_drv;
  53         u32 phy_clk_drv;
  54         u32 phy_cmd_drv;
  55         u32 phy_dqs_drv;
  56         u32 phy_odt;
  57 };
  58
  59 struct rk3399_dram_timing {
  60         unsigned int ddr3_speed_bin;
  61         unsigned int pd_idle;
  62         unsigned int sr_idle;
  63         unsigned int sr_mc_gate_idle;
  64         unsigned int srpd_lite_idle;
  65         unsigned int standby_idle;
  66         unsigned int dram_dll_dis_freq;
  67         unsigned int phy_dll_dis_freq;
  68         unsigned int ddr3_odt_dis_freq;
  69         unsigned int ddr3_drv;
  70         unsigned int ddr3_odt;
  71         unsigned int phy_ddr3_ca_drv;
  72         unsigned int phy_ddr3_dq_drv;
  73         unsigned int phy_ddr3_odt;
  74         unsigned int lpddr3_odt_dis_freq;
  75         unsigned int lpddr3_drv;
  76         unsigned int lpddr3_odt;
  77         unsigned int phy_lpddr3_ca_drv;
  78         unsigned int phy_lpddr3_dq_drv;
  79         unsigned int phy_lpddr3_odt;
  80         unsigned int lpddr4_odt_dis_freq;
  81         unsigned int lpddr4_drv;
  82         unsigned int lpddr4_dq_odt;
  83         unsigned int lpddr4_ca_odt;
  84         unsigned int phy_lpddr4_ca_drv;
  85         unsigned int phy_lpddr4_ck_cs_drv;
  86         unsigned int phy_lpddr4_dq_drv;
  87         unsigned int phy_lpddr4_odt;
  88 };
  89
  90 struct rockchip_dmcfreq {
  91         struct device *dev;
  92         struct devfreq *devfreq;
  93         struct devfreq_simple_ondemand_data ondemand_data;
  94         struct clk *dmc_clk;
  95         struct devfreq_event_dev *edev;
  96         struct mutex lock; /* scaling frequency lock */
  97         struct dram_timing *timing;
  98         struct regulator *vdd_center;
  99         unsigned long rate, target_rate;
 100         unsigned long volt, target_volt;
 101 };
 102
 103 static int rockchip_dmcfreq_target(struct device *dev, unsigned long *freq,
 104                                    u32 flags)
 105 {
 106         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 107         struct dev_pm_opp *opp;
 108         unsigned long old_clk_rate = dmcfreq->rate;
 109         unsigned long temp_rate, target_volt, target_rate;
 110         int err;
 111
 112         rcu_read_lock();
 113         opp = devfreq_recommended_opp(dev, freq, flags);
 114         if (IS_ERR(opp)) {
 115                 rcu_read_unlock();
 116                 return PTR_ERR(opp);
 117         }
 118
 119         temp_rate = dev_pm_opp_get_freq(opp);
 120         target_rate = clk_round_rate(dmcfreq->dmc_clk, temp_rate);
 121         if ((long)target_rate <= 0)
 122                 target_rate = temp_rate;
 123         target_volt = dev_pm_opp_get_voltage(opp);
 124
 125         rcu_read_unlock();
 126
 127         if (dmcfreq->rate == target_rate) {
 128                 if (dmcfreq->volt == target_volt)
 129                         return 0;
 130                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 131                                             INT_MAX);
 132                 if (err) {
 133                         dev_err(dev, "Cannot set voltage %lu uV\n",
 134                                 target_volt);
 135                         goto out;
 136                 }
 137         }
 138
 139         mutex_lock(&dmcfreq->lock);
 140
 141         /*
 142          * If frequency scaling from low to high, adjust voltage first.
 143          * If frequency scaling from high to low, adjust frequency first.
 144          */
 145         if (old_clk_rate < target_rate) {
 146                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 147                                             INT_MAX);
 148                 if (err) {
 149                         dev_err(dev, "Cannot set voltage %lu uV\n",
 150                                 target_volt);
 151                         goto out;
 152                 }
 153         }
 154
 155         err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
 156         if (err) {
 157                 dev_err(dev, "Cannot set frequency %lu (%d)\n",
 158                         target_rate, err);
 159                 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
 160                                       INT_MAX);
 161                 goto out;
 162         }
 163
 164         /*
 165          * Check the dpll rate,
 166          * There only two result we will get,
 167          * 1. Ddr frequency scaling fail, we still get the old rate.
 168          * 2. Ddr frequency scaling sucessful, we get the rate we set.
 169          */
 170         dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
 171
 172         /* If get the incorrect rate, set voltage to old value. */
 173         if (dmcfreq->rate != target_rate) {
 174                 dev_err(dev, "Get wrong frequency, Request %lu, Current %lu\n",
 175                         target_rate, dmcfreq->rate);
 176                 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
 177                                       INT_MAX);
 178                 goto out;
 179         } else if (old_clk_rate > target_rate) {
 180                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 181                                             INT_MAX);
 182                 if (err) {
 183                         dev_err(dev, "Cannot set vol %lu uV\n", target_volt);
 184                         goto out;
 185                 }
 186         }
 187
 188         dmcfreq->volt = target_volt;
 189 out:
 190         mutex_unlock(&dmcfreq->lock);
 191         return err;
 192 }
 193
 194 static int rockchip_dmcfreq_get_dev_status(struct device *dev,
 195                                            struct devfreq_dev_status *stat)
 196 {
 197         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 198         struct devfreq_event_data edata;
 199         int ret = 0;
 200
 201         ret = devfreq_event_get_event(dmcfreq->edev, &edata);
 202         if (ret < 0)
 203                 return ret;
 204
 205         stat->current_frequency = dmcfreq->rate;
 206         stat->busy_time = edata.load_count;
 207         stat->total_time = edata.total_count;
 208
 209         return ret;
 210 }
 211
 212 static int rockchip_dmcfreq_get_cur_freq(struct device *dev,
 213                                          unsigned long *freq)
 214 {
 215         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 216
 217         *freq = dmcfreq->rate;
 218
 219         return 0;
 220 }
 221
 222 static struct devfreq_dev_profile rockchip_devfreq_dmc_profile = {
 223         .polling_ms     = 50,
 224         .target         = rockchip_dmcfreq_target,
 225         .get_dev_status = rockchip_dmcfreq_get_dev_status,
 226         .get_cur_freq   = rockchip_dmcfreq_get_cur_freq,
 227 };
 228
 229 static __maybe_unused int rockchip_dmcfreq_suspend(struct device *dev)
 230 {
 231         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 232         int ret = 0;
 233
 234         ret = devfreq_event_disable_edev(dmcfreq->edev);
 235         if (ret < 0) {
 236                 dev_err(dev, "failed to disable the devfreq-event devices\n");
 237                 return ret;
 238         }
 239
 240         ret = devfreq_suspend_device(dmcfreq->devfreq);
 241         if (ret < 0) {
 242                 dev_err(dev, "failed to suspend the devfreq devices\n");
 243                 return ret;
 244         }
 245
 246         return 0;
 247 }
 248
 249 static __maybe_unused int rockchip_dmcfreq_resume(struct device *dev)
 250 {
 251         struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 252         int ret = 0;
 253
 254         ret = devfreq_event_enable_edev(dmcfreq->edev);
 255         if (ret < 0) {
 256                 dev_err(dev, "failed to enable the devfreq-event devices\n");
 257                 return ret;
 258         }
 259
 260         ret = devfreq_resume_device(dmcfreq->devfreq);
 261         if (ret < 0) {
 262                 dev_err(dev, "failed to resume the devfreq devices\n");
 263                 return ret;
 264         }
 265         return ret;
 266 }
 267
 268 static SIMPLE_DEV_PM_OPS(rockchip_dmcfreq_pm, rockchip_dmcfreq_suspend,
 269                          rockchip_dmcfreq_resume);
 270
 271 static int rockchip_dmcfreq_init_freq_table(struct device *dev,
 272                                             struct devfreq_dev_profile *devp)
 273 {
 274         int count;
 275         int i = 0;
 276         unsigned long freq = 0;
 277         struct dev_pm_opp *opp;
 278
 279         rcu_read_lock();
 280         count = dev_pm_opp_get_opp_count(dev);
 281         if (count < 0) {
 282                 rcu_read_unlock();
 283                 return count;
 284         }
 285         rcu_read_unlock();
 286
 287         devp->freq_table = kmalloc_array(count, sizeof(devp->freq_table[0]),
 288                                 GFP_KERNEL);
 289         if (!devp->freq_table)
 290                 return -ENOMEM;
 291
 292         rcu_read_lock();
 293         for (i = 0; i < count; i++, freq++) {
 294                 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
 295                 if (IS_ERR(opp))
 296                         break;
 297
 298                 devp->freq_table[i] = freq;
 299         }
 300         rcu_read_unlock();
 301
 302         if (count != i)
 303                 dev_warn(dev, "Unable to enumerate all OPPs (%d!=%d)\n",
 304                          count, i);
 305
 306         devp->max_state = i;
 307         return 0;
 308 }
 309
 310 static struct rk3368_dram_timing *of_get_rk3368_timings(struct device *dev,
 311                                                         struct device_node *np)
 312 {
 313         struct rk3368_dram_timing *timing = NULL;
 314         struct device_node *np_tim;
 315         int ret;
 316
 317         np_tim = of_parse_phandle(np, "ddr_timing", 0);
 318         if (np_tim) {
 319                 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
 320                 if (!timing)
 321                         goto err;
 322
 323                 ret |= of_property_read_u32(np_tim, "dram_spd_bin",
 324                                             &timing->dram_spd_bin);
 325                 ret |= of_property_read_u32(np_tim, "sr_idle",
 326                                             &timing->sr_idle);
 327                 ret |= of_property_read_u32(np_tim, "pd_idle",
 328                                             &timing->pd_idle);
 329                 ret |= of_property_read_u32(np_tim, "dram_dll_disb_freq",
 330                                             &timing->dram_dll_dis_freq);
 331                 ret |= of_property_read_u32(np_tim, "phy_dll_disb_freq",
 332                                             &timing->phy_dll_dis_freq);
 333                 ret |= of_property_read_u32(np_tim, "dram_odt_disb_freq",
 334                                             &timing->dram_odt_dis_freq);
 335                 ret |= of_property_read_u32(np_tim, "phy_odt_disb_freq",
 336                                             &timing->phy_odt_dis_freq);
 337                 ret |= of_property_read_u32(np_tim, "ddr3_drv",
 338                                             &timing->ddr3_drv);
 339                 ret |= of_property_read_u32(np_tim, "ddr3_odt",
 340                                             &timing->ddr3_odt);
 341                 ret |= of_property_read_u32(np_tim, "lpddr3_drv",
 342                                             &timing->lpddr3_drv);
 343                 ret |= of_property_read_u32(np_tim, "lpddr3_odt",
 344                                             &timing->lpddr3_odt);
 345                 ret |= of_property_read_u32(np_tim, "lpddr2_drv",
 346                                             &timing->lpddr2_drv);
 347                 ret |= of_property_read_u32(np_tim, "phy_clk_drv",
 348                                             &timing->phy_clk_drv);
 349                 ret |= of_property_read_u32(np_tim, "phy_cmd_drv",
 350                                             &timing->phy_cmd_drv);
 351                 ret |= of_property_read_u32(np_tim, "phy_dqs_drv",
 352                                             &timing->phy_dqs_drv);
 353                 ret |= of_property_read_u32(np_tim, "phy_odt",
 354                                             &timing->phy_odt);
 355                 if (ret) {
 356                         devm_kfree(dev, timing);
 357                         goto err;
 358                 }
 359                 of_node_put(np_tim);
 360                 return timing;
 361         }
 362
 363 err:
 364         if (timing) {
 365                 devm_kfree(dev, timing);
 366                 timing = NULL;
 367         }
 368         of_node_put(np_tim);
 369         return timing;
 370 }
 371
 372 static int rk3368_dmc_init(struct platform_device *pdev)
 373 {
 374         struct device *dev = &pdev->dev;
 375         struct device_node *np = pdev->dev.of_node;
 376         struct arm_smccc_res res;
 377         struct rk3368_dram_timing *dram_timing;
 378         struct clk *pclk_phy, *pclk_upctl;
 379         int ret;
 380         u32 dram_spd_bin;
 381         u32 addr_mcu_el3;
 382         u32 dclk_mode;
 383         u32 lcdc_type;
 384
 385         pclk_phy = devm_clk_get(dev, "pclk_phy");
 386         if (IS_ERR(pclk_phy)) {
 387                 dev_err(dev, "Cannot get the clk pclk_phy\n");
 388                 return PTR_ERR(pclk_phy);
 389         };
 390         ret = clk_prepare_enable(pclk_phy);
 391         if (ret < 0) {
 392                 dev_err(dev, "failed to prepare/enable pclk_phy\n");
 393                 return ret;
 394         }
 395         pclk_upctl = devm_clk_get(dev, "pclk_upctl");
 396         if (IS_ERR(pclk_phy)) {
 397                 dev_err(dev, "Cannot get the clk pclk_upctl\n");
 398                 return PTR_ERR(pclk_upctl);
 399         };
 400         ret = clk_prepare_enable(pclk_upctl);
 401         if (ret < 0) {
 402                 dev_err(dev, "failed to prepare/enable pclk_upctl\n");
 403                 return ret;
 404         }
 405
 406         /*
 407          * Get dram timing and pass it to arm trust firmware,
 408          * the dram drvier in arm trust firmware will get these
 409          * timing and to do dram initial.
 410          */
 411         dram_timing = of_get_rk3368_timings(dev, np);
 412         if (dram_timing) {
 413                 dram_spd_bin = dram_timing->dram_spd_bin;
 414                 if (scpi_ddr_send_timing((u32 *)dram_timing,
 415                                          sizeof(struct rk3368_dram_timing)))
 416                         dev_err(dev, "send ddr timing timeout\n");
 417         } else {
 418                 dev_err(dev, "get ddr timing from dts error\n");
 419                 dram_spd_bin = DDR3_DEFAULT;
 420         }
 421
 422         res = sip_smc_mcu_el3fiq(FIQ_INIT_HANDLER,
 423                                  FIQ_NUM_FOR_DCF,
 424                                  FIQ_CPU_TGT_BOOT);
 425         if ((res.a0) || (res.a1 == 0) || (res.a1 > 0x80000))
 426                 dev_err(dev, "Trust version error, pls check trust version\n");
 427         addr_mcu_el3 = res.a1;
 428
 429         if (of_property_read_u32(np, "vop-dclk-mode", &dclk_mode) == 0)
 430                 scpi_ddr_dclk_mode(dclk_mode);
 431
 432         lcdc_type = 7;
 433
 434         if (scpi_ddr_init(dram_spd_bin, 0, lcdc_type,
 435                           addr_mcu_el3))
 436                 dev_err(dev, "ddr init error\n");
 437         else
 438                 dev_dbg(dev, ("%s out\n"), __func__);
 439
 440         return 0;
 441 }
 442
 443 static struct rk3399_dram_timing *of_get_rk3399_timings(struct device *dev,
 444                                                         struct device_node *np)
 445 {
 446         struct rk3399_dram_timing *timing = NULL;
 447         struct device_node *np_tim;
 448         int ret;
 449
 450         np_tim = of_parse_phandle(np, "ddr_timing", 0);
 451         if (np_tim) {
 452                 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
 453                 if (!timing)
 454                         goto err;
 455
 456                 ret = of_property_read_u32(np_tim, "ddr3_speed_bin",
 457                                            &timing->ddr3_speed_bin);
 458                 ret |= of_property_read_u32(np_tim, "pd_idle",
 459                                             &timing->pd_idle);
 460                 ret |= of_property_read_u32(np_tim, "sr_idle",
 461                                             &timing->sr_idle);
 462                 ret |= of_property_read_u32(np_tim, "sr_mc_gate_idle",
 463                                             &timing->sr_mc_gate_idle);
 464                 ret |= of_property_read_u32(np_tim, "srpd_lite_idle",
 465                                             &timing->srpd_lite_idle);
 466                 ret |= of_property_read_u32(np_tim, "standby_idle",
 467                                             &timing->standby_idle);
 468                 ret |= of_property_read_u32(np_tim, "dram_dll_dis_freq",
 469                                             &timing->dram_dll_dis_freq);
 470                 ret |= of_property_read_u32(np_tim, "phy_dll_dis_freq",
 471                                             &timing->phy_dll_dis_freq);
 472                 ret |= of_property_read_u32(np_tim, "ddr3_odt_dis_freq",
 473                                             &timing->ddr3_odt_dis_freq);
 474                 ret |= of_property_read_u32(np_tim, "ddr3_drv",
 475                                             &timing->ddr3_drv);
 476                 ret |= of_property_read_u32(np_tim, "ddr3_odt",
 477                                             &timing->ddr3_odt);
 478                 ret |= of_property_read_u32(np_tim, "phy_ddr3_ca_drv",
 479                                             &timing->phy_ddr3_ca_drv);
 480                 ret |= of_property_read_u32(np_tim, "phy_ddr3_dq_drv",
 481                                             &timing->phy_ddr3_dq_drv);
 482                 ret |= of_property_read_u32(np_tim, "phy_ddr3_odt",
 483                                             &timing->phy_ddr3_odt);
 484                 ret |= of_property_read_u32(np_tim, "lpddr3_odt_dis_freq",
 485                                             &timing->lpddr3_odt_dis_freq);
 486                 ret |= of_property_read_u32(np_tim, "lpddr3_drv",
 487                                             &timing->lpddr3_drv);
 488                 ret |= of_property_read_u32(np_tim, "lpddr3_odt",
 489                                             &timing->lpddr3_odt);
 490                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_ca_drv",
 491                                             &timing->phy_lpddr3_ca_drv);
 492                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_dq_drv",
 493                                             &timing->phy_lpddr3_dq_drv);
 494                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_odt",
 495                                             &timing->phy_lpddr3_odt);
 496                 ret |= of_property_read_u32(np_tim, "lpddr4_odt_dis_freq",
 497                                             &timing->lpddr4_odt_dis_freq);
 498                 ret |= of_property_read_u32(np_tim, "lpddr4_drv",
 499                                             &timing->lpddr4_drv);
 500                 ret |= of_property_read_u32(np_tim, "lpddr4_dq_odt",
 501                                             &timing->lpddr4_dq_odt);
 502                 ret |= of_property_read_u32(np_tim, "lpddr4_ca_odt",
 503                                             &timing->lpddr4_ca_odt);
 504                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ca_drv",
 505                                             &timing->phy_lpddr4_ca_drv);
 506                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ck_cs_drv",
 507                                             &timing->phy_lpddr4_ck_cs_drv);
 508                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_dq_drv",
 509                                             &timing->phy_lpddr4_dq_drv);
 510                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_odt",
 511                                             &timing->phy_lpddr4_odt);
 512                 if (ret) {
 513                         devm_kfree(dev, timing);
 514                         goto err;
 515                 }
 516                 of_node_put(np_tim);
 517                 return timing;
 518         }
 519
 520 err:
 521         if (timing) {
 522                 devm_kfree(dev, timing);
 523                 timing = NULL;
 524         }
 525         of_node_put(np_tim);
 526         return timing;
 527 }
 528
 529 static int rk3399_dmc_init(struct platform_device *pdev)
 530 {
 531         struct device *dev = &pdev->dev;
 532         struct device_node *np = pdev->dev.of_node;
 533         struct arm_smccc_res res;
 534         struct rk3399_dram_timing *dram_timing;
 535         int index, size;
 536         u32 *timing;
 537
 538         /*
 539          * Get dram timing and pass it to arm trust firmware,
 540          * the dram drvier in arm trust firmware will get these
 541          * timing and to do dram initial.
 542          */
 543         dram_timing = of_get_rk3399_timings(dev, np);
 544         if (dram_timing) {
 545                 timing = (u32 *)dram_timing;
 546                 size = sizeof(struct rk3399_dram_timing) / 4;
 547                 for (index = 0; index < size; index++) {
 548                         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
 549                                       ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
 550                                       0, 0, 0, 0, &res);
 551                         if (res.a0) {
 552                                 dev_err(dev, "Failed to set dram param: %ld\n",
 553                                         res.a0);
 554                                 return -EINVAL;
 555                         }
 556                 }
 557         }
 558
 559         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
 560                       ROCKCHIP_SIP_CONFIG_DRAM_INIT,
 561                       0, 0, 0, 0, &res);
 562
 563         return 0;
 564 }
 565
 566 static const struct of_device_id rockchip_dmcfreq_of_match[] = {
 567         { .compatible = "rockchip,rk3368-dmc", .data = rk3368_dmc_init },
 568         { .compatible = "rockchip,rk3399-dmc", .data = rk3399_dmc_init },
 569         { },
 570 };
 571 MODULE_DEVICE_TABLE(of, rockchip_dmcfreq_of_match);
 572
 573 static int rockchip_dmcfreq_probe(struct platform_device *pdev)
 574 {
 575         struct device *dev = &pdev->dev;
 576         struct device_node *np = pdev->dev.of_node;
 577         struct rockchip_dmcfreq *data;
 578         struct devfreq_dev_profile *devp = &rockchip_devfreq_dmc_profile;
 579         const struct of_device_id *match;
 580         int (*init)(struct platform_device *pdev,
 581                     struct rockchip_dmcfreq *data);
 582         int ret;
 583
 584         data = devm_kzalloc(dev, sizeof(struct rockchip_dmcfreq), GFP_KERNEL);
 585         if (!data)
 586                 return -ENOMEM;
 587
 588         mutex_init(&data->lock);
 589
 590         data->vdd_center = devm_regulator_get(dev, "center");
 591         if (IS_ERR(data->vdd_center)) {
 592                 dev_err(dev, "Cannot get the regulator \"center\"\n");
 593                 return PTR_ERR(data->vdd_center);
 594         }
 595
 596         data->dmc_clk = devm_clk_get(dev, "dmc_clk");
 597         if (IS_ERR(data->dmc_clk)) {
 598                 dev_err(dev, "Cannot get the clk dmc_clk\n");
 599                 return PTR_ERR(data->dmc_clk);
 600         };
 601
 602         data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
 603         if (IS_ERR(data->edev))
 604                 return -EPROBE_DEFER;
 605
 606         ret = devfreq_event_enable_edev(data->edev);
 607         if (ret < 0) {
 608                 dev_err(dev, "failed to enable devfreq-event devices\n");
 609                 return ret;
 610         }
 611
 612         match = of_match_node(rockchip_dmcfreq_of_match, pdev->dev.of_node);
 613         if (match) {
 614                 init = match->data;
 615                 if (init) {
 616                         if (init(pdev, data))
 617                                 return -EINVAL;
 618                 }
 619         }
 620
 621         /*
 622          * We add a devfreq driver to our parent since it has a device tree node
 623          * with operating points.
 624          */
 625         if (dev_pm_opp_of_add_table(dev)) {
 626                 dev_err(dev, "Invalid operating-points in device tree.\n");
 627                 return -EINVAL;
 628         }
 629
 630         if (rockchip_dmcfreq_init_freq_table(dev, devp))
 631                 return -EFAULT;
 632
 633         of_property_read_u32(np, "upthreshold",
 634                              &data->ondemand_data.upthreshold);
 635         of_property_read_u32(np, "downdifferential",
 636                              &data->ondemand_data.downdifferential);
 637
 638         data->rate = clk_get_rate(data->dmc_clk);
 639         data->volt = regulator_get_voltage(data->vdd_center);
 640
 641         devp->initial_freq = data->rate;
 642         data->devfreq = devm_devfreq_add_device(dev, devp,
 643                                            "simple_ondemand",
 644                                            &data->ondemand_data);
 645         if (IS_ERR(data->devfreq))
 646                 return PTR_ERR(data->devfreq);
 647         devm_devfreq_register_opp_notifier(dev, data->devfreq);
 648
 649         data->devfreq->min_freq = devp->freq_table[0];
 650         data->devfreq->max_freq =
 651                 devp->freq_table[devp->max_state ? devp->max_state - 1 : 0];
 652
 653         data->dev = dev;
 654         platform_set_drvdata(pdev, data);
 655
 656         if (vop_register_dmc())
 657                 dev_err(dev, "fail to register notify to vop.\n");
 658
 659         return 0;
 660 }
 661
 662 static struct platform_driver rockchip_dmcfreq_driver = {
 663         .probe  = rockchip_dmcfreq_probe,
 664         .driver = {
 665                 .name   = "rockchip-dmc",
 666                 .pm     = &rockchip_dmcfreq_pm,
 667                 .of_match_table = rockchip_dmcfreq_of_match,
 668         },
 669 };
 670 module_platform_driver(rockchip_dmcfreq_driver);
 671
 672 MODULE_LICENSE("GPL v2");
 673 MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
 674 MODULE_DESCRIPTION("rockchip dmcfreq driver with devfreq framework");