2 # DMA engine configuration
6 bool "DMA Engine support"
9 DMA engines can do asynchronous data transfers without
10 involving the host CPU. Currently, this framework can be
11 used to offload memory copies in the network stack and
12 RAID operations in the MD driver. This menu only presents
13 DMA Device drivers supported by the configured arch, it may
14 be empty in some cases.
16 config DMADEVICES_DEBUG
17 bool "DMA Engine debugging"
18 depends on DMADEVICES != n
20 This is an option for use by developers; most people should
21 say N here. This enables DMA engine core and driver debugging.
23 config DMADEVICES_VDEBUG
24 bool "DMA Engine verbose debugging"
25 depends on DMADEVICES_DEBUG != n
27 This is an option for use by developers; most people should
28 say N here. This enables deeper (more verbose) debugging of
29 the DMA engine core and drivers.
37 tristate "Intel MID DMA support for Peripheral DMA controllers"
42 Enable support for the Intel(R) MID DMA engine present
43 in Intel MID chipsets.
45 Say Y here if you have such a chipset.
49 config ASYNC_TX_ENABLE_CHANNEL_SWITCH
53 bool "ARM PrimeCell PL080 or PL081 support"
56 select DMA_VIRTUAL_CHANNELS
58 Platform has a PL08x DMAC device
59 which can provide DMA engine support
62 tristate "Intel I/OAT DMA support"
67 Enable support for the Intel(R) I/OAT DMA engine present
68 in recent Intel Xeon chipsets.
70 Say Y here if you have such a chipset.
75 tristate "Intel IOP ADMA support"
76 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
78 select ASYNC_TX_ENABLE_CHANNEL_SWITCH
80 Enable support for the Intel(R) IOP Series RAID engines.
83 tristate "Synopsys DesignWare AHB DMA support"
84 depends on GENERIC_HARDIRQS
86 default y if CPU_AT32AP7000
88 Support the Synopsys DesignWare AHB DMA controller. This
89 can be integrated in chips such as the Atmel AT32ap7000.
91 config DW_DMAC_BIG_ENDIAN_IO
92 bool "Use big endian I/O register access"
96 Say yes here to use big endian I/O access when reading and writing
97 to the DMA controller registers. This is needed on some platforms,
98 like the Atmel AVR32 architecture.
100 If unsure, use the default setting.
103 tristate "Atmel AHB DMA support"
107 Support the Atmel AHB DMA controller.
110 tristate "Freescale Elo and Elo Plus DMA support"
113 select ASYNC_TX_ENABLE_CHANNEL_SWITCH
115 Enable support for the Freescale Elo and Elo Plus DMA controllers.
116 The Elo is the DMA controller on some 82xx and 83xx parts, and the
117 Elo Plus is the DMA controller on 85xx and 86xx parts.
120 tristate "Freescale MPC512x built-in DMA engine support"
121 depends on PPC_MPC512x || PPC_MPC831x
124 Enable support for the Freescale MPC512x built-in DMA engine.
126 source "drivers/dma/bestcomm/Kconfig"
129 bool "Marvell XOR engine support"
130 depends on PLAT_ORION
132 select ASYNC_TX_ENABLE_CHANNEL_SWITCH
134 Enable support for the Marvell XOR engine.
137 bool "MX3x Image Processing Unit support"
142 If you plan to use the Image Processing unit in the i.MX3x, say
143 Y here. If unsure, select Y.
146 int "Number of dynamically mapped interrupts for IPU"
151 Out of 137 interrupt sources on i.MX31 IPU only very few are used.
152 To avoid bloating the irq_desc[] array we allocate a sufficient
153 number of IRQ slots and map them dynamically to specific sources.
156 tristate "Toshiba TXx9 SoC DMA support"
157 depends on MACH_TX49XX || MACH_TX39XX
160 Support the TXx9 SoC internal DMA controller. This can be
161 integrated in chips such as the Toshiba TX4927/38/39.
163 config TEGRA20_APB_DMA
164 bool "NVIDIA Tegra20 APB DMA support"
165 depends on ARCH_TEGRA
168 Support for the NVIDIA Tegra20 APB DMA controller driver. The
169 DMA controller is having multiple DMA channel which can be
170 configured for different peripherals like audio, UART, SPI,
171 I2C etc which is in APB bus.
172 This DMA controller transfers data from memory to peripheral fifo
173 or vice versa. It does not support memory to memory data transfer.
175 source "drivers/dma/sh/Kconfig"
178 bool "ST-Ericsson COH901318 DMA support"
182 Enable support for ST-Ericsson COH 901 318 DMA.
185 bool "ST-Ericsson DMA40 support"
186 depends on ARCH_U8500
189 Support for ST-Ericsson DMA40 controller
191 config AMCC_PPC440SPE_ADMA
192 tristate "AMCC PPC440SPe ADMA support"
193 depends on 440SPe || 440SP
195 select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
196 select ASYNC_TX_ENABLE_CHANNEL_SWITCH
198 Enable support for the AMCC PPC440SPe RAID engines.
201 tristate "Timberdale FPGA DMA support"
202 depends on MFD_TIMBERDALE || HAS_IOMEM
205 Enable support for the Timberdale FPGA DMA engine.
208 tristate "CSR SiRFprimaII/SiRFmarco DMA support"
212 Enable support for the CSR SiRFprimaII DMA engine.
215 tristate "TI EDMA support"
216 depends on ARCH_DAVINCI
218 select DMA_VIRTUAL_CHANNELS
221 Enable support for the TI EDMA controller. This DMA
222 engine is found on TI DaVinci and AM33xx parts.
224 config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
228 tristate "DMA API Driver for PL330"
232 Select if your platform has one or more PL330 DMACs.
233 You need to provide platform specific settings via
234 platform_data for a dma-pl330 device.
237 tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA"
238 depends on PCI && X86
241 Enable support for Intel EG20T PCH DMA engine.
243 This driver also can be used for LAPIS Semiconductor IOH(Input/
244 Output Hub), ML7213, ML7223 and ML7831.
245 ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is
246 for MP(Media Phone) use and ML7831 IOH is for general purpose use.
247 ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
248 ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
251 tristate "i.MX SDMA support"
255 Support the i.MX SDMA engine. This engine is integrated into
256 Freescale i.MX25/31/35/51/53 chips.
259 tristate "i.MX DMA support"
263 Support the i.MX DMA engine. This engine is integrated into
264 Freescale i.MX1/21/27 chips.
267 bool "MXS DMA support"
268 depends on SOC_IMX23 || SOC_IMX28 || SOC_IMX6Q
272 Support the MXS DMA engine. This engine including APBH-DMA
273 and APBX-DMA is integrated into Freescale i.MX23/28 chips.
276 bool "Cirrus Logic EP93xx DMA support"
277 depends on ARCH_EP93XX
280 Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller.
283 tristate "SA-11x0 DMA support"
284 depends on ARCH_SA1100
286 select DMA_VIRTUAL_CHANNELS
288 Support the DMA engine found on Intel StrongARM SA-1100 and
289 SA-1110 SoCs. This DMA engine can only be used with on-chip
293 bool "MMP Two-Channel DMA support"
297 Support the MMP Two-Channel DMA engine.
298 This engine used for MMP Audio DMA and pxa910 SQU.
300 Say Y here if you enabled MMP ADMA, otherwise say N.
303 tristate "OMAP DMA support"
306 select DMA_VIRTUAL_CHANNELS
309 bool "MMP PDMA support"
310 depends on (ARCH_MMP || ARCH_PXA)
313 Support the MMP PDMA engine for PXA and MMP platfrom.
318 config DMA_VIRTUAL_CHANNELS
329 comment "DMA Clients"
330 depends on DMA_ENGINE
333 bool "Network: TCP receive copy offload"
334 depends on DMA_ENGINE && NET
335 default (INTEL_IOATDMA || FSL_DMA)
337 This enables the use of DMA engines in the network stack to
338 offload receive copy-to-user operations, freeing CPU cycles.
340 Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
344 bool "Async_tx: Offload support for the async_tx api"
345 depends on DMA_ENGINE
347 This allows the async_tx api to take advantage of offload engines for
348 memcpy, memset, xor, and raid6 p+q operations. If your platform has
349 a dma engine that can perform raid operations and you have enabled
355 tristate "DMA Test client"
356 depends on DMA_ENGINE
358 Simple DMA test client. Say N unless you're debugging a