2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the file
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
69 * Only the former works sanely with scatter lists, so we only implement
70 * the DMAC flow control method. However, peripherals which use the LBREQ
71 * and LSREQ signals (eg, MMCI) are unable to use this mode, which through
72 * these hardware restrictions prevents them from using scatter DMA.
75 * - Break out common code from arch/arm/mach-s3c64xx and share
77 #include <linux/amba/bus.h>
78 #include <linux/amba/pl08x.h>
79 #include <linux/debugfs.h>
80 #include <linux/delay.h>
81 #include <linux/device.h>
82 #include <linux/dmaengine.h>
83 #include <linux/dmapool.h>
84 #include <linux/init.h>
85 #include <linux/interrupt.h>
86 #include <linux/module.h>
87 #include <linux/seq_file.h>
88 #include <linux/slab.h>
89 #include <asm/hardware/pl080.h>
91 #define DRIVER_NAME "pl08xdmac"
94 * struct vendor_data - vendor-specific config parameters for PL08x derivatives
95 * @channels: the number of channels available in this variant
96 * @dualmaster: whether this version supports dual AHB masters or not.
104 * PL08X private data structures
105 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
106 * start & end do not - their bus bit info is in cctl. Also note that these
107 * are fixed 32-bit quantities.
117 * struct pl08x_driver_data - the local state holder for the PL08x
118 * @slave: slave engine for this instance
119 * @memcpy: memcpy engine for this instance
120 * @base: virtual memory base (remapped) for the PL08x
121 * @adev: the corresponding AMBA (PrimeCell) bus entry
122 * @vd: vendor data for this PL08x variant
123 * @pd: platform data passed in from the platform/machine
124 * @phy_chans: array of data for the physical channels
125 * @pool: a pool for the LLI descriptors
126 * @pool_ctr: counter of LLIs in the pool
127 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
129 * @mem_buses: set to indicate memory transfers on AHB2.
130 * @lock: a spinlock for this struct
132 struct pl08x_driver_data {
133 struct dma_device slave;
134 struct dma_device memcpy;
136 struct amba_device *adev;
137 const struct vendor_data *vd;
138 struct pl08x_platform_data *pd;
139 struct pl08x_phy_chan *phy_chans;
140 struct dma_pool *pool;
148 * PL08X specific defines
152 * Memory boundaries: the manual for PL08x says that the controller
153 * cannot read past a 1KiB boundary, so these defines are used to
154 * create transfer LLIs that do not cross such boundaries.
156 #define PL08X_BOUNDARY_SHIFT (10) /* 1KB 0x400 */
157 #define PL08X_BOUNDARY_SIZE (1 << PL08X_BOUNDARY_SHIFT)
159 /* Size (bytes) of each LLI buffer allocated for one transfer */
160 # define PL08X_LLI_TSFR_SIZE 0x2000
162 /* Maximum times we call dma_pool_alloc on this pool without freeing */
163 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
164 #define PL08X_ALIGN 8
166 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
168 return container_of(chan, struct pl08x_dma_chan, chan);
171 static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx)
173 return container_of(tx, struct pl08x_txd, tx);
177 * Physical channel handling
180 /* Whether a certain channel is busy or not */
181 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
185 val = readl(ch->base + PL080_CH_CONFIG);
186 return val & PL080_CONFIG_ACTIVE;
190 * Set the initial DMA register values i.e. those for the first LLI
191 * The next LLI pointer and the configuration interrupt bit have
192 * been set when the LLIs were constructed. Poke them into the hardware
193 * and start the transfer.
195 static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
196 struct pl08x_txd *txd)
198 struct pl08x_driver_data *pl08x = plchan->host;
199 struct pl08x_phy_chan *phychan = plchan->phychan;
200 struct pl08x_lli *lli = &txd->llis_va[0];
205 /* Wait for channel inactive */
206 while (pl08x_phy_channel_busy(phychan))
209 dev_vdbg(&pl08x->adev->dev,
210 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
211 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
212 phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
215 writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
216 writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
217 writel(lli->lli, phychan->base + PL080_CH_LLI);
218 writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
219 writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
221 /* Enable the DMA channel */
222 /* Do not access config register until channel shows as disabled */
223 while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
226 /* Do not access config register until channel shows as inactive */
227 val = readl(phychan->base + PL080_CH_CONFIG);
228 while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
229 val = readl(phychan->base + PL080_CH_CONFIG);
231 writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
235 * Pause the channel by setting the HALT bit.
237 * For M->P transfers, pause the DMAC first and then stop the peripheral -
238 * the FIFO can only drain if the peripheral is still requesting data.
239 * (note: this can still timeout if the DMAC FIFO never drains of data.)
241 * For P->M transfers, disable the peripheral first to stop it filling
242 * the DMAC FIFO, and then pause the DMAC.
244 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
249 /* Set the HALT bit and wait for the FIFO to drain */
250 val = readl(ch->base + PL080_CH_CONFIG);
251 val |= PL080_CONFIG_HALT;
252 writel(val, ch->base + PL080_CH_CONFIG);
254 /* Wait for channel inactive */
255 for (timeout = 1000; timeout; timeout--) {
256 if (!pl08x_phy_channel_busy(ch))
260 if (pl08x_phy_channel_busy(ch))
261 pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id);
264 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
268 /* Clear the HALT bit */
269 val = readl(ch->base + PL080_CH_CONFIG);
270 val &= ~PL080_CONFIG_HALT;
271 writel(val, ch->base + PL080_CH_CONFIG);
275 * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
276 * clears any pending interrupt status. This should not be used for
277 * an on-going transfer, but as a method of shutting down a channel
278 * (eg, when it's no longer used) or terminating a transfer.
280 static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
281 struct pl08x_phy_chan *ch)
283 u32 val = readl(ch->base + PL080_CH_CONFIG);
285 val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |
286 PL080_CONFIG_TC_IRQ_MASK);
288 writel(val, ch->base + PL080_CH_CONFIG);
290 writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR);
291 writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR);
294 static inline u32 get_bytes_in_cctl(u32 cctl)
296 /* The source width defines the number of bytes */
297 u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
299 switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
300 case PL080_WIDTH_8BIT:
302 case PL080_WIDTH_16BIT:
305 case PL080_WIDTH_32BIT:
312 /* The channel should be paused when calling this */
313 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
315 struct pl08x_phy_chan *ch;
316 struct pl08x_txd *txd;
320 spin_lock_irqsave(&plchan->lock, flags);
321 ch = plchan->phychan;
325 * Follow the LLIs to get the number of remaining
326 * bytes in the currently active transaction.
329 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
331 /* First get the remaining bytes in the active transfer */
332 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
335 struct pl08x_lli *llis_va = txd->llis_va;
336 dma_addr_t llis_bus = txd->llis_bus;
339 BUG_ON(clli < llis_bus || clli >= llis_bus +
340 sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
343 * Locate the next LLI - as this is an array,
344 * it's simple maths to find.
346 index = (clli - llis_bus) / sizeof(struct pl08x_lli);
348 for (; index < MAX_NUM_TSFR_LLIS; index++) {
349 bytes += get_bytes_in_cctl(llis_va[index].cctl);
352 * A LLI pointer of 0 terminates the LLI list
354 if (!llis_va[index].lli)
360 /* Sum up all queued transactions */
361 if (!list_empty(&plchan->pend_list)) {
362 struct pl08x_txd *txdi;
363 list_for_each_entry(txdi, &plchan->pend_list, node) {
368 spin_unlock_irqrestore(&plchan->lock, flags);
374 * Allocate a physical channel for a virtual channel
376 * Try to locate a physical channel to be used for this transfer. If all
377 * are taken return NULL and the requester will have to cope by using
378 * some fallback PIO mode or retrying later.
380 static struct pl08x_phy_chan *
381 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
382 struct pl08x_dma_chan *virt_chan)
384 struct pl08x_phy_chan *ch = NULL;
388 for (i = 0; i < pl08x->vd->channels; i++) {
389 ch = &pl08x->phy_chans[i];
391 spin_lock_irqsave(&ch->lock, flags);
394 ch->serving = virt_chan;
396 spin_unlock_irqrestore(&ch->lock, flags);
400 spin_unlock_irqrestore(&ch->lock, flags);
403 if (i == pl08x->vd->channels) {
404 /* No physical channel available, cope with it */
411 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
412 struct pl08x_phy_chan *ch)
416 spin_lock_irqsave(&ch->lock, flags);
418 /* Stop the channel and clear its interrupts */
419 pl08x_terminate_phy_chan(pl08x, ch);
421 /* Mark it as free */
423 spin_unlock_irqrestore(&ch->lock, flags);
430 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
433 case PL080_WIDTH_8BIT:
435 case PL080_WIDTH_16BIT:
437 case PL080_WIDTH_32BIT:
446 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
451 /* Remove all src, dst and transfer size bits */
452 retbits &= ~PL080_CONTROL_DWIDTH_MASK;
453 retbits &= ~PL080_CONTROL_SWIDTH_MASK;
454 retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
456 /* Then set the bits according to the parameters */
459 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
462 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
465 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
474 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
477 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
480 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
487 retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
491 struct pl08x_lli_build_data {
492 struct pl08x_txd *txd;
493 struct pl08x_bus_data srcbus;
494 struct pl08x_bus_data dstbus;
500 * Autoselect a master bus to use for the transfer this prefers the
501 * destination bus if both available if fixed address on one bus the
502 * other will be chosen
504 static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd,
505 struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl)
507 if (!(cctl & PL080_CONTROL_DST_INCR)) {
510 } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
514 if (bd->dstbus.buswidth == 4) {
517 } else if (bd->srcbus.buswidth == 4) {
520 } else if (bd->dstbus.buswidth == 2) {
523 } else if (bd->srcbus.buswidth == 2) {
527 /* bd->srcbus.buswidth == 1 */
535 * Fills in one LLI for a certain transfer descriptor and advance the counter
537 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
538 int num_llis, int len, u32 cctl)
540 struct pl08x_lli *llis_va = bd->txd->llis_va;
541 dma_addr_t llis_bus = bd->txd->llis_bus;
543 BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
545 llis_va[num_llis].cctl = cctl;
546 llis_va[num_llis].src = bd->srcbus.addr;
547 llis_va[num_llis].dst = bd->dstbus.addr;
548 llis_va[num_llis].lli = llis_bus + (num_llis + 1) *
549 sizeof(struct pl08x_lli);
550 llis_va[num_llis].lli |= bd->lli_bus;
552 if (cctl & PL080_CONTROL_SRC_INCR)
553 bd->srcbus.addr += len;
554 if (cctl & PL080_CONTROL_DST_INCR)
555 bd->dstbus.addr += len;
557 BUG_ON(bd->remainder < len);
559 bd->remainder -= len;
563 * Return number of bytes to fill to boundary, or len.
564 * This calculation works for any value of addr.
566 static inline size_t pl08x_pre_boundary(u32 addr, size_t len)
568 size_t boundary_len = PL08X_BOUNDARY_SIZE -
569 (addr & (PL08X_BOUNDARY_SIZE - 1));
571 return min(boundary_len, len);
575 * This fills in the table of LLIs for the transfer descriptor
576 * Note that we assume we never have to change the burst sizes
579 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
580 struct pl08x_txd *txd)
582 struct pl08x_bus_data *mbus, *sbus;
583 struct pl08x_lli_build_data bd;
586 size_t max_bytes_per_lli, total_bytes = 0;
587 struct pl08x_lli *llis_va;
589 txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus);
591 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
597 /* Get the default CCTL */
601 bd.srcbus.addr = txd->src_addr;
602 bd.dstbus.addr = txd->dst_addr;
603 bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0;
605 /* Find maximum width of the source bus */
607 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
608 PL080_CONTROL_SWIDTH_SHIFT);
610 /* Find maximum width of the destination bus */
612 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
613 PL080_CONTROL_DWIDTH_SHIFT);
615 /* Set up the bus widths to the maximum */
616 bd.srcbus.buswidth = bd.srcbus.maxwidth;
617 bd.dstbus.buswidth = bd.dstbus.maxwidth;
620 * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
622 max_bytes_per_lli = min(bd.srcbus.buswidth, bd.dstbus.buswidth) *
623 PL080_CONTROL_TRANSFER_SIZE_MASK;
625 /* We need to count this down to zero */
626 bd.remainder = txd->len;
629 * Choose bus to align to
630 * - prefers destination bus if both available
631 * - if fixed address on one bus chooses other
633 pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl);
635 dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu llimax=%zu\n",
636 bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "",
638 bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "",
640 bd.remainder, max_bytes_per_lli);
641 dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n",
642 mbus == &bd.srcbus ? "src" : "dst",
643 sbus == &bd.srcbus ? "src" : "dst");
645 if (txd->len < mbus->buswidth) {
646 /* Less than a bus width available - send as single bytes */
647 while (bd.remainder) {
648 dev_vdbg(&pl08x->adev->dev,
649 "%s single byte LLIs for a transfer of "
650 "less than a bus width (remain 0x%08x)\n",
651 __func__, bd.remainder);
652 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
653 pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
657 /* Make one byte LLIs until master bus is aligned */
658 while ((mbus->addr) % (mbus->buswidth)) {
659 dev_vdbg(&pl08x->adev->dev,
660 "%s adjustment lli for less than bus width "
662 __func__, bd.remainder);
663 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
664 pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
670 * - if slave is not then we must set its width down
672 if (sbus->addr % sbus->buswidth) {
673 dev_dbg(&pl08x->adev->dev,
674 "%s set down bus width to one byte\n",
681 * Make largest possible LLIs until less than one bus
684 while (bd.remainder > (mbus->buswidth - 1)) {
685 size_t lli_len, target_len, tsize, odd_bytes;
688 * If enough left try to send max possible,
689 * otherwise try to send the remainder
691 target_len = min(bd.remainder, max_bytes_per_lli);
694 * Set bus lengths for incrementing buses to the
695 * number of bytes which fill to next memory boundary,
696 * limiting on the target length calculated above.
698 if (cctl & PL080_CONTROL_SRC_INCR)
699 bd.srcbus.fill_bytes =
700 pl08x_pre_boundary(bd.srcbus.addr,
703 bd.srcbus.fill_bytes = target_len;
705 if (cctl & PL080_CONTROL_DST_INCR)
706 bd.dstbus.fill_bytes =
707 pl08x_pre_boundary(bd.dstbus.addr,
710 bd.dstbus.fill_bytes = target_len;
712 /* Find the nearest */
713 lli_len = min(bd.srcbus.fill_bytes,
714 bd.dstbus.fill_bytes);
716 BUG_ON(lli_len > bd.remainder);
719 dev_err(&pl08x->adev->dev,
720 "%s lli_len is %zu, <= 0\n",
725 if (lli_len == target_len) {
727 * Can send what we wanted.
730 lli_len = (lli_len/mbus->buswidth) *
735 * So now we know how many bytes to transfer
736 * to get to the nearest boundary. The next
737 * LLI will past the boundary. However, we
738 * may be working to a boundary on the slave
739 * bus. We need to ensure the master stays
740 * aligned, and that we are working in
741 * multiples of the bus widths.
743 odd_bytes = lli_len % mbus->buswidth;
744 lli_len -= odd_bytes;
750 * Check against minimum bus alignment:
751 * Calculate actual transfer size in relation
752 * to bus width an get a maximum remainder of
753 * the smallest bus width - 1
755 /* FIXME: use round_down()? */
756 tsize = lli_len / min(mbus->buswidth,
758 lli_len = tsize * min(mbus->buswidth,
761 if (target_len != lli_len) {
762 dev_vdbg(&pl08x->adev->dev,
763 "%s can't send what we want. Desired 0x%08zx, lli of 0x%08zx bytes in txd of 0x%08zx\n",
764 __func__, target_len, lli_len, txd->len);
767 cctl = pl08x_cctl_bits(cctl,
772 dev_vdbg(&pl08x->adev->dev,
773 "%s fill lli with single lli chunk of size 0x%08zx (remainder 0x%08zx)\n",
774 __func__, lli_len, bd.remainder);
775 pl08x_fill_lli_for_desc(&bd, num_llis++,
777 total_bytes += lli_len;
782 * Creep past the boundary, maintaining
786 for (j = 0; (j < mbus->buswidth)
787 && (bd.remainder); j++) {
788 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
789 dev_vdbg(&pl08x->adev->dev,
790 "%s align with boundary, single byte (remain 0x%08zx)\n",
791 __func__, bd.remainder);
792 pl08x_fill_lli_for_desc(&bd,
793 num_llis++, 1, cctl);
802 while (bd.remainder) {
803 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
804 dev_vdbg(&pl08x->adev->dev,
805 "%s align with boundary, single odd byte (remain %zu)\n",
806 __func__, bd.remainder);
807 pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
811 if (total_bytes != txd->len) {
812 dev_err(&pl08x->adev->dev,
813 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
814 __func__, total_bytes, txd->len);
818 if (num_llis >= MAX_NUM_TSFR_LLIS) {
819 dev_err(&pl08x->adev->dev,
820 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
821 __func__, (u32) MAX_NUM_TSFR_LLIS);
825 llis_va = txd->llis_va;
826 /* The final LLI terminates the LLI. */
827 llis_va[num_llis - 1].lli = 0;
828 /* The final LLI element shall also fire an interrupt. */
829 llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
835 dev_vdbg(&pl08x->adev->dev,
836 "%-3s %-9s %-10s %-10s %-10s %s\n",
837 "lli", "", "csrc", "cdst", "clli", "cctl");
838 for (i = 0; i < num_llis; i++) {
839 dev_vdbg(&pl08x->adev->dev,
840 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",
841 i, &llis_va[i], llis_va[i].src,
842 llis_va[i].dst, llis_va[i].lli, llis_va[i].cctl
851 /* You should call this with the struct pl08x lock held */
852 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
853 struct pl08x_txd *txd)
856 dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
863 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
864 struct pl08x_dma_chan *plchan)
866 struct pl08x_txd *txdi = NULL;
867 struct pl08x_txd *next;
869 if (!list_empty(&plchan->pend_list)) {
870 list_for_each_entry_safe(txdi,
871 next, &plchan->pend_list, node) {
872 list_del(&txdi->node);
873 pl08x_free_txd(pl08x, txdi);
881 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
886 static void pl08x_free_chan_resources(struct dma_chan *chan)
891 * This should be called with the channel plchan->lock held
893 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
894 struct pl08x_txd *txd)
896 struct pl08x_driver_data *pl08x = plchan->host;
897 struct pl08x_phy_chan *ch;
900 /* Check if we already have a channel */
904 ch = pl08x_get_phy_channel(pl08x, plchan);
906 /* No physical channel available, cope with it */
907 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
912 * OK we have a physical channel: for memcpy() this is all we
913 * need, but for slaves the physical signals may be muxed!
914 * Can the platform allow us to use this channel?
916 if (plchan->slave && ch->signal < 0 && pl08x->pd->get_signal) {
917 ret = pl08x->pd->get_signal(plchan);
919 dev_dbg(&pl08x->adev->dev,
920 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
921 ch->id, plchan->name);
922 /* Release physical channel & return */
923 pl08x_put_phy_channel(pl08x, ch);
928 /* Assign the flow control signal to this channel */
929 if (txd->direction == DMA_TO_DEVICE)
930 txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT;
931 else if (txd->direction == DMA_FROM_DEVICE)
932 txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT;
935 dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
940 plchan->phychan_hold++;
941 plchan->phychan = ch;
946 static void release_phy_channel(struct pl08x_dma_chan *plchan)
948 struct pl08x_driver_data *pl08x = plchan->host;
950 if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
951 pl08x->pd->put_signal(plchan);
952 plchan->phychan->signal = -1;
954 pl08x_put_phy_channel(pl08x, plchan->phychan);
955 plchan->phychan = NULL;
958 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
960 struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
961 struct pl08x_txd *txd = to_pl08x_txd(tx);
964 spin_lock_irqsave(&plchan->lock, flags);
966 plchan->chan.cookie += 1;
967 if (plchan->chan.cookie < 0)
968 plchan->chan.cookie = 1;
969 tx->cookie = plchan->chan.cookie;
971 /* Put this onto the pending list */
972 list_add_tail(&txd->node, &plchan->pend_list);
975 * If there was no physical channel available for this memcpy,
976 * stack the request up and indicate that the channel is waiting
977 * for a free physical channel.
979 if (!plchan->slave && !plchan->phychan) {
980 /* Do this memcpy whenever there is a channel ready */
981 plchan->state = PL08X_CHAN_WAITING;
982 plchan->waiting = txd;
984 plchan->phychan_hold--;
987 spin_unlock_irqrestore(&plchan->lock, flags);
992 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
993 struct dma_chan *chan, unsigned long flags)
995 struct dma_async_tx_descriptor *retval = NULL;
1001 * Code accessing dma_async_is_complete() in a tight loop may give problems.
1002 * If slaves are relying on interrupts to signal completion this function
1003 * must not be called with interrupts disabled.
1005 static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan,
1006 dma_cookie_t cookie, struct dma_tx_state *txstate)
1008 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1009 dma_cookie_t last_used;
1010 dma_cookie_t last_complete;
1011 enum dma_status ret;
1014 last_used = plchan->chan.cookie;
1015 last_complete = plchan->lc;
1017 ret = dma_async_is_complete(cookie, last_complete, last_used);
1018 if (ret == DMA_SUCCESS) {
1019 dma_set_tx_state(txstate, last_complete, last_used, 0);
1024 * This cookie not complete yet
1026 last_used = plchan->chan.cookie;
1027 last_complete = plchan->lc;
1029 /* Get number of bytes left in the active transactions and queue */
1030 bytesleft = pl08x_getbytes_chan(plchan);
1032 dma_set_tx_state(txstate, last_complete, last_used,
1035 if (plchan->state == PL08X_CHAN_PAUSED)
1038 /* Whether waiting or running, we're in progress */
1039 return DMA_IN_PROGRESS;
1042 /* PrimeCell DMA extension */
1043 struct burst_table {
1048 static const struct burst_table burst_sizes[] = {
1051 .reg = PL080_BSIZE_256,
1055 .reg = PL080_BSIZE_128,
1059 .reg = PL080_BSIZE_64,
1063 .reg = PL080_BSIZE_32,
1067 .reg = PL080_BSIZE_16,
1071 .reg = PL080_BSIZE_8,
1075 .reg = PL080_BSIZE_4,
1079 .reg = PL080_BSIZE_1,
1084 * Given the source and destination available bus masks, select which
1085 * will be routed to each port. We try to have source and destination
1086 * on separate ports, but always respect the allowable settings.
1088 static u32 pl08x_select_bus(u8 src, u8 dst)
1092 if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1)))
1093 cctl |= PL080_CONTROL_DST_AHB2;
1094 if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2)))
1095 cctl |= PL080_CONTROL_SRC_AHB2;
1100 static u32 pl08x_cctl(u32 cctl)
1102 cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
1103 PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
1104 PL080_CONTROL_PROT_MASK);
1106 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1107 return cctl | PL080_CONTROL_PROT_SYS;
1110 static u32 pl08x_width(enum dma_slave_buswidth width)
1113 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1114 return PL080_WIDTH_8BIT;
1115 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1116 return PL080_WIDTH_16BIT;
1117 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1118 return PL080_WIDTH_32BIT;
1124 static u32 pl08x_burst(u32 maxburst)
1128 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1129 if (burst_sizes[i].burstwords <= maxburst)
1132 return burst_sizes[i].reg;
1135 static int dma_set_runtime_config(struct dma_chan *chan,
1136 struct dma_slave_config *config)
1138 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1139 struct pl08x_driver_data *pl08x = plchan->host;
1140 enum dma_slave_buswidth addr_width;
1141 u32 width, burst, maxburst;
1147 /* Transfer direction */
1148 plchan->runtime_direction = config->direction;
1149 if (config->direction == DMA_TO_DEVICE) {
1150 addr_width = config->dst_addr_width;
1151 maxburst = config->dst_maxburst;
1152 } else if (config->direction == DMA_FROM_DEVICE) {
1153 addr_width = config->src_addr_width;
1154 maxburst = config->src_maxburst;
1156 dev_err(&pl08x->adev->dev,
1157 "bad runtime_config: alien transfer direction\n");
1161 width = pl08x_width(addr_width);
1163 dev_err(&pl08x->adev->dev,
1164 "bad runtime_config: alien address width\n");
1168 cctl |= width << PL080_CONTROL_SWIDTH_SHIFT;
1169 cctl |= width << PL080_CONTROL_DWIDTH_SHIFT;
1172 * If this channel will only request single transfers, set this
1173 * down to ONE element. Also select one element if no maxburst
1176 if (plchan->cd->single)
1179 burst = pl08x_burst(maxburst);
1180 cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
1181 cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
1183 if (plchan->runtime_direction == DMA_FROM_DEVICE) {
1184 plchan->src_addr = config->src_addr;
1185 plchan->src_cctl = pl08x_cctl(cctl) | PL080_CONTROL_DST_INCR |
1186 pl08x_select_bus(plchan->cd->periph_buses,
1189 plchan->dst_addr = config->dst_addr;
1190 plchan->dst_cctl = pl08x_cctl(cctl) | PL080_CONTROL_SRC_INCR |
1191 pl08x_select_bus(pl08x->mem_buses,
1192 plchan->cd->periph_buses);
1195 dev_dbg(&pl08x->adev->dev,
1196 "configured channel %s (%s) for %s, data width %d, "
1197 "maxburst %d words, LE, CCTL=0x%08x\n",
1198 dma_chan_name(chan), plchan->name,
1199 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1208 * Slave transactions callback to the slave device to allow
1209 * synchronization of slave DMA signals with the DMAC enable
1211 static void pl08x_issue_pending(struct dma_chan *chan)
1213 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1214 unsigned long flags;
1216 spin_lock_irqsave(&plchan->lock, flags);
1217 /* Something is already active, or we're waiting for a channel... */
1218 if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1219 spin_unlock_irqrestore(&plchan->lock, flags);
1223 /* Take the first element in the queue and execute it */
1224 if (!list_empty(&plchan->pend_list)) {
1225 struct pl08x_txd *next;
1227 next = list_first_entry(&plchan->pend_list,
1230 list_del(&next->node);
1231 plchan->state = PL08X_CHAN_RUNNING;
1233 pl08x_start_txd(plchan, next);
1236 spin_unlock_irqrestore(&plchan->lock, flags);
1239 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1240 struct pl08x_txd *txd)
1242 struct pl08x_driver_data *pl08x = plchan->host;
1243 unsigned long flags;
1246 num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1252 spin_lock_irqsave(&plchan->lock, flags);
1255 * See if we already have a physical channel allocated,
1256 * else this is the time to try to get one.
1258 ret = prep_phy_channel(plchan, txd);
1261 * No physical channel was available.
1263 * memcpy transfers can be sorted out at submission time.
1265 * Slave transfers may have been denied due to platform
1266 * channel muxing restrictions. Since there is no guarantee
1267 * that this will ever be resolved, and the signal must be
1268 * acquired AFTER acquiring the physical channel, we will let
1269 * them be NACK:ed with -EBUSY here. The drivers can retry
1270 * the prep() call if they are eager on doing this using DMA.
1272 if (plchan->slave) {
1273 pl08x_free_txd_list(pl08x, plchan);
1274 pl08x_free_txd(pl08x, txd);
1275 spin_unlock_irqrestore(&plchan->lock, flags);
1280 * Else we're all set, paused and ready to roll, status
1281 * will switch to PL08X_CHAN_RUNNING when we call
1282 * issue_pending(). If there is something running on the
1283 * channel already we don't change its state.
1285 if (plchan->state == PL08X_CHAN_IDLE)
1286 plchan->state = PL08X_CHAN_PAUSED;
1288 spin_unlock_irqrestore(&plchan->lock, flags);
1293 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan,
1294 unsigned long flags)
1296 struct pl08x_txd *txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1299 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
1300 txd->tx.flags = flags;
1301 txd->tx.tx_submit = pl08x_tx_submit;
1302 INIT_LIST_HEAD(&txd->node);
1304 /* Always enable error and terminal interrupts */
1305 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
1306 PL080_CONFIG_TC_IRQ_MASK;
1312 * Initialize a descriptor to be used by memcpy submit
1314 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1315 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1316 size_t len, unsigned long flags)
1318 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1319 struct pl08x_driver_data *pl08x = plchan->host;
1320 struct pl08x_txd *txd;
1323 txd = pl08x_get_txd(plchan, flags);
1325 dev_err(&pl08x->adev->dev,
1326 "%s no memory for descriptor\n", __func__);
1330 txd->direction = DMA_NONE;
1331 txd->src_addr = src;
1332 txd->dst_addr = dest;
1335 /* Set platform data for m2m */
1336 txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1337 txd->cctl = pl08x->pd->memcpy_channel.cctl &
1338 ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
1340 /* Both to be incremented or the code will break */
1341 txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1343 if (pl08x->vd->dualmaster)
1344 txd->cctl |= pl08x_select_bus(pl08x->mem_buses,
1347 ret = pl08x_prep_channel_resources(plchan, txd);
1354 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1355 struct dma_chan *chan, struct scatterlist *sgl,
1356 unsigned int sg_len, enum dma_data_direction direction,
1357 unsigned long flags)
1359 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1360 struct pl08x_driver_data *pl08x = plchan->host;
1361 struct pl08x_txd *txd;
1365 * Current implementation ASSUMES only one sg
1368 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1373 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1374 __func__, sgl->length, plchan->name);
1376 txd = pl08x_get_txd(plchan, flags);
1378 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1382 if (direction != plchan->runtime_direction)
1383 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1384 "the direction configured for the PrimeCell\n",
1388 * Set up addresses, the PrimeCell configured address
1389 * will take precedence since this may configure the
1390 * channel target address dynamically at runtime.
1392 txd->direction = direction;
1393 txd->len = sgl->length;
1395 if (direction == DMA_TO_DEVICE) {
1396 txd->ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1397 txd->cctl = plchan->dst_cctl;
1398 txd->src_addr = sgl->dma_address;
1399 txd->dst_addr = plchan->dst_addr;
1400 } else if (direction == DMA_FROM_DEVICE) {
1401 txd->ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1402 txd->cctl = plchan->src_cctl;
1403 txd->src_addr = plchan->src_addr;
1404 txd->dst_addr = sgl->dma_address;
1406 dev_err(&pl08x->adev->dev,
1407 "%s direction unsupported\n", __func__);
1411 ret = pl08x_prep_channel_resources(plchan, txd);
1418 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1421 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1422 struct pl08x_driver_data *pl08x = plchan->host;
1423 unsigned long flags;
1426 /* Controls applicable to inactive channels */
1427 if (cmd == DMA_SLAVE_CONFIG) {
1428 return dma_set_runtime_config(chan,
1429 (struct dma_slave_config *)arg);
1433 * Anything succeeds on channels with no physical allocation and
1434 * no queued transfers.
1436 spin_lock_irqsave(&plchan->lock, flags);
1437 if (!plchan->phychan && !plchan->at) {
1438 spin_unlock_irqrestore(&plchan->lock, flags);
1443 case DMA_TERMINATE_ALL:
1444 plchan->state = PL08X_CHAN_IDLE;
1446 if (plchan->phychan) {
1447 pl08x_terminate_phy_chan(pl08x, plchan->phychan);
1450 * Mark physical channel as free and free any slave
1453 release_phy_channel(plchan);
1455 /* Dequeue jobs and free LLIs */
1457 pl08x_free_txd(pl08x, plchan->at);
1460 /* Dequeue jobs not yet fired as well */
1461 pl08x_free_txd_list(pl08x, plchan);
1464 pl08x_pause_phy_chan(plchan->phychan);
1465 plchan->state = PL08X_CHAN_PAUSED;
1468 pl08x_resume_phy_chan(plchan->phychan);
1469 plchan->state = PL08X_CHAN_RUNNING;
1472 /* Unknown command */
1477 spin_unlock_irqrestore(&plchan->lock, flags);
1482 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1484 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1485 char *name = chan_id;
1487 /* Check that the channel is not taken! */
1488 if (!strcmp(plchan->name, name))
1495 * Just check that the device is there and active
1496 * TODO: turn this bit on/off depending on the number of physical channels
1497 * actually used, if it is zero... well shut it off. That will save some
1498 * power. Cut the clock at the same time.
1500 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1504 val = readl(pl08x->base + PL080_CONFIG);
1505 val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
1506 /* We implicitly clear bit 1 and that means little-endian mode */
1507 val |= PL080_CONFIG_ENABLE;
1508 writel(val, pl08x->base + PL080_CONFIG);
1511 static void pl08x_unmap_buffers(struct pl08x_txd *txd)
1513 struct device *dev = txd->tx.chan->device->dev;
1515 if (!(txd->tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
1516 if (txd->tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
1517 dma_unmap_single(dev, txd->src_addr, txd->len,
1520 dma_unmap_page(dev, txd->src_addr, txd->len,
1523 if (!(txd->tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
1524 if (txd->tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
1525 dma_unmap_single(dev, txd->dst_addr, txd->len,
1528 dma_unmap_page(dev, txd->dst_addr, txd->len,
1533 static void pl08x_tasklet(unsigned long data)
1535 struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1536 struct pl08x_driver_data *pl08x = plchan->host;
1537 struct pl08x_txd *txd;
1538 unsigned long flags;
1540 spin_lock_irqsave(&plchan->lock, flags);
1546 /* Update last completed */
1547 plchan->lc = txd->tx.cookie;
1550 /* If a new descriptor is queued, set it up plchan->at is NULL here */
1551 if (!list_empty(&plchan->pend_list)) {
1552 struct pl08x_txd *next;
1554 next = list_first_entry(&plchan->pend_list,
1557 list_del(&next->node);
1559 pl08x_start_txd(plchan, next);
1560 } else if (plchan->phychan_hold) {
1562 * This channel is still in use - we have a new txd being
1563 * prepared and will soon be queued. Don't give up the
1567 struct pl08x_dma_chan *waiting = NULL;
1570 * No more jobs, so free up the physical channel
1571 * Free any allocated signal on slave transfers too
1573 release_phy_channel(plchan);
1574 plchan->state = PL08X_CHAN_IDLE;
1577 * And NOW before anyone else can grab that free:d up
1578 * physical channel, see if there is some memcpy pending
1579 * that seriously needs to start because of being stacked
1580 * up while we were choking the physical channels with data.
1582 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1584 if (waiting->state == PL08X_CHAN_WAITING &&
1585 waiting->waiting != NULL) {
1588 /* This should REALLY not fail now */
1589 ret = prep_phy_channel(waiting,
1592 waiting->phychan_hold--;
1593 waiting->state = PL08X_CHAN_RUNNING;
1594 waiting->waiting = NULL;
1595 pl08x_issue_pending(&waiting->chan);
1601 spin_unlock_irqrestore(&plchan->lock, flags);
1604 dma_async_tx_callback callback = txd->tx.callback;
1605 void *callback_param = txd->tx.callback_param;
1607 /* Don't try to unmap buffers on slave channels */
1609 pl08x_unmap_buffers(txd);
1611 /* Free the descriptor */
1612 spin_lock_irqsave(&plchan->lock, flags);
1613 pl08x_free_txd(pl08x, txd);
1614 spin_unlock_irqrestore(&plchan->lock, flags);
1616 /* Callback to signal completion */
1618 callback(callback_param);
1622 static irqreturn_t pl08x_irq(int irq, void *dev)
1624 struct pl08x_driver_data *pl08x = dev;
1629 val = readl(pl08x->base + PL080_ERR_STATUS);
1631 /* An error interrupt (on one or more channels) */
1632 dev_err(&pl08x->adev->dev,
1633 "%s error interrupt, register value 0x%08x\n",
1636 * Simply clear ALL PL08X error interrupts,
1637 * regardless of channel and cause
1638 * FIXME: should be 0x00000003 on PL081 really.
1640 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1642 val = readl(pl08x->base + PL080_INT_STATUS);
1643 for (i = 0; i < pl08x->vd->channels; i++) {
1644 if ((1 << i) & val) {
1645 /* Locate physical channel */
1646 struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1647 struct pl08x_dma_chan *plchan = phychan->serving;
1649 /* Schedule tasklet on this channel */
1650 tasklet_schedule(&plchan->tasklet);
1655 /* Clear only the terminal interrupts on channels we processed */
1656 writel(mask, pl08x->base + PL080_TC_CLEAR);
1658 return mask ? IRQ_HANDLED : IRQ_NONE;
1661 static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan)
1663 u32 cctl = pl08x_cctl(chan->cd->cctl);
1666 chan->name = chan->cd->bus_id;
1667 chan->src_addr = chan->cd->addr;
1668 chan->dst_addr = chan->cd->addr;
1669 chan->src_cctl = cctl | PL080_CONTROL_DST_INCR |
1670 pl08x_select_bus(chan->cd->periph_buses, chan->host->mem_buses);
1671 chan->dst_cctl = cctl | PL080_CONTROL_SRC_INCR |
1672 pl08x_select_bus(chan->host->mem_buses, chan->cd->periph_buses);
1676 * Initialise the DMAC memcpy/slave channels.
1677 * Make a local wrapper to hold required data
1679 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1680 struct dma_device *dmadev, unsigned int channels, bool slave)
1682 struct pl08x_dma_chan *chan;
1685 INIT_LIST_HEAD(&dmadev->channels);
1688 * Register as many many memcpy as we have physical channels,
1689 * we won't always be able to use all but the code will have
1690 * to cope with that situation.
1692 for (i = 0; i < channels; i++) {
1693 chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
1695 dev_err(&pl08x->adev->dev,
1696 "%s no memory for channel\n", __func__);
1701 chan->state = PL08X_CHAN_IDLE;
1704 chan->cd = &pl08x->pd->slave_channels[i];
1705 pl08x_dma_slave_init(chan);
1707 chan->cd = &pl08x->pd->memcpy_channel;
1708 chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1714 if (chan->cd->circular_buffer) {
1715 dev_err(&pl08x->adev->dev,
1716 "channel %s: circular buffers not supported\n",
1721 dev_info(&pl08x->adev->dev,
1722 "initialize virtual channel \"%s\"\n",
1725 chan->chan.device = dmadev;
1726 chan->chan.cookie = 0;
1729 spin_lock_init(&chan->lock);
1730 INIT_LIST_HEAD(&chan->pend_list);
1731 tasklet_init(&chan->tasklet, pl08x_tasklet,
1732 (unsigned long) chan);
1734 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1736 dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1737 i, slave ? "slave" : "memcpy");
1741 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1743 struct pl08x_dma_chan *chan = NULL;
1744 struct pl08x_dma_chan *next;
1746 list_for_each_entry_safe(chan,
1747 next, &dmadev->channels, chan.device_node) {
1748 list_del(&chan->chan.device_node);
1753 #ifdef CONFIG_DEBUG_FS
1754 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1757 case PL08X_CHAN_IDLE:
1759 case PL08X_CHAN_RUNNING:
1761 case PL08X_CHAN_PAUSED:
1763 case PL08X_CHAN_WAITING:
1768 return "UNKNOWN STATE";
1771 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1773 struct pl08x_driver_data *pl08x = s->private;
1774 struct pl08x_dma_chan *chan;
1775 struct pl08x_phy_chan *ch;
1776 unsigned long flags;
1779 seq_printf(s, "PL08x physical channels:\n");
1780 seq_printf(s, "CHANNEL:\tUSER:\n");
1781 seq_printf(s, "--------\t-----\n");
1782 for (i = 0; i < pl08x->vd->channels; i++) {
1783 struct pl08x_dma_chan *virt_chan;
1785 ch = &pl08x->phy_chans[i];
1787 spin_lock_irqsave(&ch->lock, flags);
1788 virt_chan = ch->serving;
1790 seq_printf(s, "%d\t\t%s\n",
1791 ch->id, virt_chan ? virt_chan->name : "(none)");
1793 spin_unlock_irqrestore(&ch->lock, flags);
1796 seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1797 seq_printf(s, "CHANNEL:\tSTATE:\n");
1798 seq_printf(s, "--------\t------\n");
1799 list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1800 seq_printf(s, "%s\t\t%s\n", chan->name,
1801 pl08x_state_str(chan->state));
1804 seq_printf(s, "\nPL08x virtual slave channels:\n");
1805 seq_printf(s, "CHANNEL:\tSTATE:\n");
1806 seq_printf(s, "--------\t------\n");
1807 list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1808 seq_printf(s, "%s\t\t%s\n", chan->name,
1809 pl08x_state_str(chan->state));
1815 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1817 return single_open(file, pl08x_debugfs_show, inode->i_private);
1820 static const struct file_operations pl08x_debugfs_operations = {
1821 .open = pl08x_debugfs_open,
1823 .llseek = seq_lseek,
1824 .release = single_release,
1827 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1829 /* Expose a simple debugfs interface to view all clocks */
1830 (void) debugfs_create_file(dev_name(&pl08x->adev->dev),
1831 S_IFREG | S_IRUGO, NULL, pl08x,
1832 &pl08x_debugfs_operations);
1836 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1841 static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
1843 struct pl08x_driver_data *pl08x;
1844 const struct vendor_data *vd = id->data;
1848 ret = amba_request_regions(adev, NULL);
1852 /* Create the driver state holder */
1853 pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
1859 /* Initialize memcpy engine */
1860 dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1861 pl08x->memcpy.dev = &adev->dev;
1862 pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1863 pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1864 pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1865 pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1866 pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1867 pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1868 pl08x->memcpy.device_control = pl08x_control;
1870 /* Initialize slave engine */
1871 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1872 pl08x->slave.dev = &adev->dev;
1873 pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1874 pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1875 pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1876 pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1877 pl08x->slave.device_issue_pending = pl08x_issue_pending;
1878 pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1879 pl08x->slave.device_control = pl08x_control;
1881 /* Get the platform data */
1882 pl08x->pd = dev_get_platdata(&adev->dev);
1884 dev_err(&adev->dev, "no platform data supplied\n");
1885 goto out_no_platdata;
1888 /* Assign useful pointers to the driver state */
1892 /* By default, AHB1 only. If dualmaster, from platform */
1893 pl08x->lli_buses = PL08X_AHB1;
1894 pl08x->mem_buses = PL08X_AHB1;
1895 if (pl08x->vd->dualmaster) {
1896 pl08x->lli_buses = pl08x->pd->lli_buses;
1897 pl08x->mem_buses = pl08x->pd->mem_buses;
1900 /* A DMA memory pool for LLIs, align on 1-byte boundary */
1901 pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1902 PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1905 goto out_no_lli_pool;
1908 spin_lock_init(&pl08x->lock);
1910 pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1913 goto out_no_ioremap;
1916 /* Turn on the PL08x */
1917 pl08x_ensure_on(pl08x);
1919 /* Attach the interrupt handler */
1920 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1921 writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1923 ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
1924 DRIVER_NAME, pl08x);
1926 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1927 __func__, adev->irq[0]);
1931 /* Initialize physical channels */
1932 pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
1934 if (!pl08x->phy_chans) {
1935 dev_err(&adev->dev, "%s failed to allocate "
1936 "physical channel holders\n",
1938 goto out_no_phychans;
1941 for (i = 0; i < vd->channels; i++) {
1942 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1945 ch->base = pl08x->base + PL080_Cx_BASE(i);
1946 spin_lock_init(&ch->lock);
1949 dev_info(&adev->dev,
1950 "physical channel %d is %s\n", i,
1951 pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1954 /* Register as many memcpy channels as there are physical channels */
1955 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
1956 pl08x->vd->channels, false);
1958 dev_warn(&pl08x->adev->dev,
1959 "%s failed to enumerate memcpy channels - %d\n",
1963 pl08x->memcpy.chancnt = ret;
1965 /* Register slave channels */
1966 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
1967 pl08x->pd->num_slave_channels, true);
1969 dev_warn(&pl08x->adev->dev,
1970 "%s failed to enumerate slave channels - %d\n",
1974 pl08x->slave.chancnt = ret;
1976 ret = dma_async_device_register(&pl08x->memcpy);
1978 dev_warn(&pl08x->adev->dev,
1979 "%s failed to register memcpy as an async device - %d\n",
1981 goto out_no_memcpy_reg;
1984 ret = dma_async_device_register(&pl08x->slave);
1986 dev_warn(&pl08x->adev->dev,
1987 "%s failed to register slave as an async device - %d\n",
1989 goto out_no_slave_reg;
1992 amba_set_drvdata(adev, pl08x);
1993 init_pl08x_debugfs(pl08x);
1994 dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
1995 amba_part(adev), amba_rev(adev),
1996 (unsigned long long)adev->res.start, adev->irq[0]);
2000 dma_async_device_unregister(&pl08x->memcpy);
2002 pl08x_free_virtual_channels(&pl08x->slave);
2004 pl08x_free_virtual_channels(&pl08x->memcpy);
2006 kfree(pl08x->phy_chans);
2008 free_irq(adev->irq[0], pl08x);
2010 iounmap(pl08x->base);
2012 dma_pool_destroy(pl08x->pool);
2017 amba_release_regions(adev);
2021 /* PL080 has 8 channels and the PL080 have just 2 */
2022 static struct vendor_data vendor_pl080 = {
2027 static struct vendor_data vendor_pl081 = {
2029 .dualmaster = false,
2032 static struct amba_id pl08x_ids[] = {
2037 .data = &vendor_pl080,
2043 .data = &vendor_pl081,
2045 /* Nomadik 8815 PL080 variant */
2049 .data = &vendor_pl080,
2054 static struct amba_driver pl08x_amba_driver = {
2055 .drv.name = DRIVER_NAME,
2056 .id_table = pl08x_ids,
2057 .probe = pl08x_probe,
2060 static int __init pl08x_init(void)
2063 retval = amba_driver_register(&pl08x_amba_driver);
2065 printk(KERN_WARNING DRIVER_NAME
2066 "failed to register as an AMBA device (%d)\n",
2070 subsys_initcall(pl08x_init);