1 #include <linux/delay.h>
2 #include <linux/dmaengine.h>
3 #include <linux/dma-mapping.h>
4 #include <linux/platform_device.h>
5 #include <linux/module.h>
7 #include <linux/slab.h>
8 #include <linux/of_dma.h>
9 #include <linux/of_irq.h>
10 #include <linux/dmapool.h>
11 #include <linux/interrupt.h>
12 #include <linux/of_address.h>
13 #include <linux/pm_runtime.h>
14 #include "dmaengine.h"
17 #define DESC_TYPE_HOST 0x10
18 #define DESC_TYPE_TEARD 0x13
20 #define TD_DESC_IS_RX (1 << 16)
21 #define TD_DESC_DMA_NUM 10
23 #define DESC_LENGTH_BITS_NUM 21
25 #define DESC_TYPE_USB (5 << 26)
26 #define DESC_PD_COMPLETE (1 << 31)
30 #define DMA_TXGCR(x) (0x800 + (x) * 0x20)
31 #define DMA_RXGCR(x) (0x808 + (x) * 0x20)
34 #define GCR_CHAN_ENABLE (1 << 31)
35 #define GCR_TEARDOWN (1 << 30)
36 #define GCR_STARV_RETRY (1 << 24)
37 #define GCR_DESC_TYPE_HOST (1 << 14)
40 #define DMA_SCHED_CTRL 0
41 #define DMA_SCHED_CTRL_EN (1 << 31)
42 #define DMA_SCHED_WORD(x) ((x) * 4 + 0x800)
44 #define SCHED_ENTRY0_CHAN(x) ((x) << 0)
45 #define SCHED_ENTRY0_IS_RX (1 << 7)
47 #define SCHED_ENTRY1_CHAN(x) ((x) << 8)
48 #define SCHED_ENTRY1_IS_RX (1 << 15)
50 #define SCHED_ENTRY2_CHAN(x) ((x) << 16)
51 #define SCHED_ENTRY2_IS_RX (1 << 23)
53 #define SCHED_ENTRY3_CHAN(x) ((x) << 24)
54 #define SCHED_ENTRY3_IS_RX (1 << 31)
57 /* 4 KiB of memory for descriptors, 2 for each endpoint */
58 #define ALLOC_DECS_NUM 128
60 #define TOTAL_DESCS_NUM (ALLOC_DECS_NUM * DESCS_AREAS)
61 #define QMGR_SCRATCH_SIZE (TOTAL_DESCS_NUM * 4)
63 #define QMGR_LRAM0_BASE 0x80
64 #define QMGR_LRAM_SIZE 0x84
65 #define QMGR_LRAM1_BASE 0x88
66 #define QMGR_MEMBASE(x) (0x1000 + (x) * 0x10)
67 #define QMGR_MEMCTRL(x) (0x1004 + (x) * 0x10)
68 #define QMGR_MEMCTRL_IDX_SH 16
69 #define QMGR_MEMCTRL_DESC_SH 8
71 #define QMGR_NUM_PEND 5
72 #define QMGR_PEND(x) (0x90 + (x) * 4)
74 #define QMGR_PENDING_SLOT_Q(x) (x / 32)
75 #define QMGR_PENDING_BIT_Q(x) (x % 32)
77 #define QMGR_QUEUE_A(n) (0x2000 + (n) * 0x10)
78 #define QMGR_QUEUE_B(n) (0x2004 + (n) * 0x10)
79 #define QMGR_QUEUE_C(n) (0x2008 + (n) * 0x10)
80 #define QMGR_QUEUE_D(n) (0x200c + (n) * 0x10)
82 /* Glue layer specific */
83 /* USBSS / USB AM335x */
84 #define USBSS_IRQ_STATUS 0x28
85 #define USBSS_IRQ_ENABLER 0x2c
86 #define USBSS_IRQ_CLEARR 0x30
88 #define USBSS_IRQ_PD_COMP (1 << 2)
90 /* Packet Descriptor */
91 #define PD2_ZERO_LENGTH (1 << 19)
93 struct cppi41_channel {
95 struct dma_async_tx_descriptor txd;
96 struct cppi41_dd *cdd;
97 struct cppi41_desc *desc;
99 void __iomem *gcr_reg;
104 unsigned int q_comp_num;
105 unsigned int port_num;
108 unsigned td_queued:1;
110 unsigned td_desc_seen:1;
130 struct dma_device ddev;
133 dma_addr_t scratch_phys;
135 struct cppi41_desc *cd;
136 dma_addr_t descs_phys;
138 struct cppi41_channel *chan_busy[ALLOC_DECS_NUM];
140 void __iomem *usbss_mem;
141 void __iomem *ctrl_mem;
142 void __iomem *sched_mem;
143 void __iomem *qmgr_mem;
145 const struct chan_queues *queues_rx;
146 const struct chan_queues *queues_tx;
147 struct chan_queues td_queue;
149 /* context for suspend/resume */
150 unsigned int dma_tdfdq;
153 #define FIST_COMPLETION_QUEUE 93
154 static struct chan_queues usb_queues_tx[] = {
156 [ 0] = { .submit = 32, .complete = 93},
157 [ 1] = { .submit = 34, .complete = 94},
158 [ 2] = { .submit = 36, .complete = 95},
159 [ 3] = { .submit = 38, .complete = 96},
160 [ 4] = { .submit = 40, .complete = 97},
161 [ 5] = { .submit = 42, .complete = 98},
162 [ 6] = { .submit = 44, .complete = 99},
163 [ 7] = { .submit = 46, .complete = 100},
164 [ 8] = { .submit = 48, .complete = 101},
165 [ 9] = { .submit = 50, .complete = 102},
166 [10] = { .submit = 52, .complete = 103},
167 [11] = { .submit = 54, .complete = 104},
168 [12] = { .submit = 56, .complete = 105},
169 [13] = { .submit = 58, .complete = 106},
170 [14] = { .submit = 60, .complete = 107},
173 [15] = { .submit = 62, .complete = 125},
174 [16] = { .submit = 64, .complete = 126},
175 [17] = { .submit = 66, .complete = 127},
176 [18] = { .submit = 68, .complete = 128},
177 [19] = { .submit = 70, .complete = 129},
178 [20] = { .submit = 72, .complete = 130},
179 [21] = { .submit = 74, .complete = 131},
180 [22] = { .submit = 76, .complete = 132},
181 [23] = { .submit = 78, .complete = 133},
182 [24] = { .submit = 80, .complete = 134},
183 [25] = { .submit = 82, .complete = 135},
184 [26] = { .submit = 84, .complete = 136},
185 [27] = { .submit = 86, .complete = 137},
186 [28] = { .submit = 88, .complete = 138},
187 [29] = { .submit = 90, .complete = 139},
190 static const struct chan_queues usb_queues_rx[] = {
192 [ 0] = { .submit = 1, .complete = 109},
193 [ 1] = { .submit = 2, .complete = 110},
194 [ 2] = { .submit = 3, .complete = 111},
195 [ 3] = { .submit = 4, .complete = 112},
196 [ 4] = { .submit = 5, .complete = 113},
197 [ 5] = { .submit = 6, .complete = 114},
198 [ 6] = { .submit = 7, .complete = 115},
199 [ 7] = { .submit = 8, .complete = 116},
200 [ 8] = { .submit = 9, .complete = 117},
201 [ 9] = { .submit = 10, .complete = 118},
202 [10] = { .submit = 11, .complete = 119},
203 [11] = { .submit = 12, .complete = 120},
204 [12] = { .submit = 13, .complete = 121},
205 [13] = { .submit = 14, .complete = 122},
206 [14] = { .submit = 15, .complete = 123},
209 [15] = { .submit = 16, .complete = 141},
210 [16] = { .submit = 17, .complete = 142},
211 [17] = { .submit = 18, .complete = 143},
212 [18] = { .submit = 19, .complete = 144},
213 [19] = { .submit = 20, .complete = 145},
214 [20] = { .submit = 21, .complete = 146},
215 [21] = { .submit = 22, .complete = 147},
216 [22] = { .submit = 23, .complete = 148},
217 [23] = { .submit = 24, .complete = 149},
218 [24] = { .submit = 25, .complete = 150},
219 [25] = { .submit = 26, .complete = 151},
220 [26] = { .submit = 27, .complete = 152},
221 [27] = { .submit = 28, .complete = 153},
222 [28] = { .submit = 29, .complete = 154},
223 [29] = { .submit = 30, .complete = 155},
226 struct cppi_glue_infos {
227 irqreturn_t (*isr)(int irq, void *data);
228 const struct chan_queues *queues_rx;
229 const struct chan_queues *queues_tx;
230 struct chan_queues td_queue;
233 static struct cppi41_channel *to_cpp41_chan(struct dma_chan *c)
235 return container_of(c, struct cppi41_channel, chan);
238 static struct cppi41_channel *desc_to_chan(struct cppi41_dd *cdd, u32 desc)
240 struct cppi41_channel *c;
244 descs_size = sizeof(struct cppi41_desc) * ALLOC_DECS_NUM;
246 if (!((desc >= cdd->descs_phys) &&
247 (desc < (cdd->descs_phys + descs_size)))) {
251 desc_num = (desc - cdd->descs_phys) / sizeof(struct cppi41_desc);
252 BUG_ON(desc_num >= ALLOC_DECS_NUM);
253 c = cdd->chan_busy[desc_num];
254 cdd->chan_busy[desc_num] = NULL;
258 static void cppi_writel(u32 val, void *__iomem *mem)
260 __raw_writel(val, mem);
263 static u32 cppi_readl(void *__iomem *mem)
265 return __raw_readl(mem);
268 static u32 pd_trans_len(u32 val)
270 return val & ((1 << (DESC_LENGTH_BITS_NUM + 1)) - 1);
273 static u32 cppi41_pop_desc(struct cppi41_dd *cdd, unsigned queue_num)
277 desc = cppi_readl(cdd->qmgr_mem + QMGR_QUEUE_D(queue_num));
282 static irqreturn_t cppi41_irq(int irq, void *data)
284 struct cppi41_dd *cdd = data;
285 struct cppi41_channel *c;
289 status = cppi_readl(cdd->usbss_mem + USBSS_IRQ_STATUS);
290 if (!(status & USBSS_IRQ_PD_COMP))
292 cppi_writel(status, cdd->usbss_mem + USBSS_IRQ_STATUS);
294 for (i = QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE); i < QMGR_NUM_PEND;
299 val = cppi_readl(cdd->qmgr_mem + QMGR_PEND(i));
300 if (i == QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE) && val) {
302 /* set corresponding bit for completetion Q 93 */
303 mask = 1 << QMGR_PENDING_BIT_Q(FIST_COMPLETION_QUEUE);
304 /* not set all bits for queues less than Q 93 */
306 /* now invert and keep only Q 93+ set */
317 val &= ~(1 << q_num);
319 desc = cppi41_pop_desc(cdd, q_num);
320 c = desc_to_chan(cdd, desc);
322 pr_err("%s() q %d desc %08x\n", __func__,
327 if (c->desc->pd2 & PD2_ZERO_LENGTH)
330 len = pd_trans_len(c->desc->pd0);
332 c->residue = pd_trans_len(c->desc->pd6) - len;
333 dma_cookie_complete(&c->txd);
334 c->txd.callback(c->txd.callback_param);
340 static dma_cookie_t cppi41_tx_submit(struct dma_async_tx_descriptor *tx)
344 cookie = dma_cookie_assign(tx);
349 static int cppi41_dma_alloc_chan_resources(struct dma_chan *chan)
351 struct cppi41_channel *c = to_cpp41_chan(chan);
353 dma_cookie_init(chan);
354 dma_async_tx_descriptor_init(&c->txd, chan);
355 c->txd.tx_submit = cppi41_tx_submit;
358 cppi_writel(c->q_num, c->gcr_reg + RXHPCRA0);
363 static void cppi41_dma_free_chan_resources(struct dma_chan *chan)
367 static enum dma_status cppi41_dma_tx_status(struct dma_chan *chan,
368 dma_cookie_t cookie, struct dma_tx_state *txstate)
370 struct cppi41_channel *c = to_cpp41_chan(chan);
374 ret = dma_cookie_status(chan, cookie, txstate);
375 if (txstate && ret == DMA_COMPLETE)
376 txstate->residue = c->residue;
382 static void push_desc_queue(struct cppi41_channel *c)
384 struct cppi41_dd *cdd = c->cdd;
389 desc_phys = lower_32_bits(c->desc_phys);
390 desc_num = (desc_phys - cdd->descs_phys) / sizeof(struct cppi41_desc);
391 WARN_ON(cdd->chan_busy[desc_num]);
392 cdd->chan_busy[desc_num] = c;
394 reg = (sizeof(struct cppi41_desc) - 24) / 4;
396 cppi_writel(reg, cdd->qmgr_mem + QMGR_QUEUE_D(c->q_num));
399 static void cppi41_dma_issue_pending(struct dma_chan *chan)
401 struct cppi41_channel *c = to_cpp41_chan(chan);
406 reg = GCR_CHAN_ENABLE;
408 reg |= GCR_STARV_RETRY;
409 reg |= GCR_DESC_TYPE_HOST;
410 reg |= c->q_comp_num;
413 cppi_writel(reg, c->gcr_reg);
416 * We don't use writel() but __raw_writel() so we have to make sure
417 * that the DMA descriptor in coherent memory made to the main memory
418 * before starting the dma engine.
424 static u32 get_host_pd0(u32 length)
428 reg = DESC_TYPE_HOST << DESC_TYPE;
434 static u32 get_host_pd1(struct cppi41_channel *c)
443 static u32 get_host_pd2(struct cppi41_channel *c)
448 reg |= c->q_comp_num;
453 static u32 get_host_pd3(u32 length)
457 /* PD3 = packet size */
463 static u32 get_host_pd6(u32 length)
467 /* PD6 buffer size */
468 reg = DESC_PD_COMPLETE;
474 static u32 get_host_pd4_or_7(u32 addr)
483 static u32 get_host_pd5(void)
492 static struct dma_async_tx_descriptor *cppi41_dma_prep_slave_sg(
493 struct dma_chan *chan, struct scatterlist *sgl, unsigned sg_len,
494 enum dma_transfer_direction dir, unsigned long tx_flags, void *context)
496 struct cppi41_channel *c = to_cpp41_chan(chan);
497 struct cppi41_desc *d;
498 struct scatterlist *sg;
504 for_each_sg(sgl, sg, sg_len, i) {
508 /* We need to use more than one desc once musb supports sg */
510 addr = lower_32_bits(sg_dma_address(sg));
511 len = sg_dma_len(sg);
513 d->pd0 = get_host_pd0(len);
514 d->pd1 = get_host_pd1(c);
515 d->pd2 = get_host_pd2(c);
516 d->pd3 = get_host_pd3(len);
517 d->pd4 = get_host_pd4_or_7(addr);
518 d->pd5 = get_host_pd5();
519 d->pd6 = get_host_pd6(len);
520 d->pd7 = get_host_pd4_or_7(addr);
528 static void cppi41_compute_td_desc(struct cppi41_desc *d)
530 d->pd0 = DESC_TYPE_TEARD << DESC_TYPE;
533 static int cppi41_tear_down_chan(struct cppi41_channel *c)
535 struct cppi41_dd *cdd = c->cdd;
536 struct cppi41_desc *td;
542 td += cdd->first_td_desc;
544 td_desc_phys = cdd->descs_phys;
545 td_desc_phys += cdd->first_td_desc * sizeof(struct cppi41_desc);
548 cppi41_compute_td_desc(td);
551 reg = (sizeof(struct cppi41_desc) - 24) / 4;
553 cppi_writel(reg, cdd->qmgr_mem +
554 QMGR_QUEUE_D(cdd->td_queue.submit));
556 reg = GCR_CHAN_ENABLE;
558 reg |= GCR_STARV_RETRY;
559 reg |= GCR_DESC_TYPE_HOST;
560 reg |= c->q_comp_num;
563 cppi_writel(reg, c->gcr_reg);
568 if (!c->td_seen || !c->td_desc_seen) {
570 desc_phys = cppi41_pop_desc(cdd, cdd->td_queue.complete);
572 desc_phys = cppi41_pop_desc(cdd, c->q_comp_num);
574 if (desc_phys == c->desc_phys) {
577 } else if (desc_phys == td_desc_phys) {
582 WARN_ON((pd0 >> DESC_TYPE) != DESC_TYPE_TEARD);
583 WARN_ON(!c->is_tx && !(pd0 & TD_DESC_IS_RX));
584 WARN_ON((pd0 & 0x1f) != c->port_num);
586 } else if (desc_phys) {
592 * If the TX descriptor / channel is in use, the caller needs to poke
593 * his TD bit multiple times. After that he hardware releases the
594 * transfer descriptor followed by TD descriptor. Waiting seems not to
595 * cause any difference.
596 * RX seems to be thrown out right away. However once the TearDown
597 * descriptor gets through we are done. If we have seens the transfer
598 * descriptor before the TD we fetch it from enqueue, it has to be
599 * there waiting for us.
601 if (!c->td_seen && c->td_retry) {
605 WARN_ON(!c->td_retry);
607 if (!c->td_desc_seen) {
608 desc_phys = cppi41_pop_desc(cdd, c->q_num);
610 desc_phys = cppi41_pop_desc(cdd, c->q_comp_num);
617 cppi_writel(0, c->gcr_reg);
621 static int cppi41_stop_chan(struct dma_chan *chan)
623 struct cppi41_channel *c = to_cpp41_chan(chan);
624 struct cppi41_dd *cdd = c->cdd;
629 desc_phys = lower_32_bits(c->desc_phys);
630 desc_num = (desc_phys - cdd->descs_phys) / sizeof(struct cppi41_desc);
631 if (!cdd->chan_busy[desc_num])
634 ret = cppi41_tear_down_chan(c);
638 WARN_ON(!cdd->chan_busy[desc_num]);
639 cdd->chan_busy[desc_num] = NULL;
644 static void cleanup_chans(struct cppi41_dd *cdd)
646 while (!list_empty(&cdd->ddev.channels)) {
647 struct cppi41_channel *cchan;
649 cchan = list_first_entry(&cdd->ddev.channels,
650 struct cppi41_channel, chan.device_node);
651 list_del(&cchan->chan.device_node);
656 static int cppi41_add_chans(struct device *dev, struct cppi41_dd *cdd)
658 struct cppi41_channel *cchan;
663 ret = of_property_read_u32(dev->of_node, "#dma-channels",
668 * The channels can only be used as TX or as RX. So we add twice
669 * that much dma channels because USB can only do RX or TX.
673 for (i = 0; i < n_chans; i++) {
674 cchan = kzalloc(sizeof(*cchan), GFP_KERNEL);
680 cchan->gcr_reg = cdd->ctrl_mem + DMA_TXGCR(i >> 1);
683 cchan->gcr_reg = cdd->ctrl_mem + DMA_RXGCR(i >> 1);
686 cchan->port_num = i >> 1;
687 cchan->desc = &cdd->cd[i];
688 cchan->desc_phys = cdd->descs_phys;
689 cchan->desc_phys += i * sizeof(struct cppi41_desc);
690 cchan->chan.device = &cdd->ddev;
691 list_add_tail(&cchan->chan.device_node, &cdd->ddev.channels);
693 cdd->first_td_desc = n_chans;
701 static void purge_descs(struct device *dev, struct cppi41_dd *cdd)
703 unsigned int mem_decs;
706 mem_decs = ALLOC_DECS_NUM * sizeof(struct cppi41_desc);
708 for (i = 0; i < DESCS_AREAS; i++) {
710 cppi_writel(0, cdd->qmgr_mem + QMGR_MEMBASE(i));
711 cppi_writel(0, cdd->qmgr_mem + QMGR_MEMCTRL(i));
713 dma_free_coherent(dev, mem_decs, cdd->cd,
718 static void disable_sched(struct cppi41_dd *cdd)
720 cppi_writel(0, cdd->sched_mem + DMA_SCHED_CTRL);
723 static void deinit_cppi41(struct device *dev, struct cppi41_dd *cdd)
727 purge_descs(dev, cdd);
729 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM0_BASE);
730 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM0_BASE);
731 dma_free_coherent(dev, QMGR_SCRATCH_SIZE, cdd->qmgr_scratch,
735 static int init_descs(struct device *dev, struct cppi41_dd *cdd)
737 unsigned int desc_size;
738 unsigned int mem_decs;
743 BUILD_BUG_ON(sizeof(struct cppi41_desc) &
744 (sizeof(struct cppi41_desc) - 1));
745 BUILD_BUG_ON(sizeof(struct cppi41_desc) < 32);
746 BUILD_BUG_ON(ALLOC_DECS_NUM < 32);
748 desc_size = sizeof(struct cppi41_desc);
749 mem_decs = ALLOC_DECS_NUM * desc_size;
752 for (i = 0; i < DESCS_AREAS; i++) {
754 reg = idx << QMGR_MEMCTRL_IDX_SH;
755 reg |= (ilog2(desc_size) - 5) << QMGR_MEMCTRL_DESC_SH;
756 reg |= ilog2(ALLOC_DECS_NUM) - 5;
758 BUILD_BUG_ON(DESCS_AREAS != 1);
759 cdd->cd = dma_alloc_coherent(dev, mem_decs,
760 &cdd->descs_phys, GFP_KERNEL);
764 cppi_writel(cdd->descs_phys, cdd->qmgr_mem + QMGR_MEMBASE(i));
765 cppi_writel(reg, cdd->qmgr_mem + QMGR_MEMCTRL(i));
767 idx += ALLOC_DECS_NUM;
772 static void init_sched(struct cppi41_dd *cdd)
779 cppi_writel(0, cdd->sched_mem + DMA_SCHED_CTRL);
780 for (ch = 0; ch < 15 * 2; ch += 2) {
782 reg = SCHED_ENTRY0_CHAN(ch);
783 reg |= SCHED_ENTRY1_CHAN(ch) | SCHED_ENTRY1_IS_RX;
785 reg |= SCHED_ENTRY2_CHAN(ch + 1);
786 reg |= SCHED_ENTRY3_CHAN(ch + 1) | SCHED_ENTRY3_IS_RX;
787 cppi_writel(reg, cdd->sched_mem + DMA_SCHED_WORD(word));
790 reg = 15 * 2 * 2 - 1;
791 reg |= DMA_SCHED_CTRL_EN;
792 cppi_writel(reg, cdd->sched_mem + DMA_SCHED_CTRL);
795 static int init_cppi41(struct device *dev, struct cppi41_dd *cdd)
799 BUILD_BUG_ON(QMGR_SCRATCH_SIZE > ((1 << 14) - 1));
800 cdd->qmgr_scratch = dma_alloc_coherent(dev, QMGR_SCRATCH_SIZE,
801 &cdd->scratch_phys, GFP_KERNEL);
802 if (!cdd->qmgr_scratch)
805 cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE);
806 cppi_writel(QMGR_SCRATCH_SIZE, cdd->qmgr_mem + QMGR_LRAM_SIZE);
807 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE);
809 ret = init_descs(dev, cdd);
813 cppi_writel(cdd->td_queue.submit, cdd->ctrl_mem + DMA_TDFDQ);
817 deinit_cppi41(dev, cdd);
821 static struct platform_driver cpp41_dma_driver;
823 * The param format is:
831 static bool cpp41_dma_filter_fn(struct dma_chan *chan, void *param)
833 struct cppi41_channel *cchan;
834 struct cppi41_dd *cdd;
835 const struct chan_queues *queues;
838 if (chan->device->dev->driver != &cpp41_dma_driver.driver)
841 cchan = to_cpp41_chan(chan);
843 if (cchan->port_num != num[INFO_PORT])
846 if (cchan->is_tx && !num[INFO_IS_TX])
850 queues = cdd->queues_tx;
852 queues = cdd->queues_rx;
854 BUILD_BUG_ON(ARRAY_SIZE(usb_queues_rx) != ARRAY_SIZE(usb_queues_tx));
855 if (WARN_ON(cchan->port_num > ARRAY_SIZE(usb_queues_rx)))
858 cchan->q_num = queues[cchan->port_num].submit;
859 cchan->q_comp_num = queues[cchan->port_num].complete;
863 static struct of_dma_filter_info cpp41_dma_info = {
864 .filter_fn = cpp41_dma_filter_fn,
867 static struct dma_chan *cppi41_dma_xlate(struct of_phandle_args *dma_spec,
868 struct of_dma *ofdma)
870 int count = dma_spec->args_count;
871 struct of_dma_filter_info *info = ofdma->of_dma_data;
873 if (!info || !info->filter_fn)
879 return dma_request_channel(info->dma_cap, info->filter_fn,
883 static const struct cppi_glue_infos usb_infos = {
885 .queues_rx = usb_queues_rx,
886 .queues_tx = usb_queues_tx,
887 .td_queue = { .submit = 31, .complete = 0 },
890 static const struct of_device_id cppi41_dma_ids[] = {
891 { .compatible = "ti,am3359-cppi41", .data = &usb_infos},
894 MODULE_DEVICE_TABLE(of, cppi41_dma_ids);
896 static const struct cppi_glue_infos *get_glue_info(struct device *dev)
898 const struct of_device_id *of_id;
900 of_id = of_match_node(cppi41_dma_ids, dev->of_node);
906 static int cppi41_dma_probe(struct platform_device *pdev)
908 struct cppi41_dd *cdd;
909 struct device *dev = &pdev->dev;
910 const struct cppi_glue_infos *glue_info;
914 glue_info = get_glue_info(dev);
918 cdd = devm_kzalloc(&pdev->dev, sizeof(*cdd), GFP_KERNEL);
922 dma_cap_set(DMA_SLAVE, cdd->ddev.cap_mask);
923 cdd->ddev.device_alloc_chan_resources = cppi41_dma_alloc_chan_resources;
924 cdd->ddev.device_free_chan_resources = cppi41_dma_free_chan_resources;
925 cdd->ddev.device_tx_status = cppi41_dma_tx_status;
926 cdd->ddev.device_issue_pending = cppi41_dma_issue_pending;
927 cdd->ddev.device_prep_slave_sg = cppi41_dma_prep_slave_sg;
928 cdd->ddev.device_terminate_all = cppi41_stop_chan;
930 INIT_LIST_HEAD(&cdd->ddev.channels);
931 cpp41_dma_info.dma_cap = cdd->ddev.cap_mask;
933 cdd->usbss_mem = of_iomap(dev->of_node, 0);
934 cdd->ctrl_mem = of_iomap(dev->of_node, 1);
935 cdd->sched_mem = of_iomap(dev->of_node, 2);
936 cdd->qmgr_mem = of_iomap(dev->of_node, 3);
938 if (!cdd->usbss_mem || !cdd->ctrl_mem || !cdd->sched_mem ||
942 pm_runtime_enable(dev);
943 ret = pm_runtime_get_sync(dev);
947 cdd->queues_rx = glue_info->queues_rx;
948 cdd->queues_tx = glue_info->queues_tx;
949 cdd->td_queue = glue_info->td_queue;
951 ret = init_cppi41(dev, cdd);
955 ret = cppi41_add_chans(dev, cdd);
959 irq = irq_of_parse_and_map(dev->of_node, 0);
965 cppi_writel(USBSS_IRQ_PD_COMP, cdd->usbss_mem + USBSS_IRQ_ENABLER);
967 ret = devm_request_irq(&pdev->dev, irq, glue_info->isr, IRQF_SHARED,
973 ret = dma_async_device_register(&cdd->ddev);
977 ret = of_dma_controller_register(dev->of_node,
978 cppi41_dma_xlate, &cpp41_dma_info);
982 platform_set_drvdata(pdev, cdd);
985 dma_async_device_unregister(&cdd->ddev);
988 cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
991 deinit_cppi41(dev, cdd);
995 pm_runtime_disable(dev);
996 iounmap(cdd->usbss_mem);
997 iounmap(cdd->ctrl_mem);
998 iounmap(cdd->sched_mem);
999 iounmap(cdd->qmgr_mem);
1003 static int cppi41_dma_remove(struct platform_device *pdev)
1005 struct cppi41_dd *cdd = platform_get_drvdata(pdev);
1007 of_dma_controller_free(pdev->dev.of_node);
1008 dma_async_device_unregister(&cdd->ddev);
1010 cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
1011 devm_free_irq(&pdev->dev, cdd->irq, cdd);
1013 deinit_cppi41(&pdev->dev, cdd);
1014 iounmap(cdd->usbss_mem);
1015 iounmap(cdd->ctrl_mem);
1016 iounmap(cdd->sched_mem);
1017 iounmap(cdd->qmgr_mem);
1018 pm_runtime_put(&pdev->dev);
1019 pm_runtime_disable(&pdev->dev);
1023 #ifdef CONFIG_PM_SLEEP
1024 static int cppi41_suspend(struct device *dev)
1026 struct cppi41_dd *cdd = dev_get_drvdata(dev);
1028 cdd->dma_tdfdq = cppi_readl(cdd->ctrl_mem + DMA_TDFDQ);
1029 cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
1035 static int cppi41_resume(struct device *dev)
1037 struct cppi41_dd *cdd = dev_get_drvdata(dev);
1038 struct cppi41_channel *c;
1041 for (i = 0; i < DESCS_AREAS; i++)
1042 cppi_writel(cdd->descs_phys, cdd->qmgr_mem + QMGR_MEMBASE(i));
1044 list_for_each_entry(c, &cdd->ddev.channels, chan.device_node)
1046 cppi_writel(c->q_num, c->gcr_reg + RXHPCRA0);
1050 cppi_writel(cdd->dma_tdfdq, cdd->ctrl_mem + DMA_TDFDQ);
1051 cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE);
1052 cppi_writel(QMGR_SCRATCH_SIZE, cdd->qmgr_mem + QMGR_LRAM_SIZE);
1053 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE);
1055 cppi_writel(USBSS_IRQ_PD_COMP, cdd->usbss_mem + USBSS_IRQ_ENABLER);
1061 static SIMPLE_DEV_PM_OPS(cppi41_pm_ops, cppi41_suspend, cppi41_resume);
1063 static struct platform_driver cpp41_dma_driver = {
1064 .probe = cppi41_dma_probe,
1065 .remove = cppi41_dma_remove,
1067 .name = "cppi41-dma-engine",
1068 .pm = &cppi41_pm_ops,
1069 .of_match_table = of_match_ptr(cppi41_dma_ids),
1073 module_platform_driver(cpp41_dma_driver);
1074 MODULE_LICENSE("GPL");
1075 MODULE_AUTHOR("Sebastian Andrzej Siewior <bigeasy@linutronix.de>");