drivers/dma/dw/core.c

   1 /*
   2  * Core driver for the Synopsys DesignWare DMA Controller
   3  *
   4  * Copyright (C) 2007-2008 Atmel Corporation
   5  * Copyright (C) 2010-2011 ST Microelectronics
   6  * Copyright (C) 2013 Intel Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/bitops.h>
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/dmaengine.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/dmapool.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/mm.h>
  24 #include <linux/module.h>
  25 #include <linux/slab.h>
  26
  27 #include "../dmaengine.h"
  28 #include "internal.h"
  29
  30 /*
  31  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
  32  * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
  33  * of which use ARM any more).  See the "Databook" from Synopsys for
  34  * information beyond what licensees probably provide.
  35  *
  36  * The driver has been tested with the Atmel AT32AP7000, which does not
  37  * support descriptor writeback.
  38  */
  39
  40 #define DWC_DEFAULT_CTLLO(_chan) ({                             \
  41                 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan);       \
  42                 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
  43                 bool _is_slave = is_slave_direction(_dwc->direction);   \
  44                 u8 _smsize = _is_slave ? _sconfig->src_maxburst :       \
  45                         DW_DMA_MSIZE_16;                        \
  46                 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst :       \
  47                         DW_DMA_MSIZE_16;                        \
  48                                                                 \
  49                 (DWC_CTLL_DST_MSIZE(_dmsize)                    \
  50                  | DWC_CTLL_SRC_MSIZE(_smsize)                  \
  51                  | DWC_CTLL_LLP_D_EN                            \
  52                  | DWC_CTLL_LLP_S_EN                            \
  53                  | DWC_CTLL_DMS(_dwc->dst_master)               \
  54                  | DWC_CTLL_SMS(_dwc->src_master));             \
  55         })
  56
  57 /*
  58  * Number of descriptors to allocate for each channel. This should be
  59  * made configurable somehow; preferably, the clients (at least the
  60  * ones using slave transfers) should be able to give us a hint.
  61  */
  62 #define NR_DESCS_PER_CHANNEL    64
  63
  64 /*----------------------------------------------------------------------*/
  65
  66 static struct device *chan2dev(struct dma_chan *chan)
  67 {
  68         return &chan->dev->device;
  69 }
  70
  71 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
  72 {
  73         return to_dw_desc(dwc->active_list.next);
  74 }
  75
  76 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
  77 {
  78         struct dw_desc *desc, *_desc;
  79         struct dw_desc *ret = NULL;
  80         unsigned int i = 0;
  81         unsigned long flags;
  82
  83         spin_lock_irqsave(&dwc->lock, flags);
  84         list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
  85                 i++;
  86                 if (async_tx_test_ack(&desc->txd)) {
  87                         list_del(&desc->desc_node);
  88                         ret = desc;
  89                         break;
  90                 }
  91                 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
  92         }
  93         spin_unlock_irqrestore(&dwc->lock, flags);
  94
  95         dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
  96
  97         return ret;
  98 }
  99
 100 /*
 101  * Move a descriptor, including any children, to the free list.
 102  * `desc' must not be on any lists.
 103  */
 104 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
 105 {
 106         unsigned long flags;
 107
 108         if (desc) {
 109                 struct dw_desc *child;
 110
 111                 spin_lock_irqsave(&dwc->lock, flags);
 112                 list_for_each_entry(child, &desc->tx_list, desc_node)
 113                         dev_vdbg(chan2dev(&dwc->chan),
 114                                         "moving child desc %p to freelist\n",
 115                                         child);
 116                 list_splice_init(&desc->tx_list, &dwc->free_list);
 117                 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
 118                 list_add(&desc->desc_node, &dwc->free_list);
 119                 spin_unlock_irqrestore(&dwc->lock, flags);
 120         }
 121 }
 122
 123 static void dwc_initialize(struct dw_dma_chan *dwc)
 124 {
 125         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
 126         struct dw_dma_slave *dws = dwc->chan.private;
 127         u32 cfghi = DWC_CFGH_FIFO_MODE;
 128         u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
 129
 130         if (dwc->initialized == true)
 131                 return;
 132
 133         if (dws) {
 134                 /*
 135                  * We need controller-specific data to set up slave
 136                  * transfers.
 137                  */
 138                 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
 139
 140                 cfghi |= DWC_CFGH_DST_PER(dws->dst_id);
 141                 cfghi |= DWC_CFGH_SRC_PER(dws->src_id);
 142         } else {
 143                 cfghi |= DWC_CFGH_DST_PER(dwc->dst_id);
 144                 cfghi |= DWC_CFGH_SRC_PER(dwc->src_id);
 145         }
 146
 147         channel_writel(dwc, CFG_LO, cfglo);
 148         channel_writel(dwc, CFG_HI, cfghi);
 149
 150         /* Enable interrupts */
 151         channel_set_bit(dw, MASK.XFER, dwc->mask);
 152         channel_set_bit(dw, MASK.ERROR, dwc->mask);
 153
 154         dwc->initialized = true;
 155 }
 156
 157 /*----------------------------------------------------------------------*/
 158
 159 static inline unsigned int dwc_fast_fls(unsigned long long v)
 160 {
 161         /*
 162          * We can be a lot more clever here, but this should take care
 163          * of the most common optimization.
 164          */
 165         if (!(v & 7))
 166                 return 3;
 167         else if (!(v & 3))
 168                 return 2;
 169         else if (!(v & 1))
 170                 return 1;
 171         return 0;
 172 }
 173
 174 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
 175 {
 176         dev_err(chan2dev(&dwc->chan),
 177                 "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
 178                 channel_readl(dwc, SAR),
 179                 channel_readl(dwc, DAR),
 180                 channel_readl(dwc, LLP),
 181                 channel_readl(dwc, CTL_HI),
 182                 channel_readl(dwc, CTL_LO));
 183 }
 184
 185 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
 186 {
 187         channel_clear_bit(dw, CH_EN, dwc->mask);
 188         while (dma_readl(dw, CH_EN) & dwc->mask)
 189                 cpu_relax();
 190 }
 191
 192 /*----------------------------------------------------------------------*/
 193
 194 /* Perform single block transfer */
 195 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
 196                                        struct dw_desc *desc)
 197 {
 198         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 199         u32             ctllo;
 200
 201         /*
 202          * Software emulation of LLP mode relies on interrupts to continue
 203          * multi block transfer.
 204          */
 205         ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
 206
 207         channel_writel(dwc, SAR, desc->lli.sar);
 208         channel_writel(dwc, DAR, desc->lli.dar);
 209         channel_writel(dwc, CTL_LO, ctllo);
 210         channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
 211         channel_set_bit(dw, CH_EN, dwc->mask);
 212
 213         /* Move pointer to next descriptor */
 214         dwc->tx_node_active = dwc->tx_node_active->next;
 215 }
 216
 217 /* Called with dwc->lock held and bh disabled */
 218 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
 219 {
 220         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 221         unsigned long   was_soft_llp;
 222
 223         /* ASSERT:  channel is idle */
 224         if (dma_readl(dw, CH_EN) & dwc->mask) {
 225                 dev_err(chan2dev(&dwc->chan),
 226                         "BUG: Attempted to start non-idle channel\n");
 227                 dwc_dump_chan_regs(dwc);
 228
 229                 /* The tasklet will hopefully advance the queue... */
 230                 return;
 231         }
 232
 233         if (dwc->nollp) {
 234                 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
 235                                                 &dwc->flags);
 236                 if (was_soft_llp) {
 237                         dev_err(chan2dev(&dwc->chan),
 238                                 "BUG: Attempted to start new LLP transfer inside ongoing one\n");
 239                         return;
 240                 }
 241
 242                 dwc_initialize(dwc);
 243
 244                 dwc->residue = first->total_len;
 245                 dwc->tx_node_active = &first->tx_list;
 246
 247                 /* Submit first block */
 248                 dwc_do_single_block(dwc, first);
 249
 250                 return;
 251         }
 252
 253         dwc_initialize(dwc);
 254
 255         channel_writel(dwc, LLP, first->txd.phys);
 256         channel_writel(dwc, CTL_LO,
 257                         DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 258         channel_writel(dwc, CTL_HI, 0);
 259         channel_set_bit(dw, CH_EN, dwc->mask);
 260 }
 261
 262 static void dwc_dostart_first_queued(struct dw_dma_chan *dwc)
 263 {
 264         struct dw_desc *desc;
 265
 266         if (list_empty(&dwc->queue))
 267                 return;
 268
 269         list_move(dwc->queue.next, &dwc->active_list);
 270         desc = dwc_first_active(dwc);
 271         dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie);
 272         dwc_dostart(dwc, desc);
 273 }
 274
 275 /*----------------------------------------------------------------------*/
 276
 277 static void
 278 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
 279                 bool callback_required)
 280 {
 281         dma_async_tx_callback           callback = NULL;
 282         void                            *param = NULL;
 283         struct dma_async_tx_descriptor  *txd = &desc->txd;
 284         struct dw_desc                  *child;
 285         unsigned long                   flags;
 286
 287         dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 288
 289         spin_lock_irqsave(&dwc->lock, flags);
 290         dma_cookie_complete(txd);
 291         if (callback_required) {
 292                 callback = txd->callback;
 293                 param = txd->callback_param;
 294         }
 295
 296         /* async_tx_ack */
 297         list_for_each_entry(child, &desc->tx_list, desc_node)
 298                 async_tx_ack(&child->txd);
 299         async_tx_ack(&desc->txd);
 300
 301         list_splice_init(&desc->tx_list, &dwc->free_list);
 302         list_move(&desc->desc_node, &dwc->free_list);
 303
 304         dma_descriptor_unmap(txd);
 305         spin_unlock_irqrestore(&dwc->lock, flags);
 306
 307         if (callback)
 308                 callback(param);
 309 }
 310
 311 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
 312 {
 313         struct dw_desc *desc, *_desc;
 314         LIST_HEAD(list);
 315         unsigned long flags;
 316
 317         spin_lock_irqsave(&dwc->lock, flags);
 318         if (dma_readl(dw, CH_EN) & dwc->mask) {
 319                 dev_err(chan2dev(&dwc->chan),
 320                         "BUG: XFER bit set, but channel not idle!\n");
 321
 322                 /* Try to continue after resetting the channel... */
 323                 dwc_chan_disable(dw, dwc);
 324         }
 325
 326         /*
 327          * Submit queued descriptors ASAP, i.e. before we go through
 328          * the completed ones.
 329          */
 330         list_splice_init(&dwc->active_list, &list);
 331         dwc_dostart_first_queued(dwc);
 332
 333         spin_unlock_irqrestore(&dwc->lock, flags);
 334
 335         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 336                 dwc_descriptor_complete(dwc, desc, true);
 337 }
 338
 339 /* Returns how many bytes were already received from source */
 340 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
 341 {
 342         u32 ctlhi = channel_readl(dwc, CTL_HI);
 343         u32 ctllo = channel_readl(dwc, CTL_LO);
 344
 345         return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
 346 }
 347
 348 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 349 {
 350         dma_addr_t llp;
 351         struct dw_desc *desc, *_desc;
 352         struct dw_desc *child;
 353         u32 status_xfer;
 354         unsigned long flags;
 355
 356         spin_lock_irqsave(&dwc->lock, flags);
 357         llp = channel_readl(dwc, LLP);
 358         status_xfer = dma_readl(dw, RAW.XFER);
 359
 360         if (status_xfer & dwc->mask) {
 361                 /* Everything we've submitted is done */
 362                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 363
 364                 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 365                         struct list_head *head, *active = dwc->tx_node_active;
 366
 367                         /*
 368                          * We are inside first active descriptor.
 369                          * Otherwise something is really wrong.
 370                          */
 371                         desc = dwc_first_active(dwc);
 372
 373                         head = &desc->tx_list;
 374                         if (active != head) {
 375                                 /* Update desc to reflect last sent one */
 376                                 if (active != head->next)
 377                                         desc = to_dw_desc(active->prev);
 378
 379                                 dwc->residue -= desc->len;
 380
 381                                 child = to_dw_desc(active);
 382
 383                                 /* Submit next block */
 384                                 dwc_do_single_block(dwc, child);
 385
 386                                 spin_unlock_irqrestore(&dwc->lock, flags);
 387                                 return;
 388                         }
 389
 390                         /* We are done here */
 391                         clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
 392                 }
 393
 394                 dwc->residue = 0;
 395
 396                 spin_unlock_irqrestore(&dwc->lock, flags);
 397
 398                 dwc_complete_all(dw, dwc);
 399                 return;
 400         }
 401
 402         if (list_empty(&dwc->active_list)) {
 403                 dwc->residue = 0;
 404                 spin_unlock_irqrestore(&dwc->lock, flags);
 405                 return;
 406         }
 407
 408         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 409                 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
 410                 spin_unlock_irqrestore(&dwc->lock, flags);
 411                 return;
 412         }
 413
 414         dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp);
 415
 416         list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
 417                 /* Initial residue value */
 418                 dwc->residue = desc->total_len;
 419
 420                 /* Check first descriptors addr */
 421                 if (desc->txd.phys == llp) {
 422                         spin_unlock_irqrestore(&dwc->lock, flags);
 423                         return;
 424                 }
 425
 426                 /* Check first descriptors llp */
 427                 if (desc->lli.llp == llp) {
 428                         /* This one is currently in progress */
 429                         dwc->residue -= dwc_get_sent(dwc);
 430                         spin_unlock_irqrestore(&dwc->lock, flags);
 431                         return;
 432                 }
 433
 434                 dwc->residue -= desc->len;
 435                 list_for_each_entry(child, &desc->tx_list, desc_node) {
 436                         if (child->lli.llp == llp) {
 437                                 /* Currently in progress */
 438                                 dwc->residue -= dwc_get_sent(dwc);
 439                                 spin_unlock_irqrestore(&dwc->lock, flags);
 440                                 return;
 441                         }
 442                         dwc->residue -= child->len;
 443                 }
 444
 445                 /*
 446                  * No descriptors so far seem to be in progress, i.e.
 447                  * this one must be done.
 448                  */
 449                 spin_unlock_irqrestore(&dwc->lock, flags);
 450                 dwc_descriptor_complete(dwc, desc, true);
 451                 spin_lock_irqsave(&dwc->lock, flags);
 452         }
 453
 454         dev_err(chan2dev(&dwc->chan),
 455                 "BUG: All descriptors done, but channel not idle!\n");
 456
 457         /* Try to continue after resetting the channel... */
 458         dwc_chan_disable(dw, dwc);
 459
 460         dwc_dostart_first_queued(dwc);
 461         spin_unlock_irqrestore(&dwc->lock, flags);
 462 }
 463
 464 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
 465 {
 466         dev_crit(chan2dev(&dwc->chan), "  desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
 467                  lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
 468 }
 469
 470 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
 471 {
 472         struct dw_desc *bad_desc;
 473         struct dw_desc *child;
 474         unsigned long flags;
 475
 476         dwc_scan_descriptors(dw, dwc);
 477
 478         spin_lock_irqsave(&dwc->lock, flags);
 479
 480         /*
 481          * The descriptor currently at the head of the active list is
 482          * borked. Since we don't have any way to report errors, we'll
 483          * just have to scream loudly and try to carry on.
 484          */
 485         bad_desc = dwc_first_active(dwc);
 486         list_del_init(&bad_desc->desc_node);
 487         list_move(dwc->queue.next, dwc->active_list.prev);
 488
 489         /* Clear the error flag and try to restart the controller */
 490         dma_writel(dw, CLEAR.ERROR, dwc->mask);
 491         if (!list_empty(&dwc->active_list))
 492                 dwc_dostart(dwc, dwc_first_active(dwc));
 493
 494         /*
 495          * WARN may seem harsh, but since this only happens
 496          * when someone submits a bad physical address in a
 497          * descriptor, we should consider ourselves lucky that the
 498          * controller flagged an error instead of scribbling over
 499          * random memory locations.
 500          */
 501         dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
 502                                        "  cookie: %d\n", bad_desc->txd.cookie);
 503         dwc_dump_lli(dwc, &bad_desc->lli);
 504         list_for_each_entry(child, &bad_desc->tx_list, desc_node)
 505                 dwc_dump_lli(dwc, &child->lli);
 506
 507         spin_unlock_irqrestore(&dwc->lock, flags);
 508
 509         /* Pretend the descriptor completed successfully */
 510         dwc_descriptor_complete(dwc, bad_desc, true);
 511 }
 512
 513 /* --------------------- Cyclic DMA API extensions -------------------- */
 514
 515 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
 516 {
 517         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 518         return channel_readl(dwc, SAR);
 519 }
 520 EXPORT_SYMBOL(dw_dma_get_src_addr);
 521
 522 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
 523 {
 524         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 525         return channel_readl(dwc, DAR);
 526 }
 527 EXPORT_SYMBOL(dw_dma_get_dst_addr);
 528
 529 /* Called with dwc->lock held and all DMAC interrupts disabled */
 530 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
 531                 u32 status_err, u32 status_xfer)
 532 {
 533         unsigned long flags;
 534
 535         if (dwc->mask) {
 536                 void (*callback)(void *param);
 537                 void *callback_param;
 538
 539                 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
 540                                 channel_readl(dwc, LLP));
 541
 542                 callback = dwc->cdesc->period_callback;
 543                 callback_param = dwc->cdesc->period_callback_param;
 544
 545                 if (callback)
 546                         callback(callback_param);
 547         }
 548
 549         /*
 550          * Error and transfer complete are highly unlikely, and will most
 551          * likely be due to a configuration error by the user.
 552          */
 553         if (unlikely(status_err & dwc->mask) ||
 554                         unlikely(status_xfer & dwc->mask)) {
 555                 int i;
 556
 557                 dev_err(chan2dev(&dwc->chan),
 558                         "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n",
 559                         status_xfer ? "xfer" : "error");
 560
 561                 spin_lock_irqsave(&dwc->lock, flags);
 562
 563                 dwc_dump_chan_regs(dwc);
 564
 565                 dwc_chan_disable(dw, dwc);
 566
 567                 /* Make sure DMA does not restart by loading a new list */
 568                 channel_writel(dwc, LLP, 0);
 569                 channel_writel(dwc, CTL_LO, 0);
 570                 channel_writel(dwc, CTL_HI, 0);
 571
 572                 dma_writel(dw, CLEAR.ERROR, dwc->mask);
 573                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 574
 575                 for (i = 0; i < dwc->cdesc->periods; i++)
 576                         dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
 577
 578                 spin_unlock_irqrestore(&dwc->lock, flags);
 579         }
 580 }
 581
 582 /* ------------------------------------------------------------------------- */
 583
 584 static void dw_dma_tasklet(unsigned long data)
 585 {
 586         struct dw_dma *dw = (struct dw_dma *)data;
 587         struct dw_dma_chan *dwc;
 588         u32 status_xfer;
 589         u32 status_err;
 590         int i;
 591
 592         status_xfer = dma_readl(dw, RAW.XFER);
 593         status_err = dma_readl(dw, RAW.ERROR);
 594
 595         dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
 596
 597         for (i = 0; i < dw->dma.chancnt; i++) {
 598                 dwc = &dw->chan[i];
 599                 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
 600                         dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
 601                 else if (status_err & (1 << i))
 602                         dwc_handle_error(dw, dwc);
 603                 else if (status_xfer & (1 << i))
 604                         dwc_scan_descriptors(dw, dwc);
 605         }
 606
 607         /*
 608          * Re-enable interrupts.
 609          */
 610         channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
 611         channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
 612 }
 613
 614 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
 615 {
 616         struct dw_dma *dw = dev_id;
 617         u32 status = dma_readl(dw, STATUS_INT);
 618
 619         dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
 620
 621         /* Check if we have any interrupt from the DMAC */
 622         if (!status)
 623                 return IRQ_NONE;
 624
 625         /*
 626          * Just disable the interrupts. We'll turn them back on in the
 627          * softirq handler.
 628          */
 629         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
 630         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
 631
 632         status = dma_readl(dw, STATUS_INT);
 633         if (status) {
 634                 dev_err(dw->dma.dev,
 635                         "BUG: Unexpected interrupts pending: 0x%x\n",
 636                         status);
 637
 638                 /* Try to recover */
 639                 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
 640                 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
 641                 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
 642                 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
 643         }
 644
 645         tasklet_schedule(&dw->tasklet);
 646
 647         return IRQ_HANDLED;
 648 }
 649
 650 /*----------------------------------------------------------------------*/
 651
 652 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
 653 {
 654         struct dw_desc          *desc = txd_to_dw_desc(tx);
 655         struct dw_dma_chan      *dwc = to_dw_dma_chan(tx->chan);
 656         dma_cookie_t            cookie;
 657         unsigned long           flags;
 658
 659         spin_lock_irqsave(&dwc->lock, flags);
 660         cookie = dma_cookie_assign(tx);
 661
 662         /*
 663          * REVISIT: We should attempt to chain as many descriptors as
 664          * possible, perhaps even appending to those already submitted
 665          * for DMA. But this is hard to do in a race-free manner.
 666          */
 667
 668         dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie);
 669         list_add_tail(&desc->desc_node, &dwc->queue);
 670
 671         spin_unlock_irqrestore(&dwc->lock, flags);
 672
 673         return cookie;
 674 }
 675
 676 static struct dma_async_tx_descriptor *
 677 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 678                 size_t len, unsigned long flags)
 679 {
 680         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 681         struct dw_dma           *dw = to_dw_dma(chan->device);
 682         struct dw_desc          *desc;
 683         struct dw_desc          *first;
 684         struct dw_desc          *prev;
 685         size_t                  xfer_count;
 686         size_t                  offset;
 687         unsigned int            src_width;
 688         unsigned int            dst_width;
 689         unsigned int            data_width;
 690         u32                     ctllo;
 691
 692         dev_vdbg(chan2dev(chan),
 693                         "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
 694                         &dest, &src, len, flags);
 695
 696         if (unlikely(!len)) {
 697                 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
 698                 return NULL;
 699         }
 700
 701         dwc->direction = DMA_MEM_TO_MEM;
 702
 703         data_width = min_t(unsigned int, dw->data_width[dwc->src_master],
 704                            dw->data_width[dwc->dst_master]);
 705
 706         src_width = dst_width = min_t(unsigned int, data_width,
 707                                       dwc_fast_fls(src | dest | len));
 708
 709         ctllo = DWC_DEFAULT_CTLLO(chan)
 710                         | DWC_CTLL_DST_WIDTH(dst_width)
 711                         | DWC_CTLL_SRC_WIDTH(src_width)
 712                         | DWC_CTLL_DST_INC
 713                         | DWC_CTLL_SRC_INC
 714                         | DWC_CTLL_FC_M2M;
 715         prev = first = NULL;
 716
 717         for (offset = 0; offset < len; offset += xfer_count << src_width) {
 718                 xfer_count = min_t(size_t, (len - offset) >> src_width,
 719                                            dwc->block_size);
 720
 721                 desc = dwc_desc_get(dwc);
 722                 if (!desc)
 723                         goto err_desc_get;
 724
 725                 desc->lli.sar = src + offset;
 726                 desc->lli.dar = dest + offset;
 727                 desc->lli.ctllo = ctllo;
 728                 desc->lli.ctlhi = xfer_count;
 729                 desc->len = xfer_count << src_width;
 730
 731                 if (!first) {
 732                         first = desc;
 733                 } else {
 734                         prev->lli.llp = desc->txd.phys;
 735                         list_add_tail(&desc->desc_node,
 736                                         &first->tx_list);
 737                 }
 738                 prev = desc;
 739         }
 740
 741         if (flags & DMA_PREP_INTERRUPT)
 742                 /* Trigger interrupt after last block */
 743                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 744
 745         prev->lli.llp = 0;
 746         first->txd.flags = flags;
 747         first->total_len = len;
 748
 749         return &first->txd;
 750
 751 err_desc_get:
 752         dwc_desc_put(dwc, first);
 753         return NULL;
 754 }
 755
 756 static struct dma_async_tx_descriptor *
 757 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 758                 unsigned int sg_len, enum dma_transfer_direction direction,
 759                 unsigned long flags, void *context)
 760 {
 761         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 762         struct dw_dma           *dw = to_dw_dma(chan->device);
 763         struct dma_slave_config *sconfig = &dwc->dma_sconfig;
 764         struct dw_desc          *prev;
 765         struct dw_desc          *first;
 766         u32                     ctllo;
 767         dma_addr_t              reg;
 768         unsigned int            reg_width;
 769         unsigned int            mem_width;
 770         unsigned int            data_width;
 771         unsigned int            i;
 772         struct scatterlist      *sg;
 773         size_t                  total_len = 0;
 774
 775         dev_vdbg(chan2dev(chan), "%s\n", __func__);
 776
 777         if (unlikely(!is_slave_direction(direction) || !sg_len))
 778                 return NULL;
 779
 780         dwc->direction = direction;
 781
 782         prev = first = NULL;
 783
 784         switch (direction) {
 785         case DMA_MEM_TO_DEV:
 786                 reg_width = __fls(sconfig->dst_addr_width);
 787                 reg = sconfig->dst_addr;
 788                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 789                                 | DWC_CTLL_DST_WIDTH(reg_width)
 790                                 | DWC_CTLL_DST_FIX
 791                                 | DWC_CTLL_SRC_INC);
 792
 793                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
 794                         DWC_CTLL_FC(DW_DMA_FC_D_M2P);
 795
 796                 data_width = dw->data_width[dwc->src_master];
 797
 798                 for_each_sg(sgl, sg, sg_len, i) {
 799                         struct dw_desc  *desc;
 800                         u32             len, dlen, mem;
 801
 802                         mem = sg_dma_address(sg);
 803                         len = sg_dma_len(sg);
 804
 805                         mem_width = min_t(unsigned int,
 806                                           data_width, dwc_fast_fls(mem | len));
 807
 808 slave_sg_todev_fill_desc:
 809                         desc = dwc_desc_get(dwc);
 810                         if (!desc) {
 811                                 dev_err(chan2dev(chan),
 812                                         "not enough descriptors available\n");
 813                                 goto err_desc_get;
 814                         }
 815
 816                         desc->lli.sar = mem;
 817                         desc->lli.dar = reg;
 818                         desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
 819                         if ((len >> mem_width) > dwc->block_size) {
 820                                 dlen = dwc->block_size << mem_width;
 821                                 mem += dlen;
 822                                 len -= dlen;
 823                         } else {
 824                                 dlen = len;
 825                                 len = 0;
 826                         }
 827
 828                         desc->lli.ctlhi = dlen >> mem_width;
 829                         desc->len = dlen;
 830
 831                         if (!first) {
 832                                 first = desc;
 833                         } else {
 834                                 prev->lli.llp = desc->txd.phys;
 835                                 list_add_tail(&desc->desc_node,
 836                                                 &first->tx_list);
 837                         }
 838                         prev = desc;
 839                         total_len += dlen;
 840
 841                         if (len)
 842                                 goto slave_sg_todev_fill_desc;
 843                 }
 844                 break;
 845         case DMA_DEV_TO_MEM:
 846                 reg_width = __fls(sconfig->src_addr_width);
 847                 reg = sconfig->src_addr;
 848                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 849                                 | DWC_CTLL_SRC_WIDTH(reg_width)
 850                                 | DWC_CTLL_DST_INC
 851                                 | DWC_CTLL_SRC_FIX);
 852
 853                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
 854                         DWC_CTLL_FC(DW_DMA_FC_D_P2M);
 855
 856                 data_width = dw->data_width[dwc->dst_master];
 857
 858                 for_each_sg(sgl, sg, sg_len, i) {
 859                         struct dw_desc  *desc;
 860                         u32             len, dlen, mem;
 861
 862                         mem = sg_dma_address(sg);
 863                         len = sg_dma_len(sg);
 864
 865                         mem_width = min_t(unsigned int,
 866                                           data_width, dwc_fast_fls(mem | len));
 867
 868 slave_sg_fromdev_fill_desc:
 869                         desc = dwc_desc_get(dwc);
 870                         if (!desc) {
 871                                 dev_err(chan2dev(chan),
 872                                                 "not enough descriptors available\n");
 873                                 goto err_desc_get;
 874                         }
 875
 876                         desc->lli.sar = reg;
 877                         desc->lli.dar = mem;
 878                         desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
 879                         if ((len >> reg_width) > dwc->block_size) {
 880                                 dlen = dwc->block_size << reg_width;
 881                                 mem += dlen;
 882                                 len -= dlen;
 883                         } else {
 884                                 dlen = len;
 885                                 len = 0;
 886                         }
 887                         desc->lli.ctlhi = dlen >> reg_width;
 888                         desc->len = dlen;
 889
 890                         if (!first) {
 891                                 first = desc;
 892                         } else {
 893                                 prev->lli.llp = desc->txd.phys;
 894                                 list_add_tail(&desc->desc_node,
 895                                                 &first->tx_list);
 896                         }
 897                         prev = desc;
 898                         total_len += dlen;
 899
 900                         if (len)
 901                                 goto slave_sg_fromdev_fill_desc;
 902                 }
 903                 break;
 904         default:
 905                 return NULL;
 906         }
 907
 908         if (flags & DMA_PREP_INTERRUPT)
 909                 /* Trigger interrupt after last block */
 910                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 911
 912         prev->lli.llp = 0;
 913         first->total_len = total_len;
 914
 915         return &first->txd;
 916
 917 err_desc_get:
 918         dwc_desc_put(dwc, first);
 919         return NULL;
 920 }
 921
 922 /*
 923  * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
 924  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
 925  *
 926  * NOTE: burst size 2 is not supported by controller.
 927  *
 928  * This can be done by finding least significant bit set: n & (n - 1)
 929  */
 930 static inline void convert_burst(u32 *maxburst)
 931 {
 932         if (*maxburst > 1)
 933                 *maxburst = fls(*maxburst) - 2;
 934         else
 935                 *maxburst = 0;
 936 }
 937
 938 static int
 939 set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
 940 {
 941         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 942
 943         /* Check if chan will be configured for slave transfers */
 944         if (!is_slave_direction(sconfig->direction))
 945                 return -EINVAL;
 946
 947         memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
 948         dwc->direction = sconfig->direction;
 949
 950         convert_burst(&dwc->dma_sconfig.src_maxburst);
 951         convert_burst(&dwc->dma_sconfig.dst_maxburst);
 952
 953         return 0;
 954 }
 955
 956 static inline void dwc_chan_pause(struct dw_dma_chan *dwc)
 957 {
 958         u32 cfglo = channel_readl(dwc, CFG_LO);
 959         unsigned int count = 20;        /* timeout iterations */
 960
 961         channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
 962         while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
 963                 udelay(2);
 964
 965         dwc->paused = true;
 966 }
 967
 968 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
 969 {
 970         u32 cfglo = channel_readl(dwc, CFG_LO);
 971
 972         channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
 973
 974         dwc->paused = false;
 975 }
 976
 977 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 978                        unsigned long arg)
 979 {
 980         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 981         struct dw_dma           *dw = to_dw_dma(chan->device);
 982         struct dw_desc          *desc, *_desc;
 983         unsigned long           flags;
 984         LIST_HEAD(list);
 985
 986         if (cmd == DMA_PAUSE) {
 987                 spin_lock_irqsave(&dwc->lock, flags);
 988
 989                 dwc_chan_pause(dwc);
 990
 991                 spin_unlock_irqrestore(&dwc->lock, flags);
 992         } else if (cmd == DMA_RESUME) {
 993                 if (!dwc->paused)
 994                         return 0;
 995
 996                 spin_lock_irqsave(&dwc->lock, flags);
 997
 998                 dwc_chan_resume(dwc);
 999
1000                 spin_unlock_irqrestore(&dwc->lock, flags);
1001         } else if (cmd == DMA_TERMINATE_ALL) {
1002                 spin_lock_irqsave(&dwc->lock, flags);
1003
1004                 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1005
1006                 dwc_chan_disable(dw, dwc);
1007
1008                 dwc_chan_resume(dwc);
1009
1010                 /* active_list entries will end up before queued entries */
1011                 list_splice_init(&dwc->queue, &list);
1012                 list_splice_init(&dwc->active_list, &list);
1013
1014                 spin_unlock_irqrestore(&dwc->lock, flags);
1015
1016                 /* Flush all pending and queued descriptors */
1017                 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1018                         dwc_descriptor_complete(dwc, desc, false);
1019         } else if (cmd == DMA_SLAVE_CONFIG) {
1020                 return set_runtime_config(chan, (struct dma_slave_config *)arg);
1021         } else {
1022                 return -ENXIO;
1023         }
1024
1025         return 0;
1026 }
1027
1028 static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
1029 {
1030         unsigned long flags;
1031         u32 residue;
1032
1033         spin_lock_irqsave(&dwc->lock, flags);
1034
1035         residue = dwc->residue;
1036         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1037                 residue -= dwc_get_sent(dwc);
1038
1039         spin_unlock_irqrestore(&dwc->lock, flags);
1040         return residue;
1041 }
1042
1043 static enum dma_status
1044 dwc_tx_status(struct dma_chan *chan,
1045               dma_cookie_t cookie,
1046               struct dma_tx_state *txstate)
1047 {
1048         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1049         enum dma_status         ret;
1050
1051         ret = dma_cookie_status(chan, cookie, txstate);
1052         if (ret == DMA_COMPLETE)
1053                 return ret;
1054
1055         dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1056
1057         ret = dma_cookie_status(chan, cookie, txstate);
1058         if (ret != DMA_COMPLETE)
1059                 dma_set_residue(txstate, dwc_get_residue(dwc));
1060
1061         if (dwc->paused && ret == DMA_IN_PROGRESS)
1062                 return DMA_PAUSED;
1063
1064         return ret;
1065 }
1066
1067 static void dwc_issue_pending(struct dma_chan *chan)
1068 {
1069         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1070         unsigned long           flags;
1071
1072         spin_lock_irqsave(&dwc->lock, flags);
1073         if (list_empty(&dwc->active_list))
1074                 dwc_dostart_first_queued(dwc);
1075         spin_unlock_irqrestore(&dwc->lock, flags);
1076 }
1077
1078 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1079 {
1080         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1081         struct dw_dma           *dw = to_dw_dma(chan->device);
1082         struct dw_desc          *desc;
1083         int                     i;
1084         unsigned long           flags;
1085
1086         dev_vdbg(chan2dev(chan), "%s\n", __func__);
1087
1088         /* ASSERT:  channel is idle */
1089         if (dma_readl(dw, CH_EN) & dwc->mask) {
1090                 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1091                 return -EIO;
1092         }
1093
1094         dma_cookie_init(chan);
1095
1096         /*
1097          * NOTE: some controllers may have additional features that we
1098          * need to initialize here, like "scatter-gather" (which
1099          * doesn't mean what you think it means), and status writeback.
1100          */
1101
1102         spin_lock_irqsave(&dwc->lock, flags);
1103         i = dwc->descs_allocated;
1104         while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1105                 dma_addr_t phys;
1106
1107                 spin_unlock_irqrestore(&dwc->lock, flags);
1108
1109                 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1110                 if (!desc)
1111                         goto err_desc_alloc;
1112
1113                 memset(desc, 0, sizeof(struct dw_desc));
1114
1115                 INIT_LIST_HEAD(&desc->tx_list);
1116                 dma_async_tx_descriptor_init(&desc->txd, chan);
1117                 desc->txd.tx_submit = dwc_tx_submit;
1118                 desc->txd.flags = DMA_CTRL_ACK;
1119                 desc->txd.phys = phys;
1120
1121                 dwc_desc_put(dwc, desc);
1122
1123                 spin_lock_irqsave(&dwc->lock, flags);
1124                 i = ++dwc->descs_allocated;
1125         }
1126
1127         spin_unlock_irqrestore(&dwc->lock, flags);
1128
1129         dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1130
1131         return i;
1132
1133 err_desc_alloc:
1134         dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1135
1136         return i;
1137 }
1138
1139 static void dwc_free_chan_resources(struct dma_chan *chan)
1140 {
1141         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1142         struct dw_dma           *dw = to_dw_dma(chan->device);
1143         struct dw_desc          *desc, *_desc;
1144         unsigned long           flags;
1145         LIST_HEAD(list);
1146
1147         dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1148                         dwc->descs_allocated);
1149
1150         /* ASSERT:  channel is idle */
1151         BUG_ON(!list_empty(&dwc->active_list));
1152         BUG_ON(!list_empty(&dwc->queue));
1153         BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1154
1155         spin_lock_irqsave(&dwc->lock, flags);
1156         list_splice_init(&dwc->free_list, &list);
1157         dwc->descs_allocated = 0;
1158         dwc->initialized = false;
1159
1160         /* Disable interrupts */
1161         channel_clear_bit(dw, MASK.XFER, dwc->mask);
1162         channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1163
1164         spin_unlock_irqrestore(&dwc->lock, flags);
1165
1166         list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1167                 dev_vdbg(chan2dev(chan), "  freeing descriptor %p\n", desc);
1168                 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1169         }
1170
1171         dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1172 }
1173
1174 /* --------------------- Cyclic DMA API extensions -------------------- */
1175
1176 /**
1177  * dw_dma_cyclic_start - start the cyclic DMA transfer
1178  * @chan: the DMA channel to start
1179  *
1180  * Must be called with soft interrupts disabled. Returns zero on success or
1181  * -errno on failure.
1182  */
1183 int dw_dma_cyclic_start(struct dma_chan *chan)
1184 {
1185         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1186         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1187         unsigned long           flags;
1188
1189         if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1190                 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1191                 return -ENODEV;
1192         }
1193
1194         spin_lock_irqsave(&dwc->lock, flags);
1195
1196         /* Assert channel is idle */
1197         if (dma_readl(dw, CH_EN) & dwc->mask) {
1198                 dev_err(chan2dev(&dwc->chan),
1199                         "BUG: Attempted to start non-idle channel\n");
1200                 dwc_dump_chan_regs(dwc);
1201                 spin_unlock_irqrestore(&dwc->lock, flags);
1202                 return -EBUSY;
1203         }
1204
1205         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1206         dma_writel(dw, CLEAR.XFER, dwc->mask);
1207
1208         /* Setup DMAC channel registers */
1209         channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1210         channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1211         channel_writel(dwc, CTL_HI, 0);
1212
1213         channel_set_bit(dw, CH_EN, dwc->mask);
1214
1215         spin_unlock_irqrestore(&dwc->lock, flags);
1216
1217         return 0;
1218 }
1219 EXPORT_SYMBOL(dw_dma_cyclic_start);
1220
1221 /**
1222  * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1223  * @chan: the DMA channel to stop
1224  *
1225  * Must be called with soft interrupts disabled.
1226  */
1227 void dw_dma_cyclic_stop(struct dma_chan *chan)
1228 {
1229         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1230         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1231         unsigned long           flags;
1232
1233         spin_lock_irqsave(&dwc->lock, flags);
1234
1235         dwc_chan_disable(dw, dwc);
1236
1237         spin_unlock_irqrestore(&dwc->lock, flags);
1238 }
1239 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1240
1241 /**
1242  * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1243  * @chan: the DMA channel to prepare
1244  * @buf_addr: physical DMA address where the buffer starts
1245  * @buf_len: total number of bytes for the entire buffer
1246  * @period_len: number of bytes for each period
1247  * @direction: transfer direction, to or from device
1248  *
1249  * Must be called before trying to start the transfer. Returns a valid struct
1250  * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1251  */
1252 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1253                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1254                 enum dma_transfer_direction direction)
1255 {
1256         struct dw_dma_chan              *dwc = to_dw_dma_chan(chan);
1257         struct dma_slave_config         *sconfig = &dwc->dma_sconfig;
1258         struct dw_cyclic_desc           *cdesc;
1259         struct dw_cyclic_desc           *retval = NULL;
1260         struct dw_desc                  *desc;
1261         struct dw_desc                  *last = NULL;
1262         unsigned long                   was_cyclic;
1263         unsigned int                    reg_width;
1264         unsigned int                    periods;
1265         unsigned int                    i;
1266         unsigned long                   flags;
1267
1268         spin_lock_irqsave(&dwc->lock, flags);
1269         if (dwc->nollp) {
1270                 spin_unlock_irqrestore(&dwc->lock, flags);
1271                 dev_dbg(chan2dev(&dwc->chan),
1272                                 "channel doesn't support LLP transfers\n");
1273                 return ERR_PTR(-EINVAL);
1274         }
1275
1276         if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1277                 spin_unlock_irqrestore(&dwc->lock, flags);
1278                 dev_dbg(chan2dev(&dwc->chan),
1279                                 "queue and/or active list are not empty\n");
1280                 return ERR_PTR(-EBUSY);
1281         }
1282
1283         was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1284         spin_unlock_irqrestore(&dwc->lock, flags);
1285         if (was_cyclic) {
1286                 dev_dbg(chan2dev(&dwc->chan),
1287                                 "channel already prepared for cyclic DMA\n");
1288                 return ERR_PTR(-EBUSY);
1289         }
1290
1291         retval = ERR_PTR(-EINVAL);
1292
1293         if (unlikely(!is_slave_direction(direction)))
1294                 goto out_err;
1295
1296         dwc->direction = direction;
1297
1298         if (direction == DMA_MEM_TO_DEV)
1299                 reg_width = __ffs(sconfig->dst_addr_width);
1300         else
1301                 reg_width = __ffs(sconfig->src_addr_width);
1302
1303         periods = buf_len / period_len;
1304
1305         /* Check for too big/unaligned periods and unaligned DMA buffer. */
1306         if (period_len > (dwc->block_size << reg_width))
1307                 goto out_err;
1308         if (unlikely(period_len & ((1 << reg_width) - 1)))
1309                 goto out_err;
1310         if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1311                 goto out_err;
1312
1313         retval = ERR_PTR(-ENOMEM);
1314
1315         if (periods > NR_DESCS_PER_CHANNEL)
1316                 goto out_err;
1317
1318         cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1319         if (!cdesc)
1320                 goto out_err;
1321
1322         cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1323         if (!cdesc->desc)
1324                 goto out_err_alloc;
1325
1326         for (i = 0; i < periods; i++) {
1327                 desc = dwc_desc_get(dwc);
1328                 if (!desc)
1329                         goto out_err_desc_get;
1330
1331                 switch (direction) {
1332                 case DMA_MEM_TO_DEV:
1333                         desc->lli.dar = sconfig->dst_addr;
1334                         desc->lli.sar = buf_addr + (period_len * i);
1335                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1336                                         | DWC_CTLL_DST_WIDTH(reg_width)
1337                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1338                                         | DWC_CTLL_DST_FIX
1339                                         | DWC_CTLL_SRC_INC
1340                                         | DWC_CTLL_INT_EN);
1341
1342                         desc->lli.ctllo |= sconfig->device_fc ?
1343                                 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1344                                 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1345
1346                         break;
1347                 case DMA_DEV_TO_MEM:
1348                         desc->lli.dar = buf_addr + (period_len * i);
1349                         desc->lli.sar = sconfig->src_addr;
1350                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1351                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1352                                         | DWC_CTLL_DST_WIDTH(reg_width)
1353                                         | DWC_CTLL_DST_INC
1354                                         | DWC_CTLL_SRC_FIX
1355                                         | DWC_CTLL_INT_EN);
1356
1357                         desc->lli.ctllo |= sconfig->device_fc ?
1358                                 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1359                                 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1360
1361                         break;
1362                 default:
1363                         break;
1364                 }
1365
1366                 desc->lli.ctlhi = (period_len >> reg_width);
1367                 cdesc->desc[i] = desc;
1368
1369                 if (last)
1370                         last->lli.llp = desc->txd.phys;
1371
1372                 last = desc;
1373         }
1374
1375         /* Let's make a cyclic list */
1376         last->lli.llp = cdesc->desc[0]->txd.phys;
1377
1378         dev_dbg(chan2dev(&dwc->chan),
1379                         "cyclic prepared buf %pad len %zu period %zu periods %d\n",
1380                         &buf_addr, buf_len, period_len, periods);
1381
1382         cdesc->periods = periods;
1383         dwc->cdesc = cdesc;
1384
1385         return cdesc;
1386
1387 out_err_desc_get:
1388         while (i--)
1389                 dwc_desc_put(dwc, cdesc->desc[i]);
1390 out_err_alloc:
1391         kfree(cdesc);
1392 out_err:
1393         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1394         return (struct dw_cyclic_desc *)retval;
1395 }
1396 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1397
1398 /**
1399  * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1400  * @chan: the DMA channel to free
1401  */
1402 void dw_dma_cyclic_free(struct dma_chan *chan)
1403 {
1404         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1405         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1406         struct dw_cyclic_desc   *cdesc = dwc->cdesc;
1407         int                     i;
1408         unsigned long           flags;
1409
1410         dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1411
1412         if (!cdesc)
1413                 return;
1414
1415         spin_lock_irqsave(&dwc->lock, flags);
1416
1417         dwc_chan_disable(dw, dwc);
1418
1419         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1420         dma_writel(dw, CLEAR.XFER, dwc->mask);
1421
1422         spin_unlock_irqrestore(&dwc->lock, flags);
1423
1424         for (i = 0; i < cdesc->periods; i++)
1425                 dwc_desc_put(dwc, cdesc->desc[i]);
1426
1427         kfree(cdesc->desc);
1428         kfree(cdesc);
1429
1430         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1431 }
1432 EXPORT_SYMBOL(dw_dma_cyclic_free);
1433
1434 /*----------------------------------------------------------------------*/
1435
1436 static void dw_dma_off(struct dw_dma *dw)
1437 {
1438         int i;
1439
1440         dma_writel(dw, CFG, 0);
1441
1442         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1443         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1444         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1445         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1446
1447         while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1448                 cpu_relax();
1449
1450         for (i = 0; i < dw->dma.chancnt; i++)
1451                 dw->chan[i].initialized = false;
1452 }
1453
1454 int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
1455 {
1456         struct dw_dma           *dw;
1457         bool                    autocfg;
1458         unsigned int            dw_params;
1459         unsigned int            nr_channels;
1460         unsigned int            max_blk_size = 0;
1461         int                     err;
1462         int                     i;
1463
1464         dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
1465         if (!dw)
1466                 return -ENOMEM;
1467
1468         dw->regs = chip->regs;
1469         chip->dw = dw;
1470
1471         dw->clk = devm_clk_get(chip->dev, "hclk");
1472         if (IS_ERR(dw->clk))
1473                 return PTR_ERR(dw->clk);
1474         err = clk_prepare_enable(dw->clk);
1475         if (err)
1476                 return err;
1477
1478         dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
1479         autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1480
1481         dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1482
1483         if (!pdata && autocfg) {
1484                 pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
1485                 if (!pdata) {
1486                         err = -ENOMEM;
1487                         goto err_pdata;
1488                 }
1489
1490                 /* Fill platform data with the default values */
1491                 pdata->is_private = true;
1492                 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1493                 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1494         } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
1495                 err = -EINVAL;
1496                 goto err_pdata;
1497         }
1498
1499         if (autocfg)
1500                 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
1501         else
1502                 nr_channels = pdata->nr_channels;
1503
1504         dw->chan = devm_kcalloc(chip->dev, nr_channels, sizeof(*dw->chan),
1505                                 GFP_KERNEL);
1506         if (!dw->chan) {
1507                 err = -ENOMEM;
1508                 goto err_pdata;
1509         }
1510
1511         /* Get hardware configuration parameters */
1512         if (autocfg) {
1513                 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1514
1515                 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1516                 for (i = 0; i < dw->nr_masters; i++) {
1517                         dw->data_width[i] =
1518                                 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1519                 }
1520         } else {
1521                 dw->nr_masters = pdata->nr_masters;
1522                 memcpy(dw->data_width, pdata->data_width, 4);
1523         }
1524
1525         /* Calculate all channel mask before DMA setup */
1526         dw->all_chan_mask = (1 << nr_channels) - 1;
1527
1528         /* Force dma off, just in case */
1529         dw_dma_off(dw);
1530
1531         /* Disable BLOCK interrupts as well */
1532         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1533
1534         /* Create a pool of consistent memory blocks for hardware descriptors */
1535         dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
1536                                          sizeof(struct dw_desc), 4, 0);
1537         if (!dw->desc_pool) {
1538                 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1539                 err = -ENOMEM;
1540                 goto err_pdata;
1541         }
1542
1543         tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1544
1545         err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
1546                           "dw_dmac", dw);
1547         if (err)
1548                 goto err_pdata;
1549
1550         INIT_LIST_HEAD(&dw->dma.channels);
1551         for (i = 0; i < nr_channels; i++) {
1552                 struct dw_dma_chan      *dwc = &dw->chan[i];
1553                 int                     r = nr_channels - i - 1;
1554
1555                 dwc->chan.device = &dw->dma;
1556                 dma_cookie_init(&dwc->chan);
1557                 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1558                         list_add_tail(&dwc->chan.device_node,
1559                                         &dw->dma.channels);
1560                 else
1561                         list_add(&dwc->chan.device_node, &dw->dma.channels);
1562
1563                 /* 7 is highest priority & 0 is lowest. */
1564                 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1565                         dwc->priority = r;
1566                 else
1567                         dwc->priority = i;
1568
1569                 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1570                 spin_lock_init(&dwc->lock);
1571                 dwc->mask = 1 << i;
1572
1573                 INIT_LIST_HEAD(&dwc->active_list);
1574                 INIT_LIST_HEAD(&dwc->queue);
1575                 INIT_LIST_HEAD(&dwc->free_list);
1576
1577                 channel_clear_bit(dw, CH_EN, dwc->mask);
1578
1579                 dwc->direction = DMA_TRANS_NONE;
1580
1581                 /* Hardware configuration */
1582                 if (autocfg) {
1583                         unsigned int dwc_params;
1584                         void __iomem *addr = chip->regs + r * sizeof(u32);
1585
1586                         dwc_params = dma_read_byaddr(addr, DWC_PARAMS);
1587
1588                         dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1589                                            dwc_params);
1590
1591                         /*
1592                          * Decode maximum block size for given channel. The
1593                          * stored 4 bit value represents blocks from 0x00 for 3
1594                          * up to 0x0a for 4095.
1595                          */
1596                         dwc->block_size =
1597                                 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1598                         dwc->nollp =
1599                                 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1600                 } else {
1601                         dwc->block_size = pdata->block_size;
1602
1603                         /* Check if channel supports multi block transfer */
1604                         channel_writel(dwc, LLP, 0xfffffffc);
1605                         dwc->nollp =
1606                                 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1607                         channel_writel(dwc, LLP, 0);
1608                 }
1609         }
1610
1611         /* Clear all interrupts on all channels. */
1612         dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1613         dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1614         dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1615         dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1616         dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1617
1618         dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1619         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1620         if (pdata->is_private)
1621                 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1622         dw->dma.dev = chip->dev;
1623         dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1624         dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1625
1626         dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1627
1628         dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1629         dw->dma.device_control = dwc_control;
1630
1631         dw->dma.device_tx_status = dwc_tx_status;
1632         dw->dma.device_issue_pending = dwc_issue_pending;
1633
1634         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1635
1636         err = dma_async_device_register(&dw->dma);
1637         if (err)
1638                 goto err_dma_register;
1639
1640         dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1641                  nr_channels);
1642
1643         return 0;
1644
1645 err_dma_register:
1646         free_irq(chip->irq, dw);
1647 err_pdata:
1648         clk_disable_unprepare(dw->clk);
1649         return err;
1650 }
1651 EXPORT_SYMBOL_GPL(dw_dma_probe);
1652
1653 int dw_dma_remove(struct dw_dma_chip *chip)
1654 {
1655         struct dw_dma           *dw = chip->dw;
1656         struct dw_dma_chan      *dwc, *_dwc;
1657
1658         dw_dma_off(dw);
1659         dma_async_device_unregister(&dw->dma);
1660
1661         free_irq(chip->irq, dw);
1662         tasklet_kill(&dw->tasklet);
1663
1664         list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1665                         chan.device_node) {
1666                 list_del(&dwc->chan.device_node);
1667                 channel_clear_bit(dw, CH_EN, dwc->mask);
1668         }
1669
1670         clk_disable_unprepare(dw->clk);
1671
1672         return 0;
1673 }
1674 EXPORT_SYMBOL_GPL(dw_dma_remove);
1675
1676 void dw_dma_shutdown(struct dw_dma_chip *chip)
1677 {
1678         struct dw_dma *dw = chip->dw;
1679
1680         dw_dma_off(dw);
1681         clk_disable_unprepare(dw->clk);
1682 }
1683 EXPORT_SYMBOL_GPL(dw_dma_shutdown);
1684
1685 #ifdef CONFIG_PM_SLEEP
1686
1687 int dw_dma_suspend(struct dw_dma_chip *chip)
1688 {
1689         struct dw_dma *dw = chip->dw;
1690
1691         dw_dma_off(dw);
1692         clk_disable_unprepare(dw->clk);
1693
1694         return 0;
1695 }
1696 EXPORT_SYMBOL_GPL(dw_dma_suspend);
1697
1698 int dw_dma_resume(struct dw_dma_chip *chip)
1699 {
1700         struct dw_dma *dw = chip->dw;
1701
1702         clk_prepare_enable(dw->clk);
1703         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1704
1705         return 0;
1706 }
1707 EXPORT_SYMBOL_GPL(dw_dma_resume);
1708
1709 #endif /* CONFIG_PM_SLEEP */
1710
1711 MODULE_LICENSE("GPL v2");
1712 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1713 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1714 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");