2 * Core driver for the Synopsys DesignWare DMA Controller
4 * Copyright (C) 2007-2008 Atmel Corporation
5 * Copyright (C) 2010-2011 ST Microelectronics
6 * Copyright (C) 2013 Intel Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/bitops.h>
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/dmaengine.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/dmapool.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/slab.h>
27 #include "../dmaengine.h"
31 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
32 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
33 * of which use ARM any more). See the "Databook" from Synopsys for
34 * information beyond what licensees probably provide.
36 * The driver has been tested with the Atmel AT32AP7000, which does not
37 * support descriptor writeback.
40 static inline bool is_request_line_unset(struct dw_dma_chan *dwc)
42 return dwc->request_line == (typeof(dwc->request_line))~0;
45 static inline void dwc_set_masters(struct dw_dma_chan *dwc)
47 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
48 struct dw_dma_slave *dws = dwc->chan.private;
49 unsigned char mmax = dw->nr_masters - 1;
51 if (!is_request_line_unset(dwc))
54 dwc->src_master = min_t(unsigned char, mmax, dwc_get_sms(dws));
55 dwc->dst_master = min_t(unsigned char, mmax, dwc_get_dms(dws));
58 #define DWC_DEFAULT_CTLLO(_chan) ({ \
59 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \
60 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
61 bool _is_slave = is_slave_direction(_dwc->direction); \
62 u8 _smsize = _is_slave ? _sconfig->src_maxburst : \
64 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \
67 (DWC_CTLL_DST_MSIZE(_dmsize) \
68 | DWC_CTLL_SRC_MSIZE(_smsize) \
71 | DWC_CTLL_DMS(_dwc->dst_master) \
72 | DWC_CTLL_SMS(_dwc->src_master)); \
76 * Number of descriptors to allocate for each channel. This should be
77 * made configurable somehow; preferably, the clients (at least the
78 * ones using slave transfers) should be able to give us a hint.
80 #define NR_DESCS_PER_CHANNEL 64
82 /*----------------------------------------------------------------------*/
84 static struct device *chan2dev(struct dma_chan *chan)
86 return &chan->dev->device;
89 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
91 return to_dw_desc(dwc->active_list.next);
94 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
96 struct dw_desc *desc, *_desc;
97 struct dw_desc *ret = NULL;
101 spin_lock_irqsave(&dwc->lock, flags);
102 list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
104 if (async_tx_test_ack(&desc->txd)) {
105 list_del(&desc->desc_node);
109 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
111 spin_unlock_irqrestore(&dwc->lock, flags);
113 dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
119 * Move a descriptor, including any children, to the free list.
120 * `desc' must not be on any lists.
122 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
127 struct dw_desc *child;
129 spin_lock_irqsave(&dwc->lock, flags);
130 list_for_each_entry(child, &desc->tx_list, desc_node)
131 dev_vdbg(chan2dev(&dwc->chan),
132 "moving child desc %p to freelist\n",
134 list_splice_init(&desc->tx_list, &dwc->free_list);
135 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
136 list_add(&desc->desc_node, &dwc->free_list);
137 spin_unlock_irqrestore(&dwc->lock, flags);
141 static void dwc_initialize(struct dw_dma_chan *dwc)
143 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
144 struct dw_dma_slave *dws = dwc->chan.private;
145 u32 cfghi = DWC_CFGH_FIFO_MODE;
146 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
148 if (dwc->initialized == true)
153 * We need controller-specific data to set up slave
156 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
159 cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
161 if (dwc->direction == DMA_MEM_TO_DEV)
162 cfghi = DWC_CFGH_DST_PER(dwc->request_line);
163 else if (dwc->direction == DMA_DEV_TO_MEM)
164 cfghi = DWC_CFGH_SRC_PER(dwc->request_line);
167 channel_writel(dwc, CFG_LO, cfglo);
168 channel_writel(dwc, CFG_HI, cfghi);
170 /* Enable interrupts */
171 channel_set_bit(dw, MASK.XFER, dwc->mask);
172 channel_set_bit(dw, MASK.ERROR, dwc->mask);
174 dwc->initialized = true;
177 /*----------------------------------------------------------------------*/
179 static inline unsigned int dwc_fast_fls(unsigned long long v)
182 * We can be a lot more clever here, but this should take care
183 * of the most common optimization.
194 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
196 dev_err(chan2dev(&dwc->chan),
197 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
198 channel_readl(dwc, SAR),
199 channel_readl(dwc, DAR),
200 channel_readl(dwc, LLP),
201 channel_readl(dwc, CTL_HI),
202 channel_readl(dwc, CTL_LO));
205 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
207 channel_clear_bit(dw, CH_EN, dwc->mask);
208 while (dma_readl(dw, CH_EN) & dwc->mask)
212 /*----------------------------------------------------------------------*/
214 /* Perform single block transfer */
215 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
216 struct dw_desc *desc)
218 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
222 * Software emulation of LLP mode relies on interrupts to continue
223 * multi block transfer.
225 ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
227 channel_writel(dwc, SAR, desc->lli.sar);
228 channel_writel(dwc, DAR, desc->lli.dar);
229 channel_writel(dwc, CTL_LO, ctllo);
230 channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
231 channel_set_bit(dw, CH_EN, dwc->mask);
233 /* Move pointer to next descriptor */
234 dwc->tx_node_active = dwc->tx_node_active->next;
237 /* Called with dwc->lock held and bh disabled */
238 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
240 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
241 unsigned long was_soft_llp;
243 /* ASSERT: channel is idle */
244 if (dma_readl(dw, CH_EN) & dwc->mask) {
245 dev_err(chan2dev(&dwc->chan),
246 "BUG: Attempted to start non-idle channel\n");
247 dwc_dump_chan_regs(dwc);
249 /* The tasklet will hopefully advance the queue... */
254 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
257 dev_err(chan2dev(&dwc->chan),
258 "BUG: Attempted to start new LLP transfer inside ongoing one\n");
264 dwc->residue = first->total_len;
265 dwc->tx_node_active = &first->tx_list;
267 /* Submit first block */
268 dwc_do_single_block(dwc, first);
275 channel_writel(dwc, LLP, first->txd.phys);
276 channel_writel(dwc, CTL_LO,
277 DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
278 channel_writel(dwc, CTL_HI, 0);
279 channel_set_bit(dw, CH_EN, dwc->mask);
282 static void dwc_dostart_first_queued(struct dw_dma_chan *dwc)
284 struct dw_desc *desc;
286 if (list_empty(&dwc->queue))
289 list_move(dwc->queue.next, &dwc->active_list);
290 desc = dwc_first_active(dwc);
291 dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie);
292 dwc_dostart(dwc, desc);
295 /*----------------------------------------------------------------------*/
298 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
299 bool callback_required)
301 dma_async_tx_callback callback = NULL;
303 struct dma_async_tx_descriptor *txd = &desc->txd;
304 struct dw_desc *child;
307 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
309 spin_lock_irqsave(&dwc->lock, flags);
310 dma_cookie_complete(txd);
311 if (callback_required) {
312 callback = txd->callback;
313 param = txd->callback_param;
317 list_for_each_entry(child, &desc->tx_list, desc_node)
318 async_tx_ack(&child->txd);
319 async_tx_ack(&desc->txd);
321 list_splice_init(&desc->tx_list, &dwc->free_list);
322 list_move(&desc->desc_node, &dwc->free_list);
324 dma_descriptor_unmap(txd);
325 spin_unlock_irqrestore(&dwc->lock, flags);
331 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
333 struct dw_desc *desc, *_desc;
337 spin_lock_irqsave(&dwc->lock, flags);
338 if (dma_readl(dw, CH_EN) & dwc->mask) {
339 dev_err(chan2dev(&dwc->chan),
340 "BUG: XFER bit set, but channel not idle!\n");
342 /* Try to continue after resetting the channel... */
343 dwc_chan_disable(dw, dwc);
347 * Submit queued descriptors ASAP, i.e. before we go through
348 * the completed ones.
350 list_splice_init(&dwc->active_list, &list);
351 dwc_dostart_first_queued(dwc);
353 spin_unlock_irqrestore(&dwc->lock, flags);
355 list_for_each_entry_safe(desc, _desc, &list, desc_node)
356 dwc_descriptor_complete(dwc, desc, true);
359 /* Returns how many bytes were already received from source */
360 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
362 u32 ctlhi = channel_readl(dwc, CTL_HI);
363 u32 ctllo = channel_readl(dwc, CTL_LO);
365 return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
368 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
371 struct dw_desc *desc, *_desc;
372 struct dw_desc *child;
376 spin_lock_irqsave(&dwc->lock, flags);
377 llp = channel_readl(dwc, LLP);
378 status_xfer = dma_readl(dw, RAW.XFER);
380 if (status_xfer & dwc->mask) {
381 /* Everything we've submitted is done */
382 dma_writel(dw, CLEAR.XFER, dwc->mask);
384 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
385 struct list_head *head, *active = dwc->tx_node_active;
388 * We are inside first active descriptor.
389 * Otherwise something is really wrong.
391 desc = dwc_first_active(dwc);
393 head = &desc->tx_list;
394 if (active != head) {
395 /* Update desc to reflect last sent one */
396 if (active != head->next)
397 desc = to_dw_desc(active->prev);
399 dwc->residue -= desc->len;
401 child = to_dw_desc(active);
403 /* Submit next block */
404 dwc_do_single_block(dwc, child);
406 spin_unlock_irqrestore(&dwc->lock, flags);
410 /* We are done here */
411 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
416 spin_unlock_irqrestore(&dwc->lock, flags);
418 dwc_complete_all(dw, dwc);
422 if (list_empty(&dwc->active_list)) {
424 spin_unlock_irqrestore(&dwc->lock, flags);
428 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
429 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
430 spin_unlock_irqrestore(&dwc->lock, flags);
434 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp);
436 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
437 /* Initial residue value */
438 dwc->residue = desc->total_len;
440 /* Check first descriptors addr */
441 if (desc->txd.phys == llp) {
442 spin_unlock_irqrestore(&dwc->lock, flags);
446 /* Check first descriptors llp */
447 if (desc->lli.llp == llp) {
448 /* This one is currently in progress */
449 dwc->residue -= dwc_get_sent(dwc);
450 spin_unlock_irqrestore(&dwc->lock, flags);
454 dwc->residue -= desc->len;
455 list_for_each_entry(child, &desc->tx_list, desc_node) {
456 if (child->lli.llp == llp) {
457 /* Currently in progress */
458 dwc->residue -= dwc_get_sent(dwc);
459 spin_unlock_irqrestore(&dwc->lock, flags);
462 dwc->residue -= child->len;
466 * No descriptors so far seem to be in progress, i.e.
467 * this one must be done.
469 spin_unlock_irqrestore(&dwc->lock, flags);
470 dwc_descriptor_complete(dwc, desc, true);
471 spin_lock_irqsave(&dwc->lock, flags);
474 dev_err(chan2dev(&dwc->chan),
475 "BUG: All descriptors done, but channel not idle!\n");
477 /* Try to continue after resetting the channel... */
478 dwc_chan_disable(dw, dwc);
480 dwc_dostart_first_queued(dwc);
481 spin_unlock_irqrestore(&dwc->lock, flags);
484 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
486 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
487 lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
490 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
492 struct dw_desc *bad_desc;
493 struct dw_desc *child;
496 dwc_scan_descriptors(dw, dwc);
498 spin_lock_irqsave(&dwc->lock, flags);
501 * The descriptor currently at the head of the active list is
502 * borked. Since we don't have any way to report errors, we'll
503 * just have to scream loudly and try to carry on.
505 bad_desc = dwc_first_active(dwc);
506 list_del_init(&bad_desc->desc_node);
507 list_move(dwc->queue.next, dwc->active_list.prev);
509 /* Clear the error flag and try to restart the controller */
510 dma_writel(dw, CLEAR.ERROR, dwc->mask);
511 if (!list_empty(&dwc->active_list))
512 dwc_dostart(dwc, dwc_first_active(dwc));
515 * WARN may seem harsh, but since this only happens
516 * when someone submits a bad physical address in a
517 * descriptor, we should consider ourselves lucky that the
518 * controller flagged an error instead of scribbling over
519 * random memory locations.
521 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
522 " cookie: %d\n", bad_desc->txd.cookie);
523 dwc_dump_lli(dwc, &bad_desc->lli);
524 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
525 dwc_dump_lli(dwc, &child->lli);
527 spin_unlock_irqrestore(&dwc->lock, flags);
529 /* Pretend the descriptor completed successfully */
530 dwc_descriptor_complete(dwc, bad_desc, true);
533 /* --------------------- Cyclic DMA API extensions -------------------- */
535 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
537 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
538 return channel_readl(dwc, SAR);
540 EXPORT_SYMBOL(dw_dma_get_src_addr);
542 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
544 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
545 return channel_readl(dwc, DAR);
547 EXPORT_SYMBOL(dw_dma_get_dst_addr);
549 /* Called with dwc->lock held and all DMAC interrupts disabled */
550 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
551 u32 status_err, u32 status_xfer)
556 void (*callback)(void *param);
557 void *callback_param;
559 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
560 channel_readl(dwc, LLP));
562 callback = dwc->cdesc->period_callback;
563 callback_param = dwc->cdesc->period_callback_param;
566 callback(callback_param);
570 * Error and transfer complete are highly unlikely, and will most
571 * likely be due to a configuration error by the user.
573 if (unlikely(status_err & dwc->mask) ||
574 unlikely(status_xfer & dwc->mask)) {
577 dev_err(chan2dev(&dwc->chan),
578 "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n",
579 status_xfer ? "xfer" : "error");
581 spin_lock_irqsave(&dwc->lock, flags);
583 dwc_dump_chan_regs(dwc);
585 dwc_chan_disable(dw, dwc);
587 /* Make sure DMA does not restart by loading a new list */
588 channel_writel(dwc, LLP, 0);
589 channel_writel(dwc, CTL_LO, 0);
590 channel_writel(dwc, CTL_HI, 0);
592 dma_writel(dw, CLEAR.ERROR, dwc->mask);
593 dma_writel(dw, CLEAR.XFER, dwc->mask);
595 for (i = 0; i < dwc->cdesc->periods; i++)
596 dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
598 spin_unlock_irqrestore(&dwc->lock, flags);
602 /* ------------------------------------------------------------------------- */
604 static void dw_dma_tasklet(unsigned long data)
606 struct dw_dma *dw = (struct dw_dma *)data;
607 struct dw_dma_chan *dwc;
612 status_xfer = dma_readl(dw, RAW.XFER);
613 status_err = dma_readl(dw, RAW.ERROR);
615 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
617 for (i = 0; i < dw->dma.chancnt; i++) {
619 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
620 dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
621 else if (status_err & (1 << i))
622 dwc_handle_error(dw, dwc);
623 else if (status_xfer & (1 << i))
624 dwc_scan_descriptors(dw, dwc);
628 * Re-enable interrupts.
630 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
631 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
634 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
636 struct dw_dma *dw = dev_id;
637 u32 status = dma_readl(dw, STATUS_INT);
639 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
641 /* Check if we have any interrupt from the DMAC */
646 * Just disable the interrupts. We'll turn them back on in the
649 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
650 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
652 status = dma_readl(dw, STATUS_INT);
655 "BUG: Unexpected interrupts pending: 0x%x\n",
659 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
660 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
661 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
662 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
665 tasklet_schedule(&dw->tasklet);
670 /*----------------------------------------------------------------------*/
672 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
674 struct dw_desc *desc = txd_to_dw_desc(tx);
675 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
679 spin_lock_irqsave(&dwc->lock, flags);
680 cookie = dma_cookie_assign(tx);
683 * REVISIT: We should attempt to chain as many descriptors as
684 * possible, perhaps even appending to those already submitted
685 * for DMA. But this is hard to do in a race-free manner.
688 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie);
689 list_add_tail(&desc->desc_node, &dwc->queue);
691 spin_unlock_irqrestore(&dwc->lock, flags);
696 static struct dma_async_tx_descriptor *
697 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
698 size_t len, unsigned long flags)
700 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
701 struct dw_dma *dw = to_dw_dma(chan->device);
702 struct dw_desc *desc;
703 struct dw_desc *first;
704 struct dw_desc *prev;
707 unsigned int src_width;
708 unsigned int dst_width;
709 unsigned int data_width;
712 dev_vdbg(chan2dev(chan),
713 "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
714 &dest, &src, len, flags);
716 if (unlikely(!len)) {
717 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
721 dwc->direction = DMA_MEM_TO_MEM;
723 data_width = min_t(unsigned int, dw->data_width[dwc->src_master],
724 dw->data_width[dwc->dst_master]);
726 src_width = dst_width = min_t(unsigned int, data_width,
727 dwc_fast_fls(src | dest | len));
729 ctllo = DWC_DEFAULT_CTLLO(chan)
730 | DWC_CTLL_DST_WIDTH(dst_width)
731 | DWC_CTLL_SRC_WIDTH(src_width)
737 for (offset = 0; offset < len; offset += xfer_count << src_width) {
738 xfer_count = min_t(size_t, (len - offset) >> src_width,
741 desc = dwc_desc_get(dwc);
745 desc->lli.sar = src + offset;
746 desc->lli.dar = dest + offset;
747 desc->lli.ctllo = ctllo;
748 desc->lli.ctlhi = xfer_count;
749 desc->len = xfer_count << src_width;
754 prev->lli.llp = desc->txd.phys;
755 list_add_tail(&desc->desc_node,
761 if (flags & DMA_PREP_INTERRUPT)
762 /* Trigger interrupt after last block */
763 prev->lli.ctllo |= DWC_CTLL_INT_EN;
766 first->txd.flags = flags;
767 first->total_len = len;
772 dwc_desc_put(dwc, first);
776 static struct dma_async_tx_descriptor *
777 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
778 unsigned int sg_len, enum dma_transfer_direction direction,
779 unsigned long flags, void *context)
781 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
782 struct dw_dma *dw = to_dw_dma(chan->device);
783 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
784 struct dw_desc *prev;
785 struct dw_desc *first;
788 unsigned int reg_width;
789 unsigned int mem_width;
790 unsigned int data_width;
792 struct scatterlist *sg;
793 size_t total_len = 0;
795 dev_vdbg(chan2dev(chan), "%s\n", __func__);
797 if (unlikely(!is_slave_direction(direction) || !sg_len))
800 dwc->direction = direction;
806 reg_width = __fls(sconfig->dst_addr_width);
807 reg = sconfig->dst_addr;
808 ctllo = (DWC_DEFAULT_CTLLO(chan)
809 | DWC_CTLL_DST_WIDTH(reg_width)
813 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
814 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
816 data_width = dw->data_width[dwc->src_master];
818 for_each_sg(sgl, sg, sg_len, i) {
819 struct dw_desc *desc;
822 mem = sg_dma_address(sg);
823 len = sg_dma_len(sg);
825 mem_width = min_t(unsigned int,
826 data_width, dwc_fast_fls(mem | len));
828 slave_sg_todev_fill_desc:
829 desc = dwc_desc_get(dwc);
831 dev_err(chan2dev(chan),
832 "not enough descriptors available\n");
838 desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
839 if ((len >> mem_width) > dwc->block_size) {
840 dlen = dwc->block_size << mem_width;
848 desc->lli.ctlhi = dlen >> mem_width;
854 prev->lli.llp = desc->txd.phys;
855 list_add_tail(&desc->desc_node,
862 goto slave_sg_todev_fill_desc;
866 reg_width = __fls(sconfig->src_addr_width);
867 reg = sconfig->src_addr;
868 ctllo = (DWC_DEFAULT_CTLLO(chan)
869 | DWC_CTLL_SRC_WIDTH(reg_width)
873 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
874 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
876 data_width = dw->data_width[dwc->dst_master];
878 for_each_sg(sgl, sg, sg_len, i) {
879 struct dw_desc *desc;
882 mem = sg_dma_address(sg);
883 len = sg_dma_len(sg);
885 mem_width = min_t(unsigned int,
886 data_width, dwc_fast_fls(mem | len));
888 slave_sg_fromdev_fill_desc:
889 desc = dwc_desc_get(dwc);
891 dev_err(chan2dev(chan),
892 "not enough descriptors available\n");
898 desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
899 if ((len >> reg_width) > dwc->block_size) {
900 dlen = dwc->block_size << reg_width;
907 desc->lli.ctlhi = dlen >> reg_width;
913 prev->lli.llp = desc->txd.phys;
914 list_add_tail(&desc->desc_node,
921 goto slave_sg_fromdev_fill_desc;
928 if (flags & DMA_PREP_INTERRUPT)
929 /* Trigger interrupt after last block */
930 prev->lli.ctllo |= DWC_CTLL_INT_EN;
933 first->total_len = total_len;
938 dwc_desc_put(dwc, first);
943 * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
944 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
946 * NOTE: burst size 2 is not supported by controller.
948 * This can be done by finding least significant bit set: n & (n - 1)
950 static inline void convert_burst(u32 *maxburst)
953 *maxburst = fls(*maxburst) - 2;
959 set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
961 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
963 /* Check if chan will be configured for slave transfers */
964 if (!is_slave_direction(sconfig->direction))
967 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
968 dwc->direction = sconfig->direction;
970 /* Take the request line from slave_id member */
971 if (is_request_line_unset(dwc))
972 dwc->request_line = sconfig->slave_id;
974 convert_burst(&dwc->dma_sconfig.src_maxburst);
975 convert_burst(&dwc->dma_sconfig.dst_maxburst);
980 static inline void dwc_chan_pause(struct dw_dma_chan *dwc)
982 u32 cfglo = channel_readl(dwc, CFG_LO);
983 unsigned int count = 20; /* timeout iterations */
985 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
986 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
992 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
994 u32 cfglo = channel_readl(dwc, CFG_LO);
996 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
1001 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1004 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1005 struct dw_dma *dw = to_dw_dma(chan->device);
1006 struct dw_desc *desc, *_desc;
1007 unsigned long flags;
1010 if (cmd == DMA_PAUSE) {
1011 spin_lock_irqsave(&dwc->lock, flags);
1013 dwc_chan_pause(dwc);
1015 spin_unlock_irqrestore(&dwc->lock, flags);
1016 } else if (cmd == DMA_RESUME) {
1020 spin_lock_irqsave(&dwc->lock, flags);
1022 dwc_chan_resume(dwc);
1024 spin_unlock_irqrestore(&dwc->lock, flags);
1025 } else if (cmd == DMA_TERMINATE_ALL) {
1026 spin_lock_irqsave(&dwc->lock, flags);
1028 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1030 dwc_chan_disable(dw, dwc);
1032 dwc_chan_resume(dwc);
1034 /* active_list entries will end up before queued entries */
1035 list_splice_init(&dwc->queue, &list);
1036 list_splice_init(&dwc->active_list, &list);
1038 spin_unlock_irqrestore(&dwc->lock, flags);
1040 /* Flush all pending and queued descriptors */
1041 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1042 dwc_descriptor_complete(dwc, desc, false);
1043 } else if (cmd == DMA_SLAVE_CONFIG) {
1044 return set_runtime_config(chan, (struct dma_slave_config *)arg);
1052 static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
1054 unsigned long flags;
1057 spin_lock_irqsave(&dwc->lock, flags);
1059 residue = dwc->residue;
1060 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1061 residue -= dwc_get_sent(dwc);
1063 spin_unlock_irqrestore(&dwc->lock, flags);
1067 static enum dma_status
1068 dwc_tx_status(struct dma_chan *chan,
1069 dma_cookie_t cookie,
1070 struct dma_tx_state *txstate)
1072 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1073 enum dma_status ret;
1075 ret = dma_cookie_status(chan, cookie, txstate);
1076 if (ret == DMA_COMPLETE)
1079 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1081 ret = dma_cookie_status(chan, cookie, txstate);
1082 if (ret != DMA_COMPLETE)
1083 dma_set_residue(txstate, dwc_get_residue(dwc));
1085 if (dwc->paused && ret == DMA_IN_PROGRESS)
1091 static void dwc_issue_pending(struct dma_chan *chan)
1093 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1094 unsigned long flags;
1096 spin_lock_irqsave(&dwc->lock, flags);
1097 if (list_empty(&dwc->active_list))
1098 dwc_dostart_first_queued(dwc);
1099 spin_unlock_irqrestore(&dwc->lock, flags);
1102 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1104 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1105 struct dw_dma *dw = to_dw_dma(chan->device);
1106 struct dw_desc *desc;
1108 unsigned long flags;
1110 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1112 /* ASSERT: channel is idle */
1113 if (dma_readl(dw, CH_EN) & dwc->mask) {
1114 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1118 dma_cookie_init(chan);
1121 * NOTE: some controllers may have additional features that we
1122 * need to initialize here, like "scatter-gather" (which
1123 * doesn't mean what you think it means), and status writeback.
1126 dwc_set_masters(dwc);
1128 spin_lock_irqsave(&dwc->lock, flags);
1129 i = dwc->descs_allocated;
1130 while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1133 spin_unlock_irqrestore(&dwc->lock, flags);
1135 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1137 goto err_desc_alloc;
1139 memset(desc, 0, sizeof(struct dw_desc));
1141 INIT_LIST_HEAD(&desc->tx_list);
1142 dma_async_tx_descriptor_init(&desc->txd, chan);
1143 desc->txd.tx_submit = dwc_tx_submit;
1144 desc->txd.flags = DMA_CTRL_ACK;
1145 desc->txd.phys = phys;
1147 dwc_desc_put(dwc, desc);
1149 spin_lock_irqsave(&dwc->lock, flags);
1150 i = ++dwc->descs_allocated;
1153 spin_unlock_irqrestore(&dwc->lock, flags);
1155 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1160 dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1165 static void dwc_free_chan_resources(struct dma_chan *chan)
1167 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1168 struct dw_dma *dw = to_dw_dma(chan->device);
1169 struct dw_desc *desc, *_desc;
1170 unsigned long flags;
1173 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1174 dwc->descs_allocated);
1176 /* ASSERT: channel is idle */
1177 BUG_ON(!list_empty(&dwc->active_list));
1178 BUG_ON(!list_empty(&dwc->queue));
1179 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1181 spin_lock_irqsave(&dwc->lock, flags);
1182 list_splice_init(&dwc->free_list, &list);
1183 dwc->descs_allocated = 0;
1184 dwc->initialized = false;
1185 dwc->request_line = ~0;
1187 /* Disable interrupts */
1188 channel_clear_bit(dw, MASK.XFER, dwc->mask);
1189 channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1191 spin_unlock_irqrestore(&dwc->lock, flags);
1193 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1194 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1195 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1198 dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1201 /* --------------------- Cyclic DMA API extensions -------------------- */
1204 * dw_dma_cyclic_start - start the cyclic DMA transfer
1205 * @chan: the DMA channel to start
1207 * Must be called with soft interrupts disabled. Returns zero on success or
1208 * -errno on failure.
1210 int dw_dma_cyclic_start(struct dma_chan *chan)
1212 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1213 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1214 unsigned long flags;
1216 if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1217 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1221 spin_lock_irqsave(&dwc->lock, flags);
1223 /* Assert channel is idle */
1224 if (dma_readl(dw, CH_EN) & dwc->mask) {
1225 dev_err(chan2dev(&dwc->chan),
1226 "BUG: Attempted to start non-idle channel\n");
1227 dwc_dump_chan_regs(dwc);
1228 spin_unlock_irqrestore(&dwc->lock, flags);
1232 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1233 dma_writel(dw, CLEAR.XFER, dwc->mask);
1235 /* Setup DMAC channel registers */
1236 channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1237 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1238 channel_writel(dwc, CTL_HI, 0);
1240 channel_set_bit(dw, CH_EN, dwc->mask);
1242 spin_unlock_irqrestore(&dwc->lock, flags);
1246 EXPORT_SYMBOL(dw_dma_cyclic_start);
1249 * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1250 * @chan: the DMA channel to stop
1252 * Must be called with soft interrupts disabled.
1254 void dw_dma_cyclic_stop(struct dma_chan *chan)
1256 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1257 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1258 unsigned long flags;
1260 spin_lock_irqsave(&dwc->lock, flags);
1262 dwc_chan_disable(dw, dwc);
1264 spin_unlock_irqrestore(&dwc->lock, flags);
1266 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1269 * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1270 * @chan: the DMA channel to prepare
1271 * @buf_addr: physical DMA address where the buffer starts
1272 * @buf_len: total number of bytes for the entire buffer
1273 * @period_len: number of bytes for each period
1274 * @direction: transfer direction, to or from device
1276 * Must be called before trying to start the transfer. Returns a valid struct
1277 * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1279 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1280 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1281 enum dma_transfer_direction direction)
1283 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1284 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
1285 struct dw_cyclic_desc *cdesc;
1286 struct dw_cyclic_desc *retval = NULL;
1287 struct dw_desc *desc;
1288 struct dw_desc *last = NULL;
1289 unsigned long was_cyclic;
1290 unsigned int reg_width;
1291 unsigned int periods;
1293 unsigned long flags;
1295 spin_lock_irqsave(&dwc->lock, flags);
1297 spin_unlock_irqrestore(&dwc->lock, flags);
1298 dev_dbg(chan2dev(&dwc->chan),
1299 "channel doesn't support LLP transfers\n");
1300 return ERR_PTR(-EINVAL);
1303 if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1304 spin_unlock_irqrestore(&dwc->lock, flags);
1305 dev_dbg(chan2dev(&dwc->chan),
1306 "queue and/or active list are not empty\n");
1307 return ERR_PTR(-EBUSY);
1310 was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1311 spin_unlock_irqrestore(&dwc->lock, flags);
1313 dev_dbg(chan2dev(&dwc->chan),
1314 "channel already prepared for cyclic DMA\n");
1315 return ERR_PTR(-EBUSY);
1318 retval = ERR_PTR(-EINVAL);
1320 if (unlikely(!is_slave_direction(direction)))
1323 dwc->direction = direction;
1325 if (direction == DMA_MEM_TO_DEV)
1326 reg_width = __ffs(sconfig->dst_addr_width);
1328 reg_width = __ffs(sconfig->src_addr_width);
1330 periods = buf_len / period_len;
1332 /* Check for too big/unaligned periods and unaligned DMA buffer. */
1333 if (period_len > (dwc->block_size << reg_width))
1335 if (unlikely(period_len & ((1 << reg_width) - 1)))
1337 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1340 retval = ERR_PTR(-ENOMEM);
1342 if (periods > NR_DESCS_PER_CHANNEL)
1345 cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1349 cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1353 for (i = 0; i < periods; i++) {
1354 desc = dwc_desc_get(dwc);
1356 goto out_err_desc_get;
1358 switch (direction) {
1359 case DMA_MEM_TO_DEV:
1360 desc->lli.dar = sconfig->dst_addr;
1361 desc->lli.sar = buf_addr + (period_len * i);
1362 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1363 | DWC_CTLL_DST_WIDTH(reg_width)
1364 | DWC_CTLL_SRC_WIDTH(reg_width)
1369 desc->lli.ctllo |= sconfig->device_fc ?
1370 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1371 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1374 case DMA_DEV_TO_MEM:
1375 desc->lli.dar = buf_addr + (period_len * i);
1376 desc->lli.sar = sconfig->src_addr;
1377 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1378 | DWC_CTLL_SRC_WIDTH(reg_width)
1379 | DWC_CTLL_DST_WIDTH(reg_width)
1384 desc->lli.ctllo |= sconfig->device_fc ?
1385 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1386 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1393 desc->lli.ctlhi = (period_len >> reg_width);
1394 cdesc->desc[i] = desc;
1397 last->lli.llp = desc->txd.phys;
1402 /* Let's make a cyclic list */
1403 last->lli.llp = cdesc->desc[0]->txd.phys;
1405 dev_dbg(chan2dev(&dwc->chan),
1406 "cyclic prepared buf %pad len %zu period %zu periods %d\n",
1407 &buf_addr, buf_len, period_len, periods);
1409 cdesc->periods = periods;
1416 dwc_desc_put(dwc, cdesc->desc[i]);
1420 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1421 return (struct dw_cyclic_desc *)retval;
1423 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1426 * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1427 * @chan: the DMA channel to free
1429 void dw_dma_cyclic_free(struct dma_chan *chan)
1431 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1432 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1433 struct dw_cyclic_desc *cdesc = dwc->cdesc;
1435 unsigned long flags;
1437 dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1442 spin_lock_irqsave(&dwc->lock, flags);
1444 dwc_chan_disable(dw, dwc);
1446 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1447 dma_writel(dw, CLEAR.XFER, dwc->mask);
1449 spin_unlock_irqrestore(&dwc->lock, flags);
1451 for (i = 0; i < cdesc->periods; i++)
1452 dwc_desc_put(dwc, cdesc->desc[i]);
1457 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1459 EXPORT_SYMBOL(dw_dma_cyclic_free);
1461 /*----------------------------------------------------------------------*/
1463 static void dw_dma_off(struct dw_dma *dw)
1467 dma_writel(dw, CFG, 0);
1469 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1470 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1471 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1472 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1474 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1477 for (i = 0; i < dw->dma.chancnt; i++)
1478 dw->chan[i].initialized = false;
1481 int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
1485 unsigned int dw_params;
1486 unsigned int nr_channels;
1487 unsigned int max_blk_size = 0;
1491 dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
1495 dw->regs = chip->regs;
1498 dw->clk = devm_clk_get(chip->dev, "hclk");
1499 if (IS_ERR(dw->clk))
1500 return PTR_ERR(dw->clk);
1501 err = clk_prepare_enable(dw->clk);
1505 dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
1506 autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1508 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1510 if (!pdata && autocfg) {
1511 pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
1517 /* Fill platform data with the default values */
1518 pdata->is_private = true;
1519 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1520 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1521 } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
1527 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
1529 nr_channels = pdata->nr_channels;
1531 dw->chan = devm_kcalloc(chip->dev, nr_channels, sizeof(*dw->chan),
1538 /* Get hardware configuration parameters */
1540 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1542 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1543 for (i = 0; i < dw->nr_masters; i++) {
1545 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1548 dw->nr_masters = pdata->nr_masters;
1549 memcpy(dw->data_width, pdata->data_width, 4);
1552 /* Calculate all channel mask before DMA setup */
1553 dw->all_chan_mask = (1 << nr_channels) - 1;
1555 /* Force dma off, just in case */
1558 /* Disable BLOCK interrupts as well */
1559 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1561 /* Create a pool of consistent memory blocks for hardware descriptors */
1562 dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
1563 sizeof(struct dw_desc), 4, 0);
1564 if (!dw->desc_pool) {
1565 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1570 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1572 err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
1577 INIT_LIST_HEAD(&dw->dma.channels);
1578 for (i = 0; i < nr_channels; i++) {
1579 struct dw_dma_chan *dwc = &dw->chan[i];
1580 int r = nr_channels - i - 1;
1582 dwc->chan.device = &dw->dma;
1583 dma_cookie_init(&dwc->chan);
1584 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1585 list_add_tail(&dwc->chan.device_node,
1588 list_add(&dwc->chan.device_node, &dw->dma.channels);
1590 /* 7 is highest priority & 0 is lowest. */
1591 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1596 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1597 spin_lock_init(&dwc->lock);
1600 INIT_LIST_HEAD(&dwc->active_list);
1601 INIT_LIST_HEAD(&dwc->queue);
1602 INIT_LIST_HEAD(&dwc->free_list);
1604 channel_clear_bit(dw, CH_EN, dwc->mask);
1606 dwc->direction = DMA_TRANS_NONE;
1607 dwc->request_line = ~0;
1609 /* Hardware configuration */
1611 unsigned int dwc_params;
1612 void __iomem *addr = chip->regs + r * sizeof(u32);
1614 dwc_params = dma_read_byaddr(addr, DWC_PARAMS);
1616 dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1620 * Decode maximum block size for given channel. The
1621 * stored 4 bit value represents blocks from 0x00 for 3
1622 * up to 0x0a for 4095.
1625 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1627 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1629 dwc->block_size = pdata->block_size;
1631 /* Check if channel supports multi block transfer */
1632 channel_writel(dwc, LLP, 0xfffffffc);
1634 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1635 channel_writel(dwc, LLP, 0);
1639 /* Clear all interrupts on all channels. */
1640 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1641 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1642 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1643 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1644 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1646 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1647 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1648 if (pdata->is_private)
1649 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1650 dw->dma.dev = chip->dev;
1651 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1652 dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1654 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1656 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1657 dw->dma.device_control = dwc_control;
1659 dw->dma.device_tx_status = dwc_tx_status;
1660 dw->dma.device_issue_pending = dwc_issue_pending;
1662 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1664 err = dma_async_device_register(&dw->dma);
1666 goto err_dma_register;
1668 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1674 free_irq(chip->irq, dw);
1676 clk_disable_unprepare(dw->clk);
1679 EXPORT_SYMBOL_GPL(dw_dma_probe);
1681 int dw_dma_remove(struct dw_dma_chip *chip)
1683 struct dw_dma *dw = chip->dw;
1684 struct dw_dma_chan *dwc, *_dwc;
1687 dma_async_device_unregister(&dw->dma);
1689 free_irq(chip->irq, dw);
1690 tasklet_kill(&dw->tasklet);
1692 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1694 list_del(&dwc->chan.device_node);
1695 channel_clear_bit(dw, CH_EN, dwc->mask);
1698 clk_disable_unprepare(dw->clk);
1702 EXPORT_SYMBOL_GPL(dw_dma_remove);
1704 void dw_dma_shutdown(struct dw_dma_chip *chip)
1706 struct dw_dma *dw = chip->dw;
1709 clk_disable_unprepare(dw->clk);
1711 EXPORT_SYMBOL_GPL(dw_dma_shutdown);
1713 #ifdef CONFIG_PM_SLEEP
1715 int dw_dma_suspend(struct dw_dma_chip *chip)
1717 struct dw_dma *dw = chip->dw;
1720 clk_disable_unprepare(dw->clk);
1724 EXPORT_SYMBOL_GPL(dw_dma_suspend);
1726 int dw_dma_resume(struct dw_dma_chip *chip)
1728 struct dw_dma *dw = chip->dw;
1730 clk_prepare_enable(dw->clk);
1731 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1735 EXPORT_SYMBOL_GPL(dw_dma_resume);
1737 #endif /* CONFIG_PM_SLEEP */
1739 MODULE_LICENSE("GPL v2");
1740 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1741 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1742 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");