2 * Driver for the Synopsys DesignWare AHB DMA Controller
4 * Copyright (C) 2005-2007 Atmel Corporation
5 * Copyright (C) 2010-2011 ST Microelectronics
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/interrupt.h>
13 #include <linux/dmaengine.h>
14 #include <linux/dw_dmac.h>
16 #define DW_DMA_MAX_NR_CHANNELS 8
17 #define DW_DMA_MAX_NR_REQUESTS 16
32 * Redefine this macro to handle differences between 32- and 64-bit
33 * addressing, big vs. little endian, etc.
35 #define DW_REG(name) u32 name; u32 __pad_##name
37 /* Hardware register definitions. */
38 struct dw_dma_chan_regs {
39 DW_REG(SAR); /* Source Address Register */
40 DW_REG(DAR); /* Destination Address Register */
41 DW_REG(LLP); /* Linked List Pointer */
42 u32 CTL_LO; /* Control Register Low */
43 u32 CTL_HI; /* Control Register High */
48 u32 CFG_LO; /* Configuration Register Low */
49 u32 CFG_HI; /* Configuration Register High */
54 struct dw_dma_irq_regs {
63 /* per-channel registers */
64 struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS];
67 struct dw_dma_irq_regs RAW; /* r */
68 struct dw_dma_irq_regs STATUS; /* r (raw & mask) */
69 struct dw_dma_irq_regs MASK; /* rw (set = irq enabled) */
70 struct dw_dma_irq_regs CLEAR; /* w (ack, affects "raw") */
72 DW_REG(STATUS_INT); /* r */
74 /* software handshaking */
92 /* optional encoded params, 0x3c8..0x3f7 */
95 /* per-channel configuration registers */
96 u32 DWC_PARAMS[DW_DMA_MAX_NR_CHANNELS];
100 /* top-level parameters */
104 #ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
105 #define dma_readl_native ioread32be
106 #define dma_writel_native iowrite32be
108 #define dma_readl_native readl
109 #define dma_writel_native writel
112 /* To access the registers in early stage of probe */
113 #define dma_read_byaddr(addr, name) \
114 dma_readl_native((addr) + offsetof(struct dw_dma_regs, name))
116 /* Bitfields in DW_PARAMS */
117 #define DW_PARAMS_NR_CHAN 8 /* number of channels */
118 #define DW_PARAMS_NR_MASTER 11 /* number of AHB masters */
119 #define DW_PARAMS_DATA_WIDTH(n) (15 + 2 * (n))
120 #define DW_PARAMS_DATA_WIDTH1 15 /* master 1 data width */
121 #define DW_PARAMS_DATA_WIDTH2 17 /* master 2 data width */
122 #define DW_PARAMS_DATA_WIDTH3 19 /* master 3 data width */
123 #define DW_PARAMS_DATA_WIDTH4 21 /* master 4 data width */
124 #define DW_PARAMS_EN 28 /* encoded parameters */
126 /* Bitfields in DWC_PARAMS */
127 #define DWC_PARAMS_MBLK_EN 11 /* multi block transfer */
129 /* Bitfields in CTL_LO */
130 #define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */
131 #define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */
132 #define DWC_CTLL_SRC_WIDTH(n) ((n)<<4)
133 #define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */
134 #define DWC_CTLL_DST_DEC (1<<7)
135 #define DWC_CTLL_DST_FIX (2<<7)
136 #define DWC_CTLL_SRC_INC (0<<7) /* SAR update/not */
137 #define DWC_CTLL_SRC_DEC (1<<9)
138 #define DWC_CTLL_SRC_FIX (2<<9)
139 #define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */
140 #define DWC_CTLL_SRC_MSIZE(n) ((n)<<14)
141 #define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */
142 #define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */
143 #define DWC_CTLL_FC(n) ((n) << 20)
144 #define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */
145 #define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */
146 #define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */
147 #define DWC_CTLL_FC_P2P (3 << 20) /* periph-to-periph */
148 /* plus 4 transfer types for peripheral-as-flow-controller */
149 #define DWC_CTLL_DMS(n) ((n)<<23) /* dst master select */
150 #define DWC_CTLL_SMS(n) ((n)<<25) /* src master select */
151 #define DWC_CTLL_LLP_D_EN (1 << 27) /* dest block chain */
152 #define DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */
154 /* Bitfields in CTL_HI */
155 #define DWC_CTLH_DONE 0x00001000
156 #define DWC_CTLH_BLOCK_TS_MASK 0x00000fff
158 /* Bitfields in CFG_LO. Platform-configurable bits are in <linux/dw_dmac.h> */
159 #define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */
160 #define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */
161 #define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */
162 #define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */
163 #define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */
164 #define DWC_CFGL_HS_SRC (1 << 11) /* handshake w/src */
165 #define DWC_CFGL_MAX_BURST(x) ((x) << 20)
166 #define DWC_CFGL_RELOAD_SAR (1 << 30)
167 #define DWC_CFGL_RELOAD_DAR (1 << 31)
169 /* Bitfields in CFG_HI. Platform-configurable bits are in <linux/dw_dmac.h> */
170 #define DWC_CFGH_DS_UPD_EN (1 << 5)
171 #define DWC_CFGH_SS_UPD_EN (1 << 6)
173 /* Bitfields in SGR */
174 #define DWC_SGR_SGI(x) ((x) << 0)
175 #define DWC_SGR_SGC(x) ((x) << 20)
177 /* Bitfields in DSR */
178 #define DWC_DSR_DSI(x) ((x) << 0)
179 #define DWC_DSR_DSC(x) ((x) << 20)
181 /* Bitfields in CFG */
182 #define DW_CFG_DMA_EN (1 << 0)
185 DW_DMA_IS_CYCLIC = 0,
186 DW_DMA_IS_SOFT_LLP = 1,
190 struct dma_chan chan;
191 void __iomem *ch_regs;
194 enum dma_transfer_direction direction;
198 /* software emulation of the LLP transfers */
199 struct list_head *tx_node_active;
203 /* these other elements are all protected by lock */
205 struct list_head active_list;
206 struct list_head queue;
207 struct list_head free_list;
209 struct dw_cyclic_desc *cdesc;
211 unsigned int descs_allocated;
213 /* hardware configuration */
214 unsigned int block_size;
217 /* custom slave configuration */
218 unsigned int request_line;
219 unsigned char src_master;
220 unsigned char dst_master;
222 /* configuration passed via DMA_SLAVE_CONFIG */
223 struct dma_slave_config dma_sconfig;
226 static inline struct dw_dma_chan_regs __iomem *
227 __dwc_regs(struct dw_dma_chan *dwc)
232 #define channel_readl(dwc, name) \
233 dma_readl_native(&(__dwc_regs(dwc)->name))
234 #define channel_writel(dwc, name, val) \
235 dma_writel_native((val), &(__dwc_regs(dwc)->name))
237 static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
239 return container_of(chan, struct dw_dma_chan, chan);
243 struct dma_device dma;
245 struct dma_pool *desc_pool;
246 struct tasklet_struct tasklet;
251 /* hardware configuration */
252 unsigned char nr_masters;
253 unsigned char data_width[4];
255 struct dw_dma_chan chan[0];
258 static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
263 #define dma_readl(dw, name) \
264 dma_readl_native(&(__dw_regs(dw)->name))
265 #define dma_writel(dw, name, val) \
266 dma_writel_native((val), &(__dw_regs(dw)->name))
268 #define channel_set_bit(dw, reg, mask) \
269 dma_writel(dw, reg, ((mask) << 8) | (mask))
270 #define channel_clear_bit(dw, reg, mask) \
271 dma_writel(dw, reg, ((mask) << 8) | 0)
273 static inline struct dw_dma *to_dw_dma(struct dma_device *ddev)
275 return container_of(ddev, struct dw_dma, dma);
278 /* LLI == Linked List Item; a.k.a. DMA block descriptor */
280 /* values that are not changed by hardware */
283 u32 llp; /* chain to next lli */
285 /* values that may get written back: */
287 /* sstat and dstat can snapshot peripheral register state.
288 * silicon config may discard either or both...
295 /* FIRST values the hardware uses */
298 /* THEN values for driver housekeeping */
299 struct list_head desc_node;
300 struct list_head tx_list;
301 struct dma_async_tx_descriptor txd;
306 #define to_dw_desc(h) list_entry(h, struct dw_desc, desc_node)
308 static inline struct dw_desc *
309 txd_to_dw_desc(struct dma_async_tx_descriptor *txd)
311 return container_of(txd, struct dw_desc, txd);