2 * Core driver for the Synopsys DesignWare DMA Controller
4 * Copyright (C) 2007-2008 Atmel Corporation
5 * Copyright (C) 2010-2011 ST Microelectronics
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
26 #include "dw_dmac_regs.h"
27 #include "dmaengine.h"
30 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
31 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
32 * of which use ARM any more). See the "Databook" from Synopsys for
33 * information beyond what licensees probably provide.
35 * The driver has currently been tested only with the Atmel AT32AP7000,
36 * which does not support descriptor writeback.
39 static inline unsigned int dwc_get_dms(struct dw_dma_slave *slave)
41 return slave ? slave->dst_master : 0;
44 static inline unsigned int dwc_get_sms(struct dw_dma_slave *slave)
46 return slave ? slave->src_master : 1;
49 #define DWC_DEFAULT_CTLLO(_chan) ({ \
50 struct dw_dma_slave *__slave = (_chan->private); \
51 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \
52 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
53 int _dms = dwc_get_dms(__slave); \
54 int _sms = dwc_get_sms(__slave); \
55 u8 _smsize = __slave ? _sconfig->src_maxburst : \
57 u8 _dmsize = __slave ? _sconfig->dst_maxburst : \
60 (DWC_CTLL_DST_MSIZE(_dmsize) \
61 | DWC_CTLL_SRC_MSIZE(_smsize) \
64 | DWC_CTLL_DMS(_dms) \
65 | DWC_CTLL_SMS(_sms)); \
69 * Number of descriptors to allocate for each channel. This should be
70 * made configurable somehow; preferably, the clients (at least the
71 * ones using slave transfers) should be able to give us a hint.
73 #define NR_DESCS_PER_CHANNEL 64
75 /*----------------------------------------------------------------------*/
78 * Because we're not relying on writeback from the controller (it may not
79 * even be configured into the core!) we don't need to use dma_pool. These
80 * descriptors -- and associated data -- are cacheable. We do need to make
81 * sure their dcache entries are written back before handing them off to
82 * the controller, though.
85 static struct device *chan2dev(struct dma_chan *chan)
87 return &chan->dev->device;
89 static struct device *chan2parent(struct dma_chan *chan)
91 return chan->dev->device.parent;
94 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
96 return to_dw_desc(dwc->active_list.next);
99 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
101 struct dw_desc *desc, *_desc;
102 struct dw_desc *ret = NULL;
106 spin_lock_irqsave(&dwc->lock, flags);
107 list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
109 if (async_tx_test_ack(&desc->txd)) {
110 list_del(&desc->desc_node);
114 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
116 spin_unlock_irqrestore(&dwc->lock, flags);
118 dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
123 static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc)
125 struct dw_desc *child;
127 list_for_each_entry(child, &desc->tx_list, desc_node)
128 dma_sync_single_for_cpu(chan2parent(&dwc->chan),
129 child->txd.phys, sizeof(child->lli),
131 dma_sync_single_for_cpu(chan2parent(&dwc->chan),
132 desc->txd.phys, sizeof(desc->lli),
137 * Move a descriptor, including any children, to the free list.
138 * `desc' must not be on any lists.
140 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
145 struct dw_desc *child;
147 dwc_sync_desc_for_cpu(dwc, desc);
149 spin_lock_irqsave(&dwc->lock, flags);
150 list_for_each_entry(child, &desc->tx_list, desc_node)
151 dev_vdbg(chan2dev(&dwc->chan),
152 "moving child desc %p to freelist\n",
154 list_splice_init(&desc->tx_list, &dwc->free_list);
155 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
156 list_add(&desc->desc_node, &dwc->free_list);
157 spin_unlock_irqrestore(&dwc->lock, flags);
161 static void dwc_initialize(struct dw_dma_chan *dwc)
163 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
164 struct dw_dma_slave *dws = dwc->chan.private;
165 u32 cfghi = DWC_CFGH_FIFO_MODE;
166 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
168 if (dwc->initialized == true)
173 * We need controller-specific data to set up slave
176 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
179 cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
181 if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV)
182 cfghi = DWC_CFGH_DST_PER(dwc->dma_sconfig.slave_id);
183 else if (dwc->dma_sconfig.direction == DMA_DEV_TO_MEM)
184 cfghi = DWC_CFGH_SRC_PER(dwc->dma_sconfig.slave_id);
187 channel_writel(dwc, CFG_LO, cfglo);
188 channel_writel(dwc, CFG_HI, cfghi);
190 /* Enable interrupts */
191 channel_set_bit(dw, MASK.XFER, dwc->mask);
192 channel_set_bit(dw, MASK.ERROR, dwc->mask);
194 dwc->initialized = true;
197 /*----------------------------------------------------------------------*/
199 static inline unsigned int dwc_fast_fls(unsigned long long v)
202 * We can be a lot more clever here, but this should take care
203 * of the most common optimization.
214 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
216 dev_err(chan2dev(&dwc->chan),
217 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
218 channel_readl(dwc, SAR),
219 channel_readl(dwc, DAR),
220 channel_readl(dwc, LLP),
221 channel_readl(dwc, CTL_HI),
222 channel_readl(dwc, CTL_LO));
225 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
227 channel_clear_bit(dw, CH_EN, dwc->mask);
228 while (dma_readl(dw, CH_EN) & dwc->mask)
232 /*----------------------------------------------------------------------*/
234 /* Perform single block transfer */
235 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
236 struct dw_desc *desc)
238 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
241 /* Software emulation of LLP mode relies on interrupts to continue
242 * multi block transfer. */
243 ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
245 channel_writel(dwc, SAR, desc->lli.sar);
246 channel_writel(dwc, DAR, desc->lli.dar);
247 channel_writel(dwc, CTL_LO, ctllo);
248 channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
249 channel_set_bit(dw, CH_EN, dwc->mask);
251 /* Move pointer to next descriptor */
252 dwc->tx_node_active = dwc->tx_node_active->next;
255 /* Called with dwc->lock held and bh disabled */
256 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
258 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
259 unsigned long was_soft_llp;
261 /* ASSERT: channel is idle */
262 if (dma_readl(dw, CH_EN) & dwc->mask) {
263 dev_err(chan2dev(&dwc->chan),
264 "BUG: Attempted to start non-idle channel\n");
265 dwc_dump_chan_regs(dwc);
267 /* The tasklet will hopefully advance the queue... */
272 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
275 dev_err(chan2dev(&dwc->chan),
276 "BUG: Attempted to start new LLP transfer "
277 "inside ongoing one\n");
283 dwc->tx_list = &first->tx_list;
284 dwc->tx_node_active = &first->tx_list;
286 dwc_do_single_block(dwc, first);
293 channel_writel(dwc, LLP, first->txd.phys);
294 channel_writel(dwc, CTL_LO,
295 DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
296 channel_writel(dwc, CTL_HI, 0);
297 channel_set_bit(dw, CH_EN, dwc->mask);
300 /*----------------------------------------------------------------------*/
303 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
304 bool callback_required)
306 dma_async_tx_callback callback = NULL;
308 struct dma_async_tx_descriptor *txd = &desc->txd;
309 struct dw_desc *child;
312 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
314 spin_lock_irqsave(&dwc->lock, flags);
315 dma_cookie_complete(txd);
316 if (callback_required) {
317 callback = txd->callback;
318 param = txd->callback_param;
321 dwc_sync_desc_for_cpu(dwc, desc);
324 list_for_each_entry(child, &desc->tx_list, desc_node)
325 async_tx_ack(&child->txd);
326 async_tx_ack(&desc->txd);
328 list_splice_init(&desc->tx_list, &dwc->free_list);
329 list_move(&desc->desc_node, &dwc->free_list);
331 if (!dwc->chan.private) {
332 struct device *parent = chan2parent(&dwc->chan);
333 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
334 if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
335 dma_unmap_single(parent, desc->lli.dar,
336 desc->len, DMA_FROM_DEVICE);
338 dma_unmap_page(parent, desc->lli.dar,
339 desc->len, DMA_FROM_DEVICE);
341 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
342 if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
343 dma_unmap_single(parent, desc->lli.sar,
344 desc->len, DMA_TO_DEVICE);
346 dma_unmap_page(parent, desc->lli.sar,
347 desc->len, DMA_TO_DEVICE);
351 spin_unlock_irqrestore(&dwc->lock, flags);
357 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
359 struct dw_desc *desc, *_desc;
363 spin_lock_irqsave(&dwc->lock, flags);
364 if (dma_readl(dw, CH_EN) & dwc->mask) {
365 dev_err(chan2dev(&dwc->chan),
366 "BUG: XFER bit set, but channel not idle!\n");
368 /* Try to continue after resetting the channel... */
369 dwc_chan_disable(dw, dwc);
373 * Submit queued descriptors ASAP, i.e. before we go through
374 * the completed ones.
376 list_splice_init(&dwc->active_list, &list);
377 if (!list_empty(&dwc->queue)) {
378 list_move(dwc->queue.next, &dwc->active_list);
379 dwc_dostart(dwc, dwc_first_active(dwc));
382 spin_unlock_irqrestore(&dwc->lock, flags);
384 list_for_each_entry_safe(desc, _desc, &list, desc_node)
385 dwc_descriptor_complete(dwc, desc, true);
388 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
391 struct dw_desc *desc, *_desc;
392 struct dw_desc *child;
396 spin_lock_irqsave(&dwc->lock, flags);
397 llp = channel_readl(dwc, LLP);
398 status_xfer = dma_readl(dw, RAW.XFER);
400 if (status_xfer & dwc->mask) {
401 /* Everything we've submitted is done */
402 dma_writel(dw, CLEAR.XFER, dwc->mask);
403 spin_unlock_irqrestore(&dwc->lock, flags);
405 dwc_complete_all(dw, dwc);
409 if (list_empty(&dwc->active_list)) {
410 spin_unlock_irqrestore(&dwc->lock, flags);
414 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__,
415 (unsigned long long)llp);
417 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
418 /* check first descriptors addr */
419 if (desc->txd.phys == llp) {
420 spin_unlock_irqrestore(&dwc->lock, flags);
424 /* check first descriptors llp */
425 if (desc->lli.llp == llp) {
426 /* This one is currently in progress */
427 spin_unlock_irqrestore(&dwc->lock, flags);
431 list_for_each_entry(child, &desc->tx_list, desc_node)
432 if (child->lli.llp == llp) {
433 /* Currently in progress */
434 spin_unlock_irqrestore(&dwc->lock, flags);
439 * No descriptors so far seem to be in progress, i.e.
440 * this one must be done.
442 spin_unlock_irqrestore(&dwc->lock, flags);
443 dwc_descriptor_complete(dwc, desc, true);
444 spin_lock_irqsave(&dwc->lock, flags);
447 dev_err(chan2dev(&dwc->chan),
448 "BUG: All descriptors done, but channel not idle!\n");
450 /* Try to continue after resetting the channel... */
451 dwc_chan_disable(dw, dwc);
453 if (!list_empty(&dwc->queue)) {
454 list_move(dwc->queue.next, &dwc->active_list);
455 dwc_dostart(dwc, dwc_first_active(dwc));
457 spin_unlock_irqrestore(&dwc->lock, flags);
460 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
462 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
463 lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
466 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
468 struct dw_desc *bad_desc;
469 struct dw_desc *child;
472 dwc_scan_descriptors(dw, dwc);
474 spin_lock_irqsave(&dwc->lock, flags);
477 * The descriptor currently at the head of the active list is
478 * borked. Since we don't have any way to report errors, we'll
479 * just have to scream loudly and try to carry on.
481 bad_desc = dwc_first_active(dwc);
482 list_del_init(&bad_desc->desc_node);
483 list_move(dwc->queue.next, dwc->active_list.prev);
485 /* Clear the error flag and try to restart the controller */
486 dma_writel(dw, CLEAR.ERROR, dwc->mask);
487 if (!list_empty(&dwc->active_list))
488 dwc_dostart(dwc, dwc_first_active(dwc));
491 * WARN may seem harsh, but since this only happens
492 * when someone submits a bad physical address in a
493 * descriptor, we should consider ourselves lucky that the
494 * controller flagged an error instead of scribbling over
495 * random memory locations.
497 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
498 " cookie: %d\n", bad_desc->txd.cookie);
499 dwc_dump_lli(dwc, &bad_desc->lli);
500 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
501 dwc_dump_lli(dwc, &child->lli);
503 spin_unlock_irqrestore(&dwc->lock, flags);
505 /* Pretend the descriptor completed successfully */
506 dwc_descriptor_complete(dwc, bad_desc, true);
509 /* --------------------- Cyclic DMA API extensions -------------------- */
511 inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
513 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
514 return channel_readl(dwc, SAR);
516 EXPORT_SYMBOL(dw_dma_get_src_addr);
518 inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
520 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
521 return channel_readl(dwc, DAR);
523 EXPORT_SYMBOL(dw_dma_get_dst_addr);
525 /* called with dwc->lock held and all DMAC interrupts disabled */
526 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
527 u32 status_err, u32 status_xfer)
532 void (*callback)(void *param);
533 void *callback_param;
535 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
536 channel_readl(dwc, LLP));
538 callback = dwc->cdesc->period_callback;
539 callback_param = dwc->cdesc->period_callback_param;
542 callback(callback_param);
546 * Error and transfer complete are highly unlikely, and will most
547 * likely be due to a configuration error by the user.
549 if (unlikely(status_err & dwc->mask) ||
550 unlikely(status_xfer & dwc->mask)) {
553 dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s "
554 "interrupt, stopping DMA transfer\n",
555 status_xfer ? "xfer" : "error");
557 spin_lock_irqsave(&dwc->lock, flags);
559 dwc_dump_chan_regs(dwc);
561 dwc_chan_disable(dw, dwc);
563 /* make sure DMA does not restart by loading a new list */
564 channel_writel(dwc, LLP, 0);
565 channel_writel(dwc, CTL_LO, 0);
566 channel_writel(dwc, CTL_HI, 0);
568 dma_writel(dw, CLEAR.ERROR, dwc->mask);
569 dma_writel(dw, CLEAR.XFER, dwc->mask);
571 for (i = 0; i < dwc->cdesc->periods; i++)
572 dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
574 spin_unlock_irqrestore(&dwc->lock, flags);
578 /* ------------------------------------------------------------------------- */
580 static void dw_dma_tasklet(unsigned long data)
582 struct dw_dma *dw = (struct dw_dma *)data;
583 struct dw_dma_chan *dwc;
588 status_xfer = dma_readl(dw, RAW.XFER);
589 status_err = dma_readl(dw, RAW.ERROR);
591 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
593 for (i = 0; i < dw->dma.chancnt; i++) {
595 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
596 dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
597 else if (status_err & (1 << i))
598 dwc_handle_error(dw, dwc);
599 else if (status_xfer & (1 << i)) {
602 spin_lock_irqsave(&dwc->lock, flags);
603 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
604 if (dwc->tx_node_active != dwc->tx_list) {
605 struct dw_desc *desc =
606 to_dw_desc(dwc->tx_node_active);
608 dma_writel(dw, CLEAR.XFER, dwc->mask);
610 dwc_do_single_block(dwc, desc);
612 spin_unlock_irqrestore(&dwc->lock, flags);
615 /* we are done here */
616 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
618 spin_unlock_irqrestore(&dwc->lock, flags);
620 dwc_scan_descriptors(dw, dwc);
625 * Re-enable interrupts.
627 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
628 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
631 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
633 struct dw_dma *dw = dev_id;
636 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__,
637 dma_readl(dw, STATUS_INT));
640 * Just disable the interrupts. We'll turn them back on in the
643 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
644 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
646 status = dma_readl(dw, STATUS_INT);
649 "BUG: Unexpected interrupts pending: 0x%x\n",
653 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
654 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
655 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
656 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
659 tasklet_schedule(&dw->tasklet);
664 /*----------------------------------------------------------------------*/
666 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
668 struct dw_desc *desc = txd_to_dw_desc(tx);
669 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
673 spin_lock_irqsave(&dwc->lock, flags);
674 cookie = dma_cookie_assign(tx);
677 * REVISIT: We should attempt to chain as many descriptors as
678 * possible, perhaps even appending to those already submitted
679 * for DMA. But this is hard to do in a race-free manner.
681 if (list_empty(&dwc->active_list)) {
682 dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__,
684 list_add_tail(&desc->desc_node, &dwc->active_list);
685 dwc_dostart(dwc, dwc_first_active(dwc));
687 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__,
690 list_add_tail(&desc->desc_node, &dwc->queue);
693 spin_unlock_irqrestore(&dwc->lock, flags);
698 static struct dma_async_tx_descriptor *
699 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
700 size_t len, unsigned long flags)
702 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
703 struct dw_dma_slave *dws = chan->private;
704 struct dw_desc *desc;
705 struct dw_desc *first;
706 struct dw_desc *prev;
709 unsigned int src_width;
710 unsigned int dst_width;
711 unsigned int data_width;
714 dev_vdbg(chan2dev(chan),
715 "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__,
716 (unsigned long long)dest, (unsigned long long)src,
719 if (unlikely(!len)) {
720 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
724 data_width = min_t(unsigned int, dwc->dw->data_width[dwc_get_sms(dws)],
725 dwc->dw->data_width[dwc_get_dms(dws)]);
727 src_width = dst_width = min_t(unsigned int, data_width,
728 dwc_fast_fls(src | dest | len));
730 ctllo = DWC_DEFAULT_CTLLO(chan)
731 | DWC_CTLL_DST_WIDTH(dst_width)
732 | DWC_CTLL_SRC_WIDTH(src_width)
738 for (offset = 0; offset < len; offset += xfer_count << src_width) {
739 xfer_count = min_t(size_t, (len - offset) >> src_width,
742 desc = dwc_desc_get(dwc);
746 desc->lli.sar = src + offset;
747 desc->lli.dar = dest + offset;
748 desc->lli.ctllo = ctllo;
749 desc->lli.ctlhi = xfer_count;
754 prev->lli.llp = desc->txd.phys;
755 dma_sync_single_for_device(chan2parent(chan),
756 prev->txd.phys, sizeof(prev->lli),
758 list_add_tail(&desc->desc_node,
765 if (flags & DMA_PREP_INTERRUPT)
766 /* Trigger interrupt after last block */
767 prev->lli.ctllo |= DWC_CTLL_INT_EN;
770 dma_sync_single_for_device(chan2parent(chan),
771 prev->txd.phys, sizeof(prev->lli),
774 first->txd.flags = flags;
780 dwc_desc_put(dwc, first);
784 static struct dma_async_tx_descriptor *
785 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
786 unsigned int sg_len, enum dma_transfer_direction direction,
787 unsigned long flags, void *context)
789 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
790 struct dw_dma_slave *dws = chan->private;
791 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
792 struct dw_desc *prev;
793 struct dw_desc *first;
796 unsigned int reg_width;
797 unsigned int mem_width;
798 unsigned int data_width;
800 struct scatterlist *sg;
801 size_t total_len = 0;
803 dev_vdbg(chan2dev(chan), "%s\n", __func__);
805 if (unlikely(!dws || !sg_len))
812 reg_width = __fls(sconfig->dst_addr_width);
813 reg = sconfig->dst_addr;
814 ctllo = (DWC_DEFAULT_CTLLO(chan)
815 | DWC_CTLL_DST_WIDTH(reg_width)
819 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
820 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
822 data_width = dwc->dw->data_width[dwc_get_sms(dws)];
824 for_each_sg(sgl, sg, sg_len, i) {
825 struct dw_desc *desc;
828 mem = sg_dma_address(sg);
829 len = sg_dma_len(sg);
831 mem_width = min_t(unsigned int,
832 data_width, dwc_fast_fls(mem | len));
834 slave_sg_todev_fill_desc:
835 desc = dwc_desc_get(dwc);
837 dev_err(chan2dev(chan),
838 "not enough descriptors available\n");
844 desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
845 if ((len >> mem_width) > dwc->block_size) {
846 dlen = dwc->block_size << mem_width;
854 desc->lli.ctlhi = dlen >> mem_width;
859 prev->lli.llp = desc->txd.phys;
860 dma_sync_single_for_device(chan2parent(chan),
864 list_add_tail(&desc->desc_node,
871 goto slave_sg_todev_fill_desc;
875 reg_width = __fls(sconfig->src_addr_width);
876 reg = sconfig->src_addr;
877 ctllo = (DWC_DEFAULT_CTLLO(chan)
878 | DWC_CTLL_SRC_WIDTH(reg_width)
882 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
883 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
885 data_width = dwc->dw->data_width[dwc_get_dms(dws)];
887 for_each_sg(sgl, sg, sg_len, i) {
888 struct dw_desc *desc;
891 mem = sg_dma_address(sg);
892 len = sg_dma_len(sg);
894 mem_width = min_t(unsigned int,
895 data_width, dwc_fast_fls(mem | len));
897 slave_sg_fromdev_fill_desc:
898 desc = dwc_desc_get(dwc);
900 dev_err(chan2dev(chan),
901 "not enough descriptors available\n");
907 desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
908 if ((len >> reg_width) > dwc->block_size) {
909 dlen = dwc->block_size << reg_width;
916 desc->lli.ctlhi = dlen >> reg_width;
921 prev->lli.llp = desc->txd.phys;
922 dma_sync_single_for_device(chan2parent(chan),
926 list_add_tail(&desc->desc_node,
933 goto slave_sg_fromdev_fill_desc;
940 if (flags & DMA_PREP_INTERRUPT)
941 /* Trigger interrupt after last block */
942 prev->lli.ctllo |= DWC_CTLL_INT_EN;
945 dma_sync_single_for_device(chan2parent(chan),
946 prev->txd.phys, sizeof(prev->lli),
949 first->len = total_len;
954 dwc_desc_put(dwc, first);
959 * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
960 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
962 * NOTE: burst size 2 is not supported by controller.
964 * This can be done by finding least significant bit set: n & (n - 1)
966 static inline void convert_burst(u32 *maxburst)
969 *maxburst = fls(*maxburst) - 2;
975 set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
977 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
979 /* Check if it is chan is configured for slave transfers */
983 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
985 convert_burst(&dwc->dma_sconfig.src_maxburst);
986 convert_burst(&dwc->dma_sconfig.dst_maxburst);
991 static inline void dwc_chan_pause(struct dw_dma_chan *dwc)
993 u32 cfglo = channel_readl(dwc, CFG_LO);
995 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
996 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY))
1002 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
1004 u32 cfglo = channel_readl(dwc, CFG_LO);
1006 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
1008 dwc->paused = false;
1011 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1014 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1015 struct dw_dma *dw = to_dw_dma(chan->device);
1016 struct dw_desc *desc, *_desc;
1017 unsigned long flags;
1020 if (cmd == DMA_PAUSE) {
1021 spin_lock_irqsave(&dwc->lock, flags);
1023 dwc_chan_pause(dwc);
1025 spin_unlock_irqrestore(&dwc->lock, flags);
1026 } else if (cmd == DMA_RESUME) {
1030 spin_lock_irqsave(&dwc->lock, flags);
1032 dwc_chan_resume(dwc);
1034 spin_unlock_irqrestore(&dwc->lock, flags);
1035 } else if (cmd == DMA_TERMINATE_ALL) {
1036 spin_lock_irqsave(&dwc->lock, flags);
1038 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1040 dwc_chan_disable(dw, dwc);
1042 dwc->paused = false;
1044 /* active_list entries will end up before queued entries */
1045 list_splice_init(&dwc->queue, &list);
1046 list_splice_init(&dwc->active_list, &list);
1048 spin_unlock_irqrestore(&dwc->lock, flags);
1050 /* Flush all pending and queued descriptors */
1051 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1052 dwc_descriptor_complete(dwc, desc, false);
1053 } else if (cmd == DMA_SLAVE_CONFIG) {
1054 return set_runtime_config(chan, (struct dma_slave_config *)arg);
1062 static enum dma_status
1063 dwc_tx_status(struct dma_chan *chan,
1064 dma_cookie_t cookie,
1065 struct dma_tx_state *txstate)
1067 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1068 enum dma_status ret;
1070 ret = dma_cookie_status(chan, cookie, txstate);
1071 if (ret != DMA_SUCCESS) {
1072 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1074 ret = dma_cookie_status(chan, cookie, txstate);
1077 if (ret != DMA_SUCCESS)
1078 dma_set_residue(txstate, dwc_first_active(dwc)->len);
1086 static void dwc_issue_pending(struct dma_chan *chan)
1088 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1090 if (!list_empty(&dwc->queue))
1091 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1094 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1096 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1097 struct dw_dma *dw = to_dw_dma(chan->device);
1098 struct dw_desc *desc;
1100 unsigned long flags;
1103 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1105 /* ASSERT: channel is idle */
1106 if (dma_readl(dw, CH_EN) & dwc->mask) {
1107 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1111 dma_cookie_init(chan);
1114 * NOTE: some controllers may have additional features that we
1115 * need to initialize here, like "scatter-gather" (which
1116 * doesn't mean what you think it means), and status writeback.
1119 spin_lock_irqsave(&dwc->lock, flags);
1120 i = dwc->descs_allocated;
1121 while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1122 spin_unlock_irqrestore(&dwc->lock, flags);
1124 desc = kzalloc(sizeof(struct dw_desc), GFP_KERNEL);
1126 goto err_desc_alloc;
1128 INIT_LIST_HEAD(&desc->tx_list);
1129 dma_async_tx_descriptor_init(&desc->txd, chan);
1130 desc->txd.tx_submit = dwc_tx_submit;
1131 desc->txd.flags = DMA_CTRL_ACK;
1132 desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli,
1133 sizeof(desc->lli), DMA_TO_DEVICE);
1134 ret = dma_mapping_error(chan2parent(chan), desc->txd.phys);
1136 goto err_desc_alloc;
1138 dwc_desc_put(dwc, desc);
1140 spin_lock_irqsave(&dwc->lock, flags);
1141 i = ++dwc->descs_allocated;
1144 spin_unlock_irqrestore(&dwc->lock, flags);
1146 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1153 dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1158 static void dwc_free_chan_resources(struct dma_chan *chan)
1160 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1161 struct dw_dma *dw = to_dw_dma(chan->device);
1162 struct dw_desc *desc, *_desc;
1163 unsigned long flags;
1166 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1167 dwc->descs_allocated);
1169 /* ASSERT: channel is idle */
1170 BUG_ON(!list_empty(&dwc->active_list));
1171 BUG_ON(!list_empty(&dwc->queue));
1172 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1174 spin_lock_irqsave(&dwc->lock, flags);
1175 list_splice_init(&dwc->free_list, &list);
1176 dwc->descs_allocated = 0;
1177 dwc->initialized = false;
1179 /* Disable interrupts */
1180 channel_clear_bit(dw, MASK.XFER, dwc->mask);
1181 channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1183 spin_unlock_irqrestore(&dwc->lock, flags);
1185 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1186 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1187 dma_unmap_single(chan2parent(chan), desc->txd.phys,
1188 sizeof(desc->lli), DMA_TO_DEVICE);
1192 dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1195 bool dw_dma_generic_filter(struct dma_chan *chan, void *param)
1197 struct dw_dma *dw = to_dw_dma(chan->device);
1198 static struct dw_dma *last_dw;
1199 static char *last_bus_id;
1203 * dmaengine framework calls this routine for all channels of all dma
1204 * controller, until true is returned. If 'param' bus_id is not
1205 * registered with a dma controller (dw), then there is no need of
1206 * running below function for all channels of dw.
1208 * This block of code does this by saving the parameters of last
1209 * failure. If dw and param are same, i.e. trying on same dw with
1210 * different channel, return false.
1212 if ((last_dw == dw) && (last_bus_id == param))
1216 * - If dw_dma's platform data is not filled with slave info, then all
1217 * dma controllers are fine for transfer.
1218 * - Or if param is NULL
1220 if (!dw->sd || !param)
1223 while (++i < dw->sd_count) {
1224 if (!strcmp(dw->sd[i].bus_id, param)) {
1225 chan->private = &dw->sd[i];
1234 last_bus_id = param;
1237 EXPORT_SYMBOL(dw_dma_generic_filter);
1239 /* --------------------- Cyclic DMA API extensions -------------------- */
1242 * dw_dma_cyclic_start - start the cyclic DMA transfer
1243 * @chan: the DMA channel to start
1245 * Must be called with soft interrupts disabled. Returns zero on success or
1246 * -errno on failure.
1248 int dw_dma_cyclic_start(struct dma_chan *chan)
1250 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1251 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1252 unsigned long flags;
1254 if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1255 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1259 spin_lock_irqsave(&dwc->lock, flags);
1261 /* assert channel is idle */
1262 if (dma_readl(dw, CH_EN) & dwc->mask) {
1263 dev_err(chan2dev(&dwc->chan),
1264 "BUG: Attempted to start non-idle channel\n");
1265 dwc_dump_chan_regs(dwc);
1266 spin_unlock_irqrestore(&dwc->lock, flags);
1270 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1271 dma_writel(dw, CLEAR.XFER, dwc->mask);
1273 /* setup DMAC channel registers */
1274 channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1275 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1276 channel_writel(dwc, CTL_HI, 0);
1278 channel_set_bit(dw, CH_EN, dwc->mask);
1280 spin_unlock_irqrestore(&dwc->lock, flags);
1284 EXPORT_SYMBOL(dw_dma_cyclic_start);
1287 * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1288 * @chan: the DMA channel to stop
1290 * Must be called with soft interrupts disabled.
1292 void dw_dma_cyclic_stop(struct dma_chan *chan)
1294 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1295 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1296 unsigned long flags;
1298 spin_lock_irqsave(&dwc->lock, flags);
1300 dwc_chan_disable(dw, dwc);
1302 spin_unlock_irqrestore(&dwc->lock, flags);
1304 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1307 * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1308 * @chan: the DMA channel to prepare
1309 * @buf_addr: physical DMA address where the buffer starts
1310 * @buf_len: total number of bytes for the entire buffer
1311 * @period_len: number of bytes for each period
1312 * @direction: transfer direction, to or from device
1314 * Must be called before trying to start the transfer. Returns a valid struct
1315 * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1317 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1318 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1319 enum dma_transfer_direction direction)
1321 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1322 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
1323 struct dw_cyclic_desc *cdesc;
1324 struct dw_cyclic_desc *retval = NULL;
1325 struct dw_desc *desc;
1326 struct dw_desc *last = NULL;
1327 unsigned long was_cyclic;
1328 unsigned int reg_width;
1329 unsigned int periods;
1331 unsigned long flags;
1333 spin_lock_irqsave(&dwc->lock, flags);
1335 spin_unlock_irqrestore(&dwc->lock, flags);
1336 dev_dbg(chan2dev(&dwc->chan),
1337 "channel doesn't support LLP transfers\n");
1338 return ERR_PTR(-EINVAL);
1341 if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1342 spin_unlock_irqrestore(&dwc->lock, flags);
1343 dev_dbg(chan2dev(&dwc->chan),
1344 "queue and/or active list are not empty\n");
1345 return ERR_PTR(-EBUSY);
1348 was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1349 spin_unlock_irqrestore(&dwc->lock, flags);
1351 dev_dbg(chan2dev(&dwc->chan),
1352 "channel already prepared for cyclic DMA\n");
1353 return ERR_PTR(-EBUSY);
1356 retval = ERR_PTR(-EINVAL);
1358 if (unlikely(!is_slave_direction(direction)))
1361 if (direction == DMA_MEM_TO_DEV)
1362 reg_width = __ffs(sconfig->dst_addr_width);
1364 reg_width = __ffs(sconfig->src_addr_width);
1366 periods = buf_len / period_len;
1368 /* Check for too big/unaligned periods and unaligned DMA buffer. */
1369 if (period_len > (dwc->block_size << reg_width))
1371 if (unlikely(period_len & ((1 << reg_width) - 1)))
1373 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1376 retval = ERR_PTR(-ENOMEM);
1378 if (periods > NR_DESCS_PER_CHANNEL)
1381 cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1385 cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1389 for (i = 0; i < periods; i++) {
1390 desc = dwc_desc_get(dwc);
1392 goto out_err_desc_get;
1394 switch (direction) {
1395 case DMA_MEM_TO_DEV:
1396 desc->lli.dar = sconfig->dst_addr;
1397 desc->lli.sar = buf_addr + (period_len * i);
1398 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1399 | DWC_CTLL_DST_WIDTH(reg_width)
1400 | DWC_CTLL_SRC_WIDTH(reg_width)
1405 desc->lli.ctllo |= sconfig->device_fc ?
1406 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1407 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1410 case DMA_DEV_TO_MEM:
1411 desc->lli.dar = buf_addr + (period_len * i);
1412 desc->lli.sar = sconfig->src_addr;
1413 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1414 | DWC_CTLL_SRC_WIDTH(reg_width)
1415 | DWC_CTLL_DST_WIDTH(reg_width)
1420 desc->lli.ctllo |= sconfig->device_fc ?
1421 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1422 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1429 desc->lli.ctlhi = (period_len >> reg_width);
1430 cdesc->desc[i] = desc;
1433 last->lli.llp = desc->txd.phys;
1434 dma_sync_single_for_device(chan2parent(chan),
1435 last->txd.phys, sizeof(last->lli),
1442 /* lets make a cyclic list */
1443 last->lli.llp = cdesc->desc[0]->txd.phys;
1444 dma_sync_single_for_device(chan2parent(chan), last->txd.phys,
1445 sizeof(last->lli), DMA_TO_DEVICE);
1447 dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu "
1448 "period %zu periods %d\n", (unsigned long long)buf_addr,
1449 buf_len, period_len, periods);
1451 cdesc->periods = periods;
1458 dwc_desc_put(dwc, cdesc->desc[i]);
1462 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1463 return (struct dw_cyclic_desc *)retval;
1465 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1468 * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1469 * @chan: the DMA channel to free
1471 void dw_dma_cyclic_free(struct dma_chan *chan)
1473 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1474 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1475 struct dw_cyclic_desc *cdesc = dwc->cdesc;
1477 unsigned long flags;
1479 dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1484 spin_lock_irqsave(&dwc->lock, flags);
1486 dwc_chan_disable(dw, dwc);
1488 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1489 dma_writel(dw, CLEAR.XFER, dwc->mask);
1491 spin_unlock_irqrestore(&dwc->lock, flags);
1493 for (i = 0; i < cdesc->periods; i++)
1494 dwc_desc_put(dwc, cdesc->desc[i]);
1499 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1501 EXPORT_SYMBOL(dw_dma_cyclic_free);
1503 /*----------------------------------------------------------------------*/
1505 static void dw_dma_off(struct dw_dma *dw)
1509 dma_writel(dw, CFG, 0);
1511 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1512 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1513 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1514 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1516 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1519 for (i = 0; i < dw->dma.chancnt; i++)
1520 dw->chan[i].initialized = false;
1524 static struct dw_dma_platform_data *
1525 dw_dma_parse_dt(struct platform_device *pdev)
1527 struct device_node *sn, *cn, *np = pdev->dev.of_node;
1528 struct dw_dma_platform_data *pdata;
1529 struct dw_dma_slave *sd;
1533 dev_err(&pdev->dev, "Missing DT data\n");
1537 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1541 if (of_property_read_u32(np, "nr_channels", &pdata->nr_channels))
1544 if (of_property_read_bool(np, "is_private"))
1545 pdata->is_private = true;
1547 if (!of_property_read_u32(np, "chan_allocation_order", &tmp))
1548 pdata->chan_allocation_order = (unsigned char)tmp;
1550 if (!of_property_read_u32(np, "chan_priority", &tmp))
1551 pdata->chan_priority = tmp;
1553 if (!of_property_read_u32(np, "block_size", &tmp))
1554 pdata->block_size = tmp;
1556 if (!of_property_read_u32(np, "nr_masters", &tmp)) {
1560 pdata->nr_masters = tmp;
1563 if (!of_property_read_u32_array(np, "data_width", arr,
1565 for (tmp = 0; tmp < pdata->nr_masters; tmp++)
1566 pdata->data_width[tmp] = arr[tmp];
1568 /* parse slave data */
1569 sn = of_find_node_by_name(np, "slave_info");
1573 /* calculate number of slaves */
1574 tmp = of_get_child_count(sn);
1578 sd = devm_kzalloc(&pdev->dev, sizeof(*sd) * tmp, GFP_KERNEL);
1583 pdata->sd_count = tmp;
1585 for_each_child_of_node(sn, cn) {
1586 sd->dma_dev = &pdev->dev;
1587 of_property_read_string(cn, "bus_id", &sd->bus_id);
1588 of_property_read_u32(cn, "cfg_hi", &sd->cfg_hi);
1589 of_property_read_u32(cn, "cfg_lo", &sd->cfg_lo);
1590 if (!of_property_read_u32(cn, "src_master", &tmp))
1591 sd->src_master = tmp;
1593 if (!of_property_read_u32(cn, "dst_master", &tmp))
1594 sd->dst_master = tmp;
1601 static inline struct dw_dma_platform_data *
1602 dw_dma_parse_dt(struct platform_device *pdev)
1608 static int dw_probe(struct platform_device *pdev)
1610 struct dw_dma_platform_data *pdata;
1611 struct resource *io;
1616 unsigned int dw_params;
1617 unsigned int nr_channels;
1618 unsigned int max_blk_size = 0;
1623 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1627 irq = platform_get_irq(pdev, 0);
1631 regs = devm_request_and_ioremap(&pdev->dev, io);
1635 dw_params = dma_read_byaddr(regs, DW_PARAMS);
1636 autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1638 pdata = dev_get_platdata(&pdev->dev);
1640 pdata = dw_dma_parse_dt(pdev);
1642 if (!pdata && autocfg) {
1643 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1647 /* Fill platform data with the default values */
1648 pdata->is_private = true;
1649 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1650 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1651 } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
1655 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
1657 nr_channels = pdata->nr_channels;
1659 size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan);
1660 dw = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1664 dw->clk = devm_clk_get(&pdev->dev, "hclk");
1665 if (IS_ERR(dw->clk))
1666 return PTR_ERR(dw->clk);
1667 clk_prepare_enable(dw->clk);
1671 dw->sd_count = pdata->sd_count;
1673 /* get hardware configuration parameters */
1675 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1677 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1678 for (i = 0; i < dw->nr_masters; i++) {
1680 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1683 dw->nr_masters = pdata->nr_masters;
1684 memcpy(dw->data_width, pdata->data_width, 4);
1687 /* Calculate all channel mask before DMA setup */
1688 dw->all_chan_mask = (1 << nr_channels) - 1;
1690 /* force dma off, just in case */
1693 /* disable BLOCK interrupts as well */
1694 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1696 err = devm_request_irq(&pdev->dev, irq, dw_dma_interrupt, 0,
1701 platform_set_drvdata(pdev, dw);
1703 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1705 INIT_LIST_HEAD(&dw->dma.channels);
1706 for (i = 0; i < nr_channels; i++) {
1707 struct dw_dma_chan *dwc = &dw->chan[i];
1708 int r = nr_channels - i - 1;
1710 dwc->chan.device = &dw->dma;
1711 dma_cookie_init(&dwc->chan);
1712 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1713 list_add_tail(&dwc->chan.device_node,
1716 list_add(&dwc->chan.device_node, &dw->dma.channels);
1718 /* 7 is highest priority & 0 is lowest. */
1719 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1724 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1725 spin_lock_init(&dwc->lock);
1728 INIT_LIST_HEAD(&dwc->active_list);
1729 INIT_LIST_HEAD(&dwc->queue);
1730 INIT_LIST_HEAD(&dwc->free_list);
1732 channel_clear_bit(dw, CH_EN, dwc->mask);
1736 /* hardware configuration */
1738 unsigned int dwc_params;
1740 dwc_params = dma_read_byaddr(regs + r * sizeof(u32),
1743 /* Decode maximum block size for given channel. The
1744 * stored 4 bit value represents blocks from 0x00 for 3
1745 * up to 0x0a for 4095. */
1747 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1749 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1751 dwc->block_size = pdata->block_size;
1753 /* Check if channel supports multi block transfer */
1754 channel_writel(dwc, LLP, 0xfffffffc);
1756 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1757 channel_writel(dwc, LLP, 0);
1761 /* Clear all interrupts on all channels. */
1762 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1763 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1764 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1765 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1766 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1768 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1769 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1770 if (pdata->is_private)
1771 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1772 dw->dma.dev = &pdev->dev;
1773 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1774 dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1776 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1778 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1779 dw->dma.device_control = dwc_control;
1781 dw->dma.device_tx_status = dwc_tx_status;
1782 dw->dma.device_issue_pending = dwc_issue_pending;
1784 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1786 dev_info(&pdev->dev, "DesignWare DMA Controller, %d channels\n",
1789 dma_async_device_register(&dw->dma);
1794 static int __devexit dw_remove(struct platform_device *pdev)
1796 struct dw_dma *dw = platform_get_drvdata(pdev);
1797 struct dw_dma_chan *dwc, *_dwc;
1800 dma_async_device_unregister(&dw->dma);
1802 tasklet_kill(&dw->tasklet);
1804 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1806 list_del(&dwc->chan.device_node);
1807 channel_clear_bit(dw, CH_EN, dwc->mask);
1813 static void dw_shutdown(struct platform_device *pdev)
1815 struct dw_dma *dw = platform_get_drvdata(pdev);
1818 clk_disable_unprepare(dw->clk);
1821 static int dw_suspend_noirq(struct device *dev)
1823 struct platform_device *pdev = to_platform_device(dev);
1824 struct dw_dma *dw = platform_get_drvdata(pdev);
1827 clk_disable_unprepare(dw->clk);
1832 static int dw_resume_noirq(struct device *dev)
1834 struct platform_device *pdev = to_platform_device(dev);
1835 struct dw_dma *dw = platform_get_drvdata(pdev);
1837 clk_prepare_enable(dw->clk);
1838 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1843 static const struct dev_pm_ops dw_dev_pm_ops = {
1844 .suspend_noirq = dw_suspend_noirq,
1845 .resume_noirq = dw_resume_noirq,
1846 .freeze_noirq = dw_suspend_noirq,
1847 .thaw_noirq = dw_resume_noirq,
1848 .restore_noirq = dw_resume_noirq,
1849 .poweroff_noirq = dw_suspend_noirq,
1853 static const struct of_device_id dw_dma_id_table[] = {
1854 { .compatible = "snps,dma-spear1340" },
1857 MODULE_DEVICE_TABLE(of, dw_dma_id_table);
1860 static struct platform_driver dw_driver = {
1862 .remove = dw_remove,
1863 .shutdown = dw_shutdown,
1866 .pm = &dw_dev_pm_ops,
1867 .of_match_table = of_match_ptr(dw_dma_id_table),
1871 static int __init dw_init(void)
1873 return platform_driver_register(&dw_driver);
1875 subsys_initcall(dw_init);
1877 static void __exit dw_exit(void)
1879 platform_driver_unregister(&dw_driver);
1881 module_exit(dw_exit);
1883 MODULE_LICENSE("GPL v2");
1884 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
1885 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1886 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");