2 * Core driver for the Synopsys DesignWare DMA Controller
4 * Copyright (C) 2007-2008 Atmel Corporation
5 * Copyright (C) 2010-2011 ST Microelectronics
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
26 #include "dw_dmac_regs.h"
27 #include "dmaengine.h"
30 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
31 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
32 * of which use ARM any more). See the "Databook" from Synopsys for
33 * information beyond what licensees probably provide.
35 * The driver has currently been tested only with the Atmel AT32AP7000,
36 * which does not support descriptor writeback.
39 static inline unsigned int dwc_get_dms(struct dw_dma_slave *slave)
41 return slave ? slave->dst_master : 0;
44 static inline unsigned int dwc_get_sms(struct dw_dma_slave *slave)
46 return slave ? slave->src_master : 1;
49 #define DWC_DEFAULT_CTLLO(_chan) ({ \
50 struct dw_dma_slave *__slave = (_chan->private); \
51 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \
52 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
53 int _dms = dwc_get_dms(__slave); \
54 int _sms = dwc_get_sms(__slave); \
55 u8 _smsize = __slave ? _sconfig->src_maxburst : \
57 u8 _dmsize = __slave ? _sconfig->dst_maxburst : \
60 (DWC_CTLL_DST_MSIZE(_dmsize) \
61 | DWC_CTLL_SRC_MSIZE(_smsize) \
64 | DWC_CTLL_DMS(_dms) \
65 | DWC_CTLL_SMS(_sms)); \
69 * Number of descriptors to allocate for each channel. This should be
70 * made configurable somehow; preferably, the clients (at least the
71 * ones using slave transfers) should be able to give us a hint.
73 #define NR_DESCS_PER_CHANNEL 64
75 /*----------------------------------------------------------------------*/
78 * Because we're not relying on writeback from the controller (it may not
79 * even be configured into the core!) we don't need to use dma_pool. These
80 * descriptors -- and associated data -- are cacheable. We do need to make
81 * sure their dcache entries are written back before handing them off to
82 * the controller, though.
85 static struct device *chan2dev(struct dma_chan *chan)
87 return &chan->dev->device;
89 static struct device *chan2parent(struct dma_chan *chan)
91 return chan->dev->device.parent;
94 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
96 return to_dw_desc(dwc->active_list.next);
99 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
101 struct dw_desc *desc, *_desc;
102 struct dw_desc *ret = NULL;
106 spin_lock_irqsave(&dwc->lock, flags);
107 list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
109 if (async_tx_test_ack(&desc->txd)) {
110 list_del(&desc->desc_node);
114 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
116 spin_unlock_irqrestore(&dwc->lock, flags);
118 dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
123 static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc)
125 struct dw_desc *child;
127 list_for_each_entry(child, &desc->tx_list, desc_node)
128 dma_sync_single_for_cpu(chan2parent(&dwc->chan),
129 child->txd.phys, sizeof(child->lli),
131 dma_sync_single_for_cpu(chan2parent(&dwc->chan),
132 desc->txd.phys, sizeof(desc->lli),
137 * Move a descriptor, including any children, to the free list.
138 * `desc' must not be on any lists.
140 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
145 struct dw_desc *child;
147 dwc_sync_desc_for_cpu(dwc, desc);
149 spin_lock_irqsave(&dwc->lock, flags);
150 list_for_each_entry(child, &desc->tx_list, desc_node)
151 dev_vdbg(chan2dev(&dwc->chan),
152 "moving child desc %p to freelist\n",
154 list_splice_init(&desc->tx_list, &dwc->free_list);
155 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
156 list_add(&desc->desc_node, &dwc->free_list);
157 spin_unlock_irqrestore(&dwc->lock, flags);
161 static void dwc_initialize(struct dw_dma_chan *dwc)
163 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
164 struct dw_dma_slave *dws = dwc->chan.private;
165 u32 cfghi = DWC_CFGH_FIFO_MODE;
166 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
168 if (dwc->initialized == true)
173 * We need controller-specific data to set up slave
176 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
179 cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
181 if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV)
182 cfghi = DWC_CFGH_DST_PER(dwc->dma_sconfig.slave_id);
183 else if (dwc->dma_sconfig.direction == DMA_DEV_TO_MEM)
184 cfghi = DWC_CFGH_SRC_PER(dwc->dma_sconfig.slave_id);
187 channel_writel(dwc, CFG_LO, cfglo);
188 channel_writel(dwc, CFG_HI, cfghi);
190 /* Enable interrupts */
191 channel_set_bit(dw, MASK.XFER, dwc->mask);
192 channel_set_bit(dw, MASK.ERROR, dwc->mask);
194 dwc->initialized = true;
197 /*----------------------------------------------------------------------*/
199 static inline unsigned int dwc_fast_fls(unsigned long long v)
202 * We can be a lot more clever here, but this should take care
203 * of the most common optimization.
214 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
216 dev_err(chan2dev(&dwc->chan),
217 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
218 channel_readl(dwc, SAR),
219 channel_readl(dwc, DAR),
220 channel_readl(dwc, LLP),
221 channel_readl(dwc, CTL_HI),
222 channel_readl(dwc, CTL_LO));
225 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
227 channel_clear_bit(dw, CH_EN, dwc->mask);
228 while (dma_readl(dw, CH_EN) & dwc->mask)
232 /*----------------------------------------------------------------------*/
234 /* Perform single block transfer */
235 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
236 struct dw_desc *desc)
238 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
241 /* Software emulation of LLP mode relies on interrupts to continue
242 * multi block transfer. */
243 ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
245 channel_writel(dwc, SAR, desc->lli.sar);
246 channel_writel(dwc, DAR, desc->lli.dar);
247 channel_writel(dwc, CTL_LO, ctllo);
248 channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
249 channel_set_bit(dw, CH_EN, dwc->mask);
252 /* Called with dwc->lock held and bh disabled */
253 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
255 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
256 unsigned long was_soft_llp;
258 /* ASSERT: channel is idle */
259 if (dma_readl(dw, CH_EN) & dwc->mask) {
260 dev_err(chan2dev(&dwc->chan),
261 "BUG: Attempted to start non-idle channel\n");
262 dwc_dump_chan_regs(dwc);
264 /* The tasklet will hopefully advance the queue... */
269 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
272 dev_err(chan2dev(&dwc->chan),
273 "BUG: Attempted to start new LLP transfer "
274 "inside ongoing one\n");
280 dwc->tx_list = &first->tx_list;
281 dwc->tx_node_active = first->tx_list.next;
283 dwc_do_single_block(dwc, first);
290 channel_writel(dwc, LLP, first->txd.phys);
291 channel_writel(dwc, CTL_LO,
292 DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
293 channel_writel(dwc, CTL_HI, 0);
294 channel_set_bit(dw, CH_EN, dwc->mask);
297 /*----------------------------------------------------------------------*/
300 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
301 bool callback_required)
303 dma_async_tx_callback callback = NULL;
305 struct dma_async_tx_descriptor *txd = &desc->txd;
306 struct dw_desc *child;
309 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
311 spin_lock_irqsave(&dwc->lock, flags);
312 dma_cookie_complete(txd);
313 if (callback_required) {
314 callback = txd->callback;
315 param = txd->callback_param;
318 dwc_sync_desc_for_cpu(dwc, desc);
321 list_for_each_entry(child, &desc->tx_list, desc_node)
322 async_tx_ack(&child->txd);
323 async_tx_ack(&desc->txd);
325 list_splice_init(&desc->tx_list, &dwc->free_list);
326 list_move(&desc->desc_node, &dwc->free_list);
328 if (!dwc->chan.private) {
329 struct device *parent = chan2parent(&dwc->chan);
330 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
331 if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
332 dma_unmap_single(parent, desc->lli.dar,
333 desc->len, DMA_FROM_DEVICE);
335 dma_unmap_page(parent, desc->lli.dar,
336 desc->len, DMA_FROM_DEVICE);
338 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
339 if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
340 dma_unmap_single(parent, desc->lli.sar,
341 desc->len, DMA_TO_DEVICE);
343 dma_unmap_page(parent, desc->lli.sar,
344 desc->len, DMA_TO_DEVICE);
348 spin_unlock_irqrestore(&dwc->lock, flags);
350 if (callback_required && callback)
354 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
356 struct dw_desc *desc, *_desc;
360 spin_lock_irqsave(&dwc->lock, flags);
361 if (dma_readl(dw, CH_EN) & dwc->mask) {
362 dev_err(chan2dev(&dwc->chan),
363 "BUG: XFER bit set, but channel not idle!\n");
365 /* Try to continue after resetting the channel... */
366 dwc_chan_disable(dw, dwc);
370 * Submit queued descriptors ASAP, i.e. before we go through
371 * the completed ones.
373 list_splice_init(&dwc->active_list, &list);
374 if (!list_empty(&dwc->queue)) {
375 list_move(dwc->queue.next, &dwc->active_list);
376 dwc_dostart(dwc, dwc_first_active(dwc));
379 spin_unlock_irqrestore(&dwc->lock, flags);
381 list_for_each_entry_safe(desc, _desc, &list, desc_node)
382 dwc_descriptor_complete(dwc, desc, true);
385 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
388 struct dw_desc *desc, *_desc;
389 struct dw_desc *child;
393 spin_lock_irqsave(&dwc->lock, flags);
394 llp = channel_readl(dwc, LLP);
395 status_xfer = dma_readl(dw, RAW.XFER);
397 if (status_xfer & dwc->mask) {
398 /* Everything we've submitted is done */
399 dma_writel(dw, CLEAR.XFER, dwc->mask);
400 spin_unlock_irqrestore(&dwc->lock, flags);
402 dwc_complete_all(dw, dwc);
406 if (list_empty(&dwc->active_list)) {
407 spin_unlock_irqrestore(&dwc->lock, flags);
411 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__,
412 (unsigned long long)llp);
414 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
415 /* check first descriptors addr */
416 if (desc->txd.phys == llp) {
417 spin_unlock_irqrestore(&dwc->lock, flags);
421 /* check first descriptors llp */
422 if (desc->lli.llp == llp) {
423 /* This one is currently in progress */
424 spin_unlock_irqrestore(&dwc->lock, flags);
428 list_for_each_entry(child, &desc->tx_list, desc_node)
429 if (child->lli.llp == llp) {
430 /* Currently in progress */
431 spin_unlock_irqrestore(&dwc->lock, flags);
436 * No descriptors so far seem to be in progress, i.e.
437 * this one must be done.
439 spin_unlock_irqrestore(&dwc->lock, flags);
440 dwc_descriptor_complete(dwc, desc, true);
441 spin_lock_irqsave(&dwc->lock, flags);
444 dev_err(chan2dev(&dwc->chan),
445 "BUG: All descriptors done, but channel not idle!\n");
447 /* Try to continue after resetting the channel... */
448 dwc_chan_disable(dw, dwc);
450 if (!list_empty(&dwc->queue)) {
451 list_move(dwc->queue.next, &dwc->active_list);
452 dwc_dostart(dwc, dwc_first_active(dwc));
454 spin_unlock_irqrestore(&dwc->lock, flags);
457 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
459 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
460 lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
463 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
465 struct dw_desc *bad_desc;
466 struct dw_desc *child;
469 dwc_scan_descriptors(dw, dwc);
471 spin_lock_irqsave(&dwc->lock, flags);
474 * The descriptor currently at the head of the active list is
475 * borked. Since we don't have any way to report errors, we'll
476 * just have to scream loudly and try to carry on.
478 bad_desc = dwc_first_active(dwc);
479 list_del_init(&bad_desc->desc_node);
480 list_move(dwc->queue.next, dwc->active_list.prev);
482 /* Clear the error flag and try to restart the controller */
483 dma_writel(dw, CLEAR.ERROR, dwc->mask);
484 if (!list_empty(&dwc->active_list))
485 dwc_dostart(dwc, dwc_first_active(dwc));
488 * WARN may seem harsh, but since this only happens
489 * when someone submits a bad physical address in a
490 * descriptor, we should consider ourselves lucky that the
491 * controller flagged an error instead of scribbling over
492 * random memory locations.
494 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
495 " cookie: %d\n", bad_desc->txd.cookie);
496 dwc_dump_lli(dwc, &bad_desc->lli);
497 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
498 dwc_dump_lli(dwc, &child->lli);
500 spin_unlock_irqrestore(&dwc->lock, flags);
502 /* Pretend the descriptor completed successfully */
503 dwc_descriptor_complete(dwc, bad_desc, true);
506 /* --------------------- Cyclic DMA API extensions -------------------- */
508 inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
510 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
511 return channel_readl(dwc, SAR);
513 EXPORT_SYMBOL(dw_dma_get_src_addr);
515 inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
517 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
518 return channel_readl(dwc, DAR);
520 EXPORT_SYMBOL(dw_dma_get_dst_addr);
522 /* called with dwc->lock held and all DMAC interrupts disabled */
523 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
524 u32 status_err, u32 status_xfer)
529 void (*callback)(void *param);
530 void *callback_param;
532 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
533 channel_readl(dwc, LLP));
535 callback = dwc->cdesc->period_callback;
536 callback_param = dwc->cdesc->period_callback_param;
539 callback(callback_param);
543 * Error and transfer complete are highly unlikely, and will most
544 * likely be due to a configuration error by the user.
546 if (unlikely(status_err & dwc->mask) ||
547 unlikely(status_xfer & dwc->mask)) {
550 dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s "
551 "interrupt, stopping DMA transfer\n",
552 status_xfer ? "xfer" : "error");
554 spin_lock_irqsave(&dwc->lock, flags);
556 dwc_dump_chan_regs(dwc);
558 dwc_chan_disable(dw, dwc);
560 /* make sure DMA does not restart by loading a new list */
561 channel_writel(dwc, LLP, 0);
562 channel_writel(dwc, CTL_LO, 0);
563 channel_writel(dwc, CTL_HI, 0);
565 dma_writel(dw, CLEAR.ERROR, dwc->mask);
566 dma_writel(dw, CLEAR.XFER, dwc->mask);
568 for (i = 0; i < dwc->cdesc->periods; i++)
569 dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
571 spin_unlock_irqrestore(&dwc->lock, flags);
575 /* ------------------------------------------------------------------------- */
577 static void dw_dma_tasklet(unsigned long data)
579 struct dw_dma *dw = (struct dw_dma *)data;
580 struct dw_dma_chan *dwc;
585 status_xfer = dma_readl(dw, RAW.XFER);
586 status_err = dma_readl(dw, RAW.ERROR);
588 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
590 for (i = 0; i < dw->dma.chancnt; i++) {
592 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
593 dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
594 else if (status_err & (1 << i))
595 dwc_handle_error(dw, dwc);
596 else if (status_xfer & (1 << i)) {
599 spin_lock_irqsave(&dwc->lock, flags);
600 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
601 if (dwc->tx_node_active != dwc->tx_list) {
602 struct dw_desc *desc =
603 to_dw_desc(dwc->tx_node_active);
605 dma_writel(dw, CLEAR.XFER, dwc->mask);
607 /* move pointer to next descriptor */
608 dwc->tx_node_active =
609 dwc->tx_node_active->next;
611 dwc_do_single_block(dwc, desc);
613 spin_unlock_irqrestore(&dwc->lock, flags);
616 /* we are done here */
617 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
620 spin_unlock_irqrestore(&dwc->lock, flags);
622 dwc_scan_descriptors(dw, dwc);
627 * Re-enable interrupts.
629 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
630 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
633 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
635 struct dw_dma *dw = dev_id;
638 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__,
639 dma_readl(dw, STATUS_INT));
642 * Just disable the interrupts. We'll turn them back on in the
645 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
646 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
648 status = dma_readl(dw, STATUS_INT);
651 "BUG: Unexpected interrupts pending: 0x%x\n",
655 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
656 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
657 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
658 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
661 tasklet_schedule(&dw->tasklet);
666 /*----------------------------------------------------------------------*/
668 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
670 struct dw_desc *desc = txd_to_dw_desc(tx);
671 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
675 spin_lock_irqsave(&dwc->lock, flags);
676 cookie = dma_cookie_assign(tx);
679 * REVISIT: We should attempt to chain as many descriptors as
680 * possible, perhaps even appending to those already submitted
681 * for DMA. But this is hard to do in a race-free manner.
683 if (list_empty(&dwc->active_list)) {
684 dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__,
686 list_add_tail(&desc->desc_node, &dwc->active_list);
687 dwc_dostart(dwc, dwc_first_active(dwc));
689 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__,
692 list_add_tail(&desc->desc_node, &dwc->queue);
695 spin_unlock_irqrestore(&dwc->lock, flags);
700 static struct dma_async_tx_descriptor *
701 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
702 size_t len, unsigned long flags)
704 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
705 struct dw_dma_slave *dws = chan->private;
706 struct dw_desc *desc;
707 struct dw_desc *first;
708 struct dw_desc *prev;
711 unsigned int src_width;
712 unsigned int dst_width;
713 unsigned int data_width;
716 dev_vdbg(chan2dev(chan),
717 "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__,
718 (unsigned long long)dest, (unsigned long long)src,
721 if (unlikely(!len)) {
722 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
726 data_width = min_t(unsigned int, dwc->dw->data_width[dwc_get_sms(dws)],
727 dwc->dw->data_width[dwc_get_dms(dws)]);
729 src_width = dst_width = min_t(unsigned int, data_width,
730 dwc_fast_fls(src | dest | len));
732 ctllo = DWC_DEFAULT_CTLLO(chan)
733 | DWC_CTLL_DST_WIDTH(dst_width)
734 | DWC_CTLL_SRC_WIDTH(src_width)
740 for (offset = 0; offset < len; offset += xfer_count << src_width) {
741 xfer_count = min_t(size_t, (len - offset) >> src_width,
744 desc = dwc_desc_get(dwc);
748 desc->lli.sar = src + offset;
749 desc->lli.dar = dest + offset;
750 desc->lli.ctllo = ctllo;
751 desc->lli.ctlhi = xfer_count;
756 prev->lli.llp = desc->txd.phys;
757 dma_sync_single_for_device(chan2parent(chan),
758 prev->txd.phys, sizeof(prev->lli),
760 list_add_tail(&desc->desc_node,
767 if (flags & DMA_PREP_INTERRUPT)
768 /* Trigger interrupt after last block */
769 prev->lli.ctllo |= DWC_CTLL_INT_EN;
772 dma_sync_single_for_device(chan2parent(chan),
773 prev->txd.phys, sizeof(prev->lli),
776 first->txd.flags = flags;
782 dwc_desc_put(dwc, first);
786 static struct dma_async_tx_descriptor *
787 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
788 unsigned int sg_len, enum dma_transfer_direction direction,
789 unsigned long flags, void *context)
791 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
792 struct dw_dma_slave *dws = chan->private;
793 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
794 struct dw_desc *prev;
795 struct dw_desc *first;
798 unsigned int reg_width;
799 unsigned int mem_width;
800 unsigned int data_width;
802 struct scatterlist *sg;
803 size_t total_len = 0;
805 dev_vdbg(chan2dev(chan), "%s\n", __func__);
807 if (unlikely(!dws || !sg_len))
814 reg_width = __fls(sconfig->dst_addr_width);
815 reg = sconfig->dst_addr;
816 ctllo = (DWC_DEFAULT_CTLLO(chan)
817 | DWC_CTLL_DST_WIDTH(reg_width)
821 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
822 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
824 data_width = dwc->dw->data_width[dwc_get_sms(dws)];
826 for_each_sg(sgl, sg, sg_len, i) {
827 struct dw_desc *desc;
830 mem = sg_dma_address(sg);
831 len = sg_dma_len(sg);
833 mem_width = min_t(unsigned int,
834 data_width, dwc_fast_fls(mem | len));
836 slave_sg_todev_fill_desc:
837 desc = dwc_desc_get(dwc);
839 dev_err(chan2dev(chan),
840 "not enough descriptors available\n");
846 desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
847 if ((len >> mem_width) > dwc->block_size) {
848 dlen = dwc->block_size << mem_width;
856 desc->lli.ctlhi = dlen >> mem_width;
861 prev->lli.llp = desc->txd.phys;
862 dma_sync_single_for_device(chan2parent(chan),
866 list_add_tail(&desc->desc_node,
873 goto slave_sg_todev_fill_desc;
877 reg_width = __fls(sconfig->src_addr_width);
878 reg = sconfig->src_addr;
879 ctllo = (DWC_DEFAULT_CTLLO(chan)
880 | DWC_CTLL_SRC_WIDTH(reg_width)
884 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
885 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
887 data_width = dwc->dw->data_width[dwc_get_dms(dws)];
889 for_each_sg(sgl, sg, sg_len, i) {
890 struct dw_desc *desc;
893 mem = sg_dma_address(sg);
894 len = sg_dma_len(sg);
896 mem_width = min_t(unsigned int,
897 data_width, dwc_fast_fls(mem | len));
899 slave_sg_fromdev_fill_desc:
900 desc = dwc_desc_get(dwc);
902 dev_err(chan2dev(chan),
903 "not enough descriptors available\n");
909 desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
910 if ((len >> reg_width) > dwc->block_size) {
911 dlen = dwc->block_size << reg_width;
918 desc->lli.ctlhi = dlen >> reg_width;
923 prev->lli.llp = desc->txd.phys;
924 dma_sync_single_for_device(chan2parent(chan),
928 list_add_tail(&desc->desc_node,
935 goto slave_sg_fromdev_fill_desc;
942 if (flags & DMA_PREP_INTERRUPT)
943 /* Trigger interrupt after last block */
944 prev->lli.ctllo |= DWC_CTLL_INT_EN;
947 dma_sync_single_for_device(chan2parent(chan),
948 prev->txd.phys, sizeof(prev->lli),
951 first->len = total_len;
956 dwc_desc_put(dwc, first);
961 * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
962 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
964 * NOTE: burst size 2 is not supported by controller.
966 * This can be done by finding least significant bit set: n & (n - 1)
968 static inline void convert_burst(u32 *maxburst)
971 *maxburst = fls(*maxburst) - 2;
977 set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
979 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
981 /* Check if it is chan is configured for slave transfers */
985 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
987 convert_burst(&dwc->dma_sconfig.src_maxburst);
988 convert_burst(&dwc->dma_sconfig.dst_maxburst);
993 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
996 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
997 struct dw_dma *dw = to_dw_dma(chan->device);
998 struct dw_desc *desc, *_desc;
1003 if (cmd == DMA_PAUSE) {
1004 spin_lock_irqsave(&dwc->lock, flags);
1006 cfglo = channel_readl(dwc, CFG_LO);
1007 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
1008 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY))
1012 spin_unlock_irqrestore(&dwc->lock, flags);
1013 } else if (cmd == DMA_RESUME) {
1017 spin_lock_irqsave(&dwc->lock, flags);
1019 cfglo = channel_readl(dwc, CFG_LO);
1020 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
1021 dwc->paused = false;
1023 spin_unlock_irqrestore(&dwc->lock, flags);
1024 } else if (cmd == DMA_TERMINATE_ALL) {
1025 spin_lock_irqsave(&dwc->lock, flags);
1027 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1029 dwc_chan_disable(dw, dwc);
1031 dwc->paused = false;
1033 /* active_list entries will end up before queued entries */
1034 list_splice_init(&dwc->queue, &list);
1035 list_splice_init(&dwc->active_list, &list);
1037 spin_unlock_irqrestore(&dwc->lock, flags);
1039 /* Flush all pending and queued descriptors */
1040 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1041 dwc_descriptor_complete(dwc, desc, false);
1042 } else if (cmd == DMA_SLAVE_CONFIG) {
1043 return set_runtime_config(chan, (struct dma_slave_config *)arg);
1051 static enum dma_status
1052 dwc_tx_status(struct dma_chan *chan,
1053 dma_cookie_t cookie,
1054 struct dma_tx_state *txstate)
1056 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1057 enum dma_status ret;
1059 ret = dma_cookie_status(chan, cookie, txstate);
1060 if (ret != DMA_SUCCESS) {
1061 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1063 ret = dma_cookie_status(chan, cookie, txstate);
1066 if (ret != DMA_SUCCESS)
1067 dma_set_residue(txstate, dwc_first_active(dwc)->len);
1075 static void dwc_issue_pending(struct dma_chan *chan)
1077 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1079 if (!list_empty(&dwc->queue))
1080 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1083 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1085 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1086 struct dw_dma *dw = to_dw_dma(chan->device);
1087 struct dw_desc *desc;
1089 unsigned long flags;
1091 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1093 /* ASSERT: channel is idle */
1094 if (dma_readl(dw, CH_EN) & dwc->mask) {
1095 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1099 dma_cookie_init(chan);
1102 * NOTE: some controllers may have additional features that we
1103 * need to initialize here, like "scatter-gather" (which
1104 * doesn't mean what you think it means), and status writeback.
1107 spin_lock_irqsave(&dwc->lock, flags);
1108 i = dwc->descs_allocated;
1109 while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1110 spin_unlock_irqrestore(&dwc->lock, flags);
1112 desc = kzalloc(sizeof(struct dw_desc), GFP_KERNEL);
1114 dev_info(chan2dev(chan),
1115 "only allocated %d descriptors\n", i);
1116 spin_lock_irqsave(&dwc->lock, flags);
1120 INIT_LIST_HEAD(&desc->tx_list);
1121 dma_async_tx_descriptor_init(&desc->txd, chan);
1122 desc->txd.tx_submit = dwc_tx_submit;
1123 desc->txd.flags = DMA_CTRL_ACK;
1124 desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli,
1125 sizeof(desc->lli), DMA_TO_DEVICE);
1126 dwc_desc_put(dwc, desc);
1128 spin_lock_irqsave(&dwc->lock, flags);
1129 i = ++dwc->descs_allocated;
1132 spin_unlock_irqrestore(&dwc->lock, flags);
1134 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1139 static void dwc_free_chan_resources(struct dma_chan *chan)
1141 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1142 struct dw_dma *dw = to_dw_dma(chan->device);
1143 struct dw_desc *desc, *_desc;
1144 unsigned long flags;
1147 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1148 dwc->descs_allocated);
1150 /* ASSERT: channel is idle */
1151 BUG_ON(!list_empty(&dwc->active_list));
1152 BUG_ON(!list_empty(&dwc->queue));
1153 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1155 spin_lock_irqsave(&dwc->lock, flags);
1156 list_splice_init(&dwc->free_list, &list);
1157 dwc->descs_allocated = 0;
1158 dwc->initialized = false;
1160 /* Disable interrupts */
1161 channel_clear_bit(dw, MASK.XFER, dwc->mask);
1162 channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1164 spin_unlock_irqrestore(&dwc->lock, flags);
1166 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1167 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1168 dma_unmap_single(chan2parent(chan), desc->txd.phys,
1169 sizeof(desc->lli), DMA_TO_DEVICE);
1173 dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1176 bool dw_dma_generic_filter(struct dma_chan *chan, void *param)
1178 struct dw_dma *dw = to_dw_dma(chan->device);
1179 static struct dw_dma *last_dw;
1180 static char *last_bus_id;
1184 * dmaengine framework calls this routine for all channels of all dma
1185 * controller, until true is returned. If 'param' bus_id is not
1186 * registered with a dma controller (dw), then there is no need of
1187 * running below function for all channels of dw.
1189 * This block of code does this by saving the parameters of last
1190 * failure. If dw and param are same, i.e. trying on same dw with
1191 * different channel, return false.
1193 if ((last_dw == dw) && (last_bus_id == param))
1197 * - If dw_dma's platform data is not filled with slave info, then all
1198 * dma controllers are fine for transfer.
1199 * - Or if param is NULL
1201 if (!dw->sd || !param)
1204 while (++i < dw->sd_count) {
1205 if (!strcmp(dw->sd[i].bus_id, param)) {
1206 chan->private = &dw->sd[i];
1215 last_bus_id = param;
1218 EXPORT_SYMBOL(dw_dma_generic_filter);
1220 /* --------------------- Cyclic DMA API extensions -------------------- */
1223 * dw_dma_cyclic_start - start the cyclic DMA transfer
1224 * @chan: the DMA channel to start
1226 * Must be called with soft interrupts disabled. Returns zero on success or
1227 * -errno on failure.
1229 int dw_dma_cyclic_start(struct dma_chan *chan)
1231 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1232 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1233 unsigned long flags;
1235 if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1236 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1240 spin_lock_irqsave(&dwc->lock, flags);
1242 /* assert channel is idle */
1243 if (dma_readl(dw, CH_EN) & dwc->mask) {
1244 dev_err(chan2dev(&dwc->chan),
1245 "BUG: Attempted to start non-idle channel\n");
1246 dwc_dump_chan_regs(dwc);
1247 spin_unlock_irqrestore(&dwc->lock, flags);
1251 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1252 dma_writel(dw, CLEAR.XFER, dwc->mask);
1254 /* setup DMAC channel registers */
1255 channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1256 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1257 channel_writel(dwc, CTL_HI, 0);
1259 channel_set_bit(dw, CH_EN, dwc->mask);
1261 spin_unlock_irqrestore(&dwc->lock, flags);
1265 EXPORT_SYMBOL(dw_dma_cyclic_start);
1268 * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1269 * @chan: the DMA channel to stop
1271 * Must be called with soft interrupts disabled.
1273 void dw_dma_cyclic_stop(struct dma_chan *chan)
1275 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1276 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1277 unsigned long flags;
1279 spin_lock_irqsave(&dwc->lock, flags);
1281 dwc_chan_disable(dw, dwc);
1283 spin_unlock_irqrestore(&dwc->lock, flags);
1285 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1288 * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1289 * @chan: the DMA channel to prepare
1290 * @buf_addr: physical DMA address where the buffer starts
1291 * @buf_len: total number of bytes for the entire buffer
1292 * @period_len: number of bytes for each period
1293 * @direction: transfer direction, to or from device
1295 * Must be called before trying to start the transfer. Returns a valid struct
1296 * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1298 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1299 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1300 enum dma_transfer_direction direction)
1302 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1303 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
1304 struct dw_cyclic_desc *cdesc;
1305 struct dw_cyclic_desc *retval = NULL;
1306 struct dw_desc *desc;
1307 struct dw_desc *last = NULL;
1308 unsigned long was_cyclic;
1309 unsigned int reg_width;
1310 unsigned int periods;
1312 unsigned long flags;
1314 spin_lock_irqsave(&dwc->lock, flags);
1316 spin_unlock_irqrestore(&dwc->lock, flags);
1317 dev_dbg(chan2dev(&dwc->chan),
1318 "channel doesn't support LLP transfers\n");
1319 return ERR_PTR(-EINVAL);
1322 if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1323 spin_unlock_irqrestore(&dwc->lock, flags);
1324 dev_dbg(chan2dev(&dwc->chan),
1325 "queue and/or active list are not empty\n");
1326 return ERR_PTR(-EBUSY);
1329 was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1330 spin_unlock_irqrestore(&dwc->lock, flags);
1332 dev_dbg(chan2dev(&dwc->chan),
1333 "channel already prepared for cyclic DMA\n");
1334 return ERR_PTR(-EBUSY);
1337 retval = ERR_PTR(-EINVAL);
1339 if (direction == DMA_MEM_TO_DEV)
1340 reg_width = __ffs(sconfig->dst_addr_width);
1342 reg_width = __ffs(sconfig->src_addr_width);
1344 periods = buf_len / period_len;
1346 /* Check for too big/unaligned periods and unaligned DMA buffer. */
1347 if (period_len > (dwc->block_size << reg_width))
1349 if (unlikely(period_len & ((1 << reg_width) - 1)))
1351 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1353 if (unlikely(!(direction & (DMA_MEM_TO_DEV | DMA_DEV_TO_MEM))))
1356 retval = ERR_PTR(-ENOMEM);
1358 if (periods > NR_DESCS_PER_CHANNEL)
1361 cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1365 cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1369 for (i = 0; i < periods; i++) {
1370 desc = dwc_desc_get(dwc);
1372 goto out_err_desc_get;
1374 switch (direction) {
1375 case DMA_MEM_TO_DEV:
1376 desc->lli.dar = sconfig->dst_addr;
1377 desc->lli.sar = buf_addr + (period_len * i);
1378 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1379 | DWC_CTLL_DST_WIDTH(reg_width)
1380 | DWC_CTLL_SRC_WIDTH(reg_width)
1385 desc->lli.ctllo |= sconfig->device_fc ?
1386 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1387 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1390 case DMA_DEV_TO_MEM:
1391 desc->lli.dar = buf_addr + (period_len * i);
1392 desc->lli.sar = sconfig->src_addr;
1393 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1394 | DWC_CTLL_SRC_WIDTH(reg_width)
1395 | DWC_CTLL_DST_WIDTH(reg_width)
1400 desc->lli.ctllo |= sconfig->device_fc ?
1401 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1402 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1409 desc->lli.ctlhi = (period_len >> reg_width);
1410 cdesc->desc[i] = desc;
1413 last->lli.llp = desc->txd.phys;
1414 dma_sync_single_for_device(chan2parent(chan),
1415 last->txd.phys, sizeof(last->lli),
1422 /* lets make a cyclic list */
1423 last->lli.llp = cdesc->desc[0]->txd.phys;
1424 dma_sync_single_for_device(chan2parent(chan), last->txd.phys,
1425 sizeof(last->lli), DMA_TO_DEVICE);
1427 dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu "
1428 "period %zu periods %d\n", (unsigned long long)buf_addr,
1429 buf_len, period_len, periods);
1431 cdesc->periods = periods;
1438 dwc_desc_put(dwc, cdesc->desc[i]);
1442 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1443 return (struct dw_cyclic_desc *)retval;
1445 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1448 * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1449 * @chan: the DMA channel to free
1451 void dw_dma_cyclic_free(struct dma_chan *chan)
1453 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1454 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1455 struct dw_cyclic_desc *cdesc = dwc->cdesc;
1457 unsigned long flags;
1459 dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1464 spin_lock_irqsave(&dwc->lock, flags);
1466 dwc_chan_disable(dw, dwc);
1468 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1469 dma_writel(dw, CLEAR.XFER, dwc->mask);
1471 spin_unlock_irqrestore(&dwc->lock, flags);
1473 for (i = 0; i < cdesc->periods; i++)
1474 dwc_desc_put(dwc, cdesc->desc[i]);
1479 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1481 EXPORT_SYMBOL(dw_dma_cyclic_free);
1483 /*----------------------------------------------------------------------*/
1485 static void dw_dma_off(struct dw_dma *dw)
1489 dma_writel(dw, CFG, 0);
1491 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1492 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1493 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1494 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1496 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1499 for (i = 0; i < dw->dma.chancnt; i++)
1500 dw->chan[i].initialized = false;
1504 static struct dw_dma_platform_data *
1505 dw_dma_parse_dt(struct platform_device *pdev)
1507 struct device_node *sn, *cn, *np = pdev->dev.of_node;
1508 struct dw_dma_platform_data *pdata;
1509 struct dw_dma_slave *sd;
1513 dev_err(&pdev->dev, "Missing DT data\n");
1517 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1521 if (of_property_read_u32(np, "nr_channels", &pdata->nr_channels))
1524 if (of_property_read_bool(np, "is_private"))
1525 pdata->is_private = true;
1527 if (!of_property_read_u32(np, "chan_allocation_order", &tmp))
1528 pdata->chan_allocation_order = (unsigned char)tmp;
1530 if (!of_property_read_u32(np, "chan_priority", &tmp))
1531 pdata->chan_priority = tmp;
1533 if (!of_property_read_u32(np, "block_size", &tmp))
1534 pdata->block_size = tmp;
1536 if (!of_property_read_u32(np, "nr_masters", &tmp)) {
1540 pdata->nr_masters = tmp;
1543 if (!of_property_read_u32_array(np, "data_width", arr,
1545 for (tmp = 0; tmp < pdata->nr_masters; tmp++)
1546 pdata->data_width[tmp] = arr[tmp];
1548 /* parse slave data */
1549 sn = of_find_node_by_name(np, "slave_info");
1553 /* calculate number of slaves */
1554 tmp = of_get_child_count(sn);
1558 sd = devm_kzalloc(&pdev->dev, sizeof(*sd) * tmp, GFP_KERNEL);
1563 pdata->sd_count = tmp;
1565 for_each_child_of_node(sn, cn) {
1566 sd->dma_dev = &pdev->dev;
1567 of_property_read_string(cn, "bus_id", &sd->bus_id);
1568 of_property_read_u32(cn, "cfg_hi", &sd->cfg_hi);
1569 of_property_read_u32(cn, "cfg_lo", &sd->cfg_lo);
1570 if (!of_property_read_u32(cn, "src_master", &tmp))
1571 sd->src_master = tmp;
1573 if (!of_property_read_u32(cn, "dst_master", &tmp))
1574 sd->dst_master = tmp;
1581 static inline struct dw_dma_platform_data *
1582 dw_dma_parse_dt(struct platform_device *pdev)
1588 static int dw_probe(struct platform_device *pdev)
1590 struct dw_dma_platform_data *pdata;
1591 struct resource *io;
1596 unsigned int dw_params;
1597 unsigned int nr_channels;
1598 unsigned int max_blk_size = 0;
1603 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1607 irq = platform_get_irq(pdev, 0);
1611 regs = devm_request_and_ioremap(&pdev->dev, io);
1615 dw_params = dma_read_byaddr(regs, DW_PARAMS);
1616 autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1618 pdata = dev_get_platdata(&pdev->dev);
1620 pdata = dw_dma_parse_dt(pdev);
1622 if (!pdata && autocfg) {
1623 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1627 /* Fill platform data with the default values */
1628 pdata->is_private = true;
1629 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1630 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1631 } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
1635 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
1637 nr_channels = pdata->nr_channels;
1639 size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan);
1640 dw = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1644 dw->clk = devm_clk_get(&pdev->dev, "hclk");
1645 if (IS_ERR(dw->clk))
1646 return PTR_ERR(dw->clk);
1647 clk_prepare_enable(dw->clk);
1651 dw->sd_count = pdata->sd_count;
1653 /* get hardware configuration parameters */
1655 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1657 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1658 for (i = 0; i < dw->nr_masters; i++) {
1660 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1663 dw->nr_masters = pdata->nr_masters;
1664 memcpy(dw->data_width, pdata->data_width, 4);
1667 /* Calculate all channel mask before DMA setup */
1668 dw->all_chan_mask = (1 << nr_channels) - 1;
1670 /* force dma off, just in case */
1673 /* disable BLOCK interrupts as well */
1674 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1676 err = devm_request_irq(&pdev->dev, irq, dw_dma_interrupt, 0,
1681 platform_set_drvdata(pdev, dw);
1683 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1685 INIT_LIST_HEAD(&dw->dma.channels);
1686 for (i = 0; i < nr_channels; i++) {
1687 struct dw_dma_chan *dwc = &dw->chan[i];
1688 int r = nr_channels - i - 1;
1690 dwc->chan.device = &dw->dma;
1691 dma_cookie_init(&dwc->chan);
1692 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1693 list_add_tail(&dwc->chan.device_node,
1696 list_add(&dwc->chan.device_node, &dw->dma.channels);
1698 /* 7 is highest priority & 0 is lowest. */
1699 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1704 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1705 spin_lock_init(&dwc->lock);
1708 INIT_LIST_HEAD(&dwc->active_list);
1709 INIT_LIST_HEAD(&dwc->queue);
1710 INIT_LIST_HEAD(&dwc->free_list);
1712 channel_clear_bit(dw, CH_EN, dwc->mask);
1716 /* hardware configuration */
1718 unsigned int dwc_params;
1720 dwc_params = dma_read_byaddr(regs + r * sizeof(u32),
1723 /* Decode maximum block size for given channel. The
1724 * stored 4 bit value represents blocks from 0x00 for 3
1725 * up to 0x0a for 4095. */
1727 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1729 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1731 dwc->block_size = pdata->block_size;
1733 /* Check if channel supports multi block transfer */
1734 channel_writel(dwc, LLP, 0xfffffffc);
1736 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1737 channel_writel(dwc, LLP, 0);
1741 /* Clear all interrupts on all channels. */
1742 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1743 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1744 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1745 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1746 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1748 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1749 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1750 if (pdata->is_private)
1751 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1752 dw->dma.dev = &pdev->dev;
1753 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1754 dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1756 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1758 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1759 dw->dma.device_control = dwc_control;
1761 dw->dma.device_tx_status = dwc_tx_status;
1762 dw->dma.device_issue_pending = dwc_issue_pending;
1764 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1766 dev_info(&pdev->dev, "DesignWare DMA Controller, %d channels\n",
1769 dma_async_device_register(&dw->dma);
1774 static int __devexit dw_remove(struct platform_device *pdev)
1776 struct dw_dma *dw = platform_get_drvdata(pdev);
1777 struct dw_dma_chan *dwc, *_dwc;
1780 dma_async_device_unregister(&dw->dma);
1782 tasklet_kill(&dw->tasklet);
1784 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1786 list_del(&dwc->chan.device_node);
1787 channel_clear_bit(dw, CH_EN, dwc->mask);
1793 static void dw_shutdown(struct platform_device *pdev)
1795 struct dw_dma *dw = platform_get_drvdata(pdev);
1798 clk_disable_unprepare(dw->clk);
1801 static int dw_suspend_noirq(struct device *dev)
1803 struct platform_device *pdev = to_platform_device(dev);
1804 struct dw_dma *dw = platform_get_drvdata(pdev);
1807 clk_disable_unprepare(dw->clk);
1812 static int dw_resume_noirq(struct device *dev)
1814 struct platform_device *pdev = to_platform_device(dev);
1815 struct dw_dma *dw = platform_get_drvdata(pdev);
1817 clk_prepare_enable(dw->clk);
1818 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1823 static const struct dev_pm_ops dw_dev_pm_ops = {
1824 .suspend_noirq = dw_suspend_noirq,
1825 .resume_noirq = dw_resume_noirq,
1826 .freeze_noirq = dw_suspend_noirq,
1827 .thaw_noirq = dw_resume_noirq,
1828 .restore_noirq = dw_resume_noirq,
1829 .poweroff_noirq = dw_suspend_noirq,
1833 static const struct of_device_id dw_dma_id_table[] = {
1834 { .compatible = "snps,dma-spear1340" },
1837 MODULE_DEVICE_TABLE(of, dw_dma_id_table);
1840 static struct platform_driver dw_driver = {
1841 .remove = dw_remove,
1842 .shutdown = dw_shutdown,
1845 .pm = &dw_dev_pm_ops,
1846 .of_match_table = of_match_ptr(dw_dma_id_table),
1850 static int __init dw_init(void)
1852 return platform_driver_probe(&dw_driver, dw_probe);
1854 subsys_initcall(dw_init);
1856 static void __exit dw_exit(void)
1858 platform_driver_unregister(&dw_driver);
1860 module_exit(dw_exit);
1862 MODULE_LICENSE("GPL v2");
1863 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
1864 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1865 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");