drivers/dma/dw_dmac.c

   1 /*
   2  * Core driver for the Synopsys DesignWare DMA Controller
   3  *
   4  * Copyright (C) 2007-2008 Atmel Corporation
   5  * Copyright (C) 2010-2011 ST Microelectronics
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/init.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/of.h>
  21 #include <linux/mm.h>
  22 #include <linux/module.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/slab.h>
  25
  26 #include "dw_dmac_regs.h"
  27 #include "dmaengine.h"
  28
  29 /*
  30  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
  31  * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
  32  * of which use ARM any more).  See the "Databook" from Synopsys for
  33  * information beyond what licensees probably provide.
  34  *
  35  * The driver has currently been tested only with the Atmel AT32AP7000,
  36  * which does not support descriptor writeback.
  37  */
  38
  39 static inline unsigned int dwc_get_dms(struct dw_dma_slave *slave)
  40 {
  41         return slave ? slave->dst_master : 0;
  42 }
  43
  44 static inline unsigned int dwc_get_sms(struct dw_dma_slave *slave)
  45 {
  46         return slave ? slave->src_master : 1;
  47 }
  48
  49 #define DWC_DEFAULT_CTLLO(_chan) ({                             \
  50                 struct dw_dma_slave *__slave = (_chan->private);        \
  51                 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan);       \
  52                 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
  53                 int _dms = dwc_get_dms(__slave);                \
  54                 int _sms = dwc_get_sms(__slave);                \
  55                 u8 _smsize = __slave ? _sconfig->src_maxburst : \
  56                         DW_DMA_MSIZE_16;                        \
  57                 u8 _dmsize = __slave ? _sconfig->dst_maxburst : \
  58                         DW_DMA_MSIZE_16;                        \
  59                                                                 \
  60                 (DWC_CTLL_DST_MSIZE(_dmsize)                    \
  61                  | DWC_CTLL_SRC_MSIZE(_smsize)                  \
  62                  | DWC_CTLL_LLP_D_EN                            \
  63                  | DWC_CTLL_LLP_S_EN                            \
  64                  | DWC_CTLL_DMS(_dms)                           \
  65                  | DWC_CTLL_SMS(_sms));                         \
  66         })
  67
  68 /*
  69  * Number of descriptors to allocate for each channel. This should be
  70  * made configurable somehow; preferably, the clients (at least the
  71  * ones using slave transfers) should be able to give us a hint.
  72  */
  73 #define NR_DESCS_PER_CHANNEL    64
  74
  75 /*----------------------------------------------------------------------*/
  76
  77 /*
  78  * Because we're not relying on writeback from the controller (it may not
  79  * even be configured into the core!) we don't need to use dma_pool.  These
  80  * descriptors -- and associated data -- are cacheable.  We do need to make
  81  * sure their dcache entries are written back before handing them off to
  82  * the controller, though.
  83  */
  84
  85 static struct device *chan2dev(struct dma_chan *chan)
  86 {
  87         return &chan->dev->device;
  88 }
  89 static struct device *chan2parent(struct dma_chan *chan)
  90 {
  91         return chan->dev->device.parent;
  92 }
  93
  94 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
  95 {
  96         return to_dw_desc(dwc->active_list.next);
  97 }
  98
  99 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
 100 {
 101         struct dw_desc *desc, *_desc;
 102         struct dw_desc *ret = NULL;
 103         unsigned int i = 0;
 104         unsigned long flags;
 105
 106         spin_lock_irqsave(&dwc->lock, flags);
 107         list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
 108                 i++;
 109                 if (async_tx_test_ack(&desc->txd)) {
 110                         list_del(&desc->desc_node);
 111                         ret = desc;
 112                         break;
 113                 }
 114                 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
 115         }
 116         spin_unlock_irqrestore(&dwc->lock, flags);
 117
 118         dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
 119
 120         return ret;
 121 }
 122
 123 static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc)
 124 {
 125         struct dw_desc  *child;
 126
 127         list_for_each_entry(child, &desc->tx_list, desc_node)
 128                 dma_sync_single_for_cpu(chan2parent(&dwc->chan),
 129                                 child->txd.phys, sizeof(child->lli),
 130                                 DMA_TO_DEVICE);
 131         dma_sync_single_for_cpu(chan2parent(&dwc->chan),
 132                         desc->txd.phys, sizeof(desc->lli),
 133                         DMA_TO_DEVICE);
 134 }
 135
 136 /*
 137  * Move a descriptor, including any children, to the free list.
 138  * `desc' must not be on any lists.
 139  */
 140 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
 141 {
 142         unsigned long flags;
 143
 144         if (desc) {
 145                 struct dw_desc *child;
 146
 147                 dwc_sync_desc_for_cpu(dwc, desc);
 148
 149                 spin_lock_irqsave(&dwc->lock, flags);
 150                 list_for_each_entry(child, &desc->tx_list, desc_node)
 151                         dev_vdbg(chan2dev(&dwc->chan),
 152                                         "moving child desc %p to freelist\n",
 153                                         child);
 154                 list_splice_init(&desc->tx_list, &dwc->free_list);
 155                 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
 156                 list_add(&desc->desc_node, &dwc->free_list);
 157                 spin_unlock_irqrestore(&dwc->lock, flags);
 158         }
 159 }
 160
 161 static void dwc_initialize(struct dw_dma_chan *dwc)
 162 {
 163         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
 164         struct dw_dma_slave *dws = dwc->chan.private;
 165         u32 cfghi = DWC_CFGH_FIFO_MODE;
 166         u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
 167
 168         if (dwc->initialized == true)
 169                 return;
 170
 171         if (dws) {
 172                 /*
 173                  * We need controller-specific data to set up slave
 174                  * transfers.
 175                  */
 176                 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
 177
 178                 cfghi = dws->cfg_hi;
 179                 cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
 180         } else {
 181                 if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV)
 182                         cfghi = DWC_CFGH_DST_PER(dwc->dma_sconfig.slave_id);
 183                 else if (dwc->dma_sconfig.direction == DMA_DEV_TO_MEM)
 184                         cfghi = DWC_CFGH_SRC_PER(dwc->dma_sconfig.slave_id);
 185         }
 186
 187         channel_writel(dwc, CFG_LO, cfglo);
 188         channel_writel(dwc, CFG_HI, cfghi);
 189
 190         /* Enable interrupts */
 191         channel_set_bit(dw, MASK.XFER, dwc->mask);
 192         channel_set_bit(dw, MASK.ERROR, dwc->mask);
 193
 194         dwc->initialized = true;
 195 }
 196
 197 /*----------------------------------------------------------------------*/
 198
 199 static inline unsigned int dwc_fast_fls(unsigned long long v)
 200 {
 201         /*
 202          * We can be a lot more clever here, but this should take care
 203          * of the most common optimization.
 204          */
 205         if (!(v & 7))
 206                 return 3;
 207         else if (!(v & 3))
 208                 return 2;
 209         else if (!(v & 1))
 210                 return 1;
 211         return 0;
 212 }
 213
 214 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
 215 {
 216         dev_err(chan2dev(&dwc->chan),
 217                 "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
 218                 channel_readl(dwc, SAR),
 219                 channel_readl(dwc, DAR),
 220                 channel_readl(dwc, LLP),
 221                 channel_readl(dwc, CTL_HI),
 222                 channel_readl(dwc, CTL_LO));
 223 }
 224
 225 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
 226 {
 227         channel_clear_bit(dw, CH_EN, dwc->mask);
 228         while (dma_readl(dw, CH_EN) & dwc->mask)
 229                 cpu_relax();
 230 }
 231
 232 /*----------------------------------------------------------------------*/
 233
 234 /* Perform single block transfer */
 235 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
 236                                        struct dw_desc *desc)
 237 {
 238         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 239         u32             ctllo;
 240
 241         /* Software emulation of LLP mode relies on interrupts to continue
 242          * multi block transfer. */
 243         ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
 244
 245         channel_writel(dwc, SAR, desc->lli.sar);
 246         channel_writel(dwc, DAR, desc->lli.dar);
 247         channel_writel(dwc, CTL_LO, ctllo);
 248         channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
 249         channel_set_bit(dw, CH_EN, dwc->mask);
 250 }
 251
 252 /* Called with dwc->lock held and bh disabled */
 253 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
 254 {
 255         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 256         unsigned long   was_soft_llp;
 257
 258         /* ASSERT:  channel is idle */
 259         if (dma_readl(dw, CH_EN) & dwc->mask) {
 260                 dev_err(chan2dev(&dwc->chan),
 261                         "BUG: Attempted to start non-idle channel\n");
 262                 dwc_dump_chan_regs(dwc);
 263
 264                 /* The tasklet will hopefully advance the queue... */
 265                 return;
 266         }
 267
 268         if (dwc->nollp) {
 269                 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
 270                                                 &dwc->flags);
 271                 if (was_soft_llp) {
 272                         dev_err(chan2dev(&dwc->chan),
 273                                 "BUG: Attempted to start new LLP transfer "
 274                                 "inside ongoing one\n");
 275                         return;
 276                 }
 277
 278                 dwc_initialize(dwc);
 279
 280                 dwc->tx_list = &first->tx_list;
 281                 dwc->tx_node_active = first->tx_list.next;
 282
 283                 dwc_do_single_block(dwc, first);
 284
 285                 return;
 286         }
 287
 288         dwc_initialize(dwc);
 289
 290         channel_writel(dwc, LLP, first->txd.phys);
 291         channel_writel(dwc, CTL_LO,
 292                         DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 293         channel_writel(dwc, CTL_HI, 0);
 294         channel_set_bit(dw, CH_EN, dwc->mask);
 295 }
 296
 297 /*----------------------------------------------------------------------*/
 298
 299 static void
 300 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
 301                 bool callback_required)
 302 {
 303         dma_async_tx_callback           callback = NULL;
 304         void                            *param = NULL;
 305         struct dma_async_tx_descriptor  *txd = &desc->txd;
 306         struct dw_desc                  *child;
 307         unsigned long                   flags;
 308
 309         dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 310
 311         spin_lock_irqsave(&dwc->lock, flags);
 312         dma_cookie_complete(txd);
 313         if (callback_required) {
 314                 callback = txd->callback;
 315                 param = txd->callback_param;
 316         }
 317
 318         dwc_sync_desc_for_cpu(dwc, desc);
 319
 320         /* async_tx_ack */
 321         list_for_each_entry(child, &desc->tx_list, desc_node)
 322                 async_tx_ack(&child->txd);
 323         async_tx_ack(&desc->txd);
 324
 325         list_splice_init(&desc->tx_list, &dwc->free_list);
 326         list_move(&desc->desc_node, &dwc->free_list);
 327
 328         if (!dwc->chan.private) {
 329                 struct device *parent = chan2parent(&dwc->chan);
 330                 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
 331                         if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
 332                                 dma_unmap_single(parent, desc->lli.dar,
 333                                                 desc->len, DMA_FROM_DEVICE);
 334                         else
 335                                 dma_unmap_page(parent, desc->lli.dar,
 336                                                 desc->len, DMA_FROM_DEVICE);
 337                 }
 338                 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
 339                         if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
 340                                 dma_unmap_single(parent, desc->lli.sar,
 341                                                 desc->len, DMA_TO_DEVICE);
 342                         else
 343                                 dma_unmap_page(parent, desc->lli.sar,
 344                                                 desc->len, DMA_TO_DEVICE);
 345                 }
 346         }
 347
 348         spin_unlock_irqrestore(&dwc->lock, flags);
 349
 350         if (callback)
 351                 callback(param);
 352 }
 353
 354 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
 355 {
 356         struct dw_desc *desc, *_desc;
 357         LIST_HEAD(list);
 358         unsigned long flags;
 359
 360         spin_lock_irqsave(&dwc->lock, flags);
 361         if (dma_readl(dw, CH_EN) & dwc->mask) {
 362                 dev_err(chan2dev(&dwc->chan),
 363                         "BUG: XFER bit set, but channel not idle!\n");
 364
 365                 /* Try to continue after resetting the channel... */
 366                 dwc_chan_disable(dw, dwc);
 367         }
 368
 369         /*
 370          * Submit queued descriptors ASAP, i.e. before we go through
 371          * the completed ones.
 372          */
 373         list_splice_init(&dwc->active_list, &list);
 374         if (!list_empty(&dwc->queue)) {
 375                 list_move(dwc->queue.next, &dwc->active_list);
 376                 dwc_dostart(dwc, dwc_first_active(dwc));
 377         }
 378
 379         spin_unlock_irqrestore(&dwc->lock, flags);
 380
 381         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 382                 dwc_descriptor_complete(dwc, desc, true);
 383 }
 384
 385 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 386 {
 387         dma_addr_t llp;
 388         struct dw_desc *desc, *_desc;
 389         struct dw_desc *child;
 390         u32 status_xfer;
 391         unsigned long flags;
 392
 393         spin_lock_irqsave(&dwc->lock, flags);
 394         llp = channel_readl(dwc, LLP);
 395         status_xfer = dma_readl(dw, RAW.XFER);
 396
 397         if (status_xfer & dwc->mask) {
 398                 /* Everything we've submitted is done */
 399                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 400                 spin_unlock_irqrestore(&dwc->lock, flags);
 401
 402                 dwc_complete_all(dw, dwc);
 403                 return;
 404         }
 405
 406         if (list_empty(&dwc->active_list)) {
 407                 spin_unlock_irqrestore(&dwc->lock, flags);
 408                 return;
 409         }
 410
 411         dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__,
 412                         (unsigned long long)llp);
 413
 414         list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
 415                 /* check first descriptors addr */
 416                 if (desc->txd.phys == llp) {
 417                         spin_unlock_irqrestore(&dwc->lock, flags);
 418                         return;
 419                 }
 420
 421                 /* check first descriptors llp */
 422                 if (desc->lli.llp == llp) {
 423                         /* This one is currently in progress */
 424                         spin_unlock_irqrestore(&dwc->lock, flags);
 425                         return;
 426                 }
 427
 428                 list_for_each_entry(child, &desc->tx_list, desc_node)
 429                         if (child->lli.llp == llp) {
 430                                 /* Currently in progress */
 431                                 spin_unlock_irqrestore(&dwc->lock, flags);
 432                                 return;
 433                         }
 434
 435                 /*
 436                  * No descriptors so far seem to be in progress, i.e.
 437                  * this one must be done.
 438                  */
 439                 spin_unlock_irqrestore(&dwc->lock, flags);
 440                 dwc_descriptor_complete(dwc, desc, true);
 441                 spin_lock_irqsave(&dwc->lock, flags);
 442         }
 443
 444         dev_err(chan2dev(&dwc->chan),
 445                 "BUG: All descriptors done, but channel not idle!\n");
 446
 447         /* Try to continue after resetting the channel... */
 448         dwc_chan_disable(dw, dwc);
 449
 450         if (!list_empty(&dwc->queue)) {
 451                 list_move(dwc->queue.next, &dwc->active_list);
 452                 dwc_dostart(dwc, dwc_first_active(dwc));
 453         }
 454         spin_unlock_irqrestore(&dwc->lock, flags);
 455 }
 456
 457 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
 458 {
 459         dev_crit(chan2dev(&dwc->chan), "  desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
 460                  lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
 461 }
 462
 463 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
 464 {
 465         struct dw_desc *bad_desc;
 466         struct dw_desc *child;
 467         unsigned long flags;
 468
 469         dwc_scan_descriptors(dw, dwc);
 470
 471         spin_lock_irqsave(&dwc->lock, flags);
 472
 473         /*
 474          * The descriptor currently at the head of the active list is
 475          * borked. Since we don't have any way to report errors, we'll
 476          * just have to scream loudly and try to carry on.
 477          */
 478         bad_desc = dwc_first_active(dwc);
 479         list_del_init(&bad_desc->desc_node);
 480         list_move(dwc->queue.next, dwc->active_list.prev);
 481
 482         /* Clear the error flag and try to restart the controller */
 483         dma_writel(dw, CLEAR.ERROR, dwc->mask);
 484         if (!list_empty(&dwc->active_list))
 485                 dwc_dostart(dwc, dwc_first_active(dwc));
 486
 487         /*
 488          * WARN may seem harsh, but since this only happens
 489          * when someone submits a bad physical address in a
 490          * descriptor, we should consider ourselves lucky that the
 491          * controller flagged an error instead of scribbling over
 492          * random memory locations.
 493          */
 494         dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
 495                                        "  cookie: %d\n", bad_desc->txd.cookie);
 496         dwc_dump_lli(dwc, &bad_desc->lli);
 497         list_for_each_entry(child, &bad_desc->tx_list, desc_node)
 498                 dwc_dump_lli(dwc, &child->lli);
 499
 500         spin_unlock_irqrestore(&dwc->lock, flags);
 501
 502         /* Pretend the descriptor completed successfully */
 503         dwc_descriptor_complete(dwc, bad_desc, true);
 504 }
 505
 506 /* --------------------- Cyclic DMA API extensions -------------------- */
 507
 508 inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
 509 {
 510         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 511         return channel_readl(dwc, SAR);
 512 }
 513 EXPORT_SYMBOL(dw_dma_get_src_addr);
 514
 515 inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
 516 {
 517         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 518         return channel_readl(dwc, DAR);
 519 }
 520 EXPORT_SYMBOL(dw_dma_get_dst_addr);
 521
 522 /* called with dwc->lock held and all DMAC interrupts disabled */
 523 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
 524                 u32 status_err, u32 status_xfer)
 525 {
 526         unsigned long flags;
 527
 528         if (dwc->mask) {
 529                 void (*callback)(void *param);
 530                 void *callback_param;
 531
 532                 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
 533                                 channel_readl(dwc, LLP));
 534
 535                 callback = dwc->cdesc->period_callback;
 536                 callback_param = dwc->cdesc->period_callback_param;
 537
 538                 if (callback)
 539                         callback(callback_param);
 540         }
 541
 542         /*
 543          * Error and transfer complete are highly unlikely, and will most
 544          * likely be due to a configuration error by the user.
 545          */
 546         if (unlikely(status_err & dwc->mask) ||
 547                         unlikely(status_xfer & dwc->mask)) {
 548                 int i;
 549
 550                 dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s "
 551                                 "interrupt, stopping DMA transfer\n",
 552                                 status_xfer ? "xfer" : "error");
 553
 554                 spin_lock_irqsave(&dwc->lock, flags);
 555
 556                 dwc_dump_chan_regs(dwc);
 557
 558                 dwc_chan_disable(dw, dwc);
 559
 560                 /* make sure DMA does not restart by loading a new list */
 561                 channel_writel(dwc, LLP, 0);
 562                 channel_writel(dwc, CTL_LO, 0);
 563                 channel_writel(dwc, CTL_HI, 0);
 564
 565                 dma_writel(dw, CLEAR.ERROR, dwc->mask);
 566                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 567
 568                 for (i = 0; i < dwc->cdesc->periods; i++)
 569                         dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
 570
 571                 spin_unlock_irqrestore(&dwc->lock, flags);
 572         }
 573 }
 574
 575 /* ------------------------------------------------------------------------- */
 576
 577 static void dw_dma_tasklet(unsigned long data)
 578 {
 579         struct dw_dma *dw = (struct dw_dma *)data;
 580         struct dw_dma_chan *dwc;
 581         u32 status_xfer;
 582         u32 status_err;
 583         int i;
 584
 585         status_xfer = dma_readl(dw, RAW.XFER);
 586         status_err = dma_readl(dw, RAW.ERROR);
 587
 588         dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
 589
 590         for (i = 0; i < dw->dma.chancnt; i++) {
 591                 dwc = &dw->chan[i];
 592                 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
 593                         dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
 594                 else if (status_err & (1 << i))
 595                         dwc_handle_error(dw, dwc);
 596                 else if (status_xfer & (1 << i)) {
 597                         unsigned long flags;
 598
 599                         spin_lock_irqsave(&dwc->lock, flags);
 600                         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 601                                 if (dwc->tx_node_active != dwc->tx_list) {
 602                                         struct dw_desc *desc =
 603                                                 to_dw_desc(dwc->tx_node_active);
 604
 605                                         dma_writel(dw, CLEAR.XFER, dwc->mask);
 606
 607                                         /* move pointer to next descriptor */
 608                                         dwc->tx_node_active =
 609                                                 dwc->tx_node_active->next;
 610
 611                                         dwc_do_single_block(dwc, desc);
 612
 613                                         spin_unlock_irqrestore(&dwc->lock, flags);
 614                                         continue;
 615                                 } else {
 616                                         /* we are done here */
 617                                         clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
 618                                 }
 619                         }
 620                         spin_unlock_irqrestore(&dwc->lock, flags);
 621
 622                         dwc_scan_descriptors(dw, dwc);
 623                 }
 624         }
 625
 626         /*
 627          * Re-enable interrupts.
 628          */
 629         channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
 630         channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
 631 }
 632
 633 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
 634 {
 635         struct dw_dma *dw = dev_id;
 636         u32 status;
 637
 638         dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__,
 639                         dma_readl(dw, STATUS_INT));
 640
 641         /*
 642          * Just disable the interrupts. We'll turn them back on in the
 643          * softirq handler.
 644          */
 645         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
 646         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
 647
 648         status = dma_readl(dw, STATUS_INT);
 649         if (status) {
 650                 dev_err(dw->dma.dev,
 651                         "BUG: Unexpected interrupts pending: 0x%x\n",
 652                         status);
 653
 654                 /* Try to recover */
 655                 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
 656                 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
 657                 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
 658                 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
 659         }
 660
 661         tasklet_schedule(&dw->tasklet);
 662
 663         return IRQ_HANDLED;
 664 }
 665
 666 /*----------------------------------------------------------------------*/
 667
 668 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
 669 {
 670         struct dw_desc          *desc = txd_to_dw_desc(tx);
 671         struct dw_dma_chan      *dwc = to_dw_dma_chan(tx->chan);
 672         dma_cookie_t            cookie;
 673         unsigned long           flags;
 674
 675         spin_lock_irqsave(&dwc->lock, flags);
 676         cookie = dma_cookie_assign(tx);
 677
 678         /*
 679          * REVISIT: We should attempt to chain as many descriptors as
 680          * possible, perhaps even appending to those already submitted
 681          * for DMA. But this is hard to do in a race-free manner.
 682          */
 683         if (list_empty(&dwc->active_list)) {
 684                 dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__,
 685                                 desc->txd.cookie);
 686                 list_add_tail(&desc->desc_node, &dwc->active_list);
 687                 dwc_dostart(dwc, dwc_first_active(dwc));
 688         } else {
 689                 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__,
 690                                 desc->txd.cookie);
 691
 692                 list_add_tail(&desc->desc_node, &dwc->queue);
 693         }
 694
 695         spin_unlock_irqrestore(&dwc->lock, flags);
 696
 697         return cookie;
 698 }
 699
 700 static struct dma_async_tx_descriptor *
 701 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 702                 size_t len, unsigned long flags)
 703 {
 704         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 705         struct dw_dma_slave     *dws = chan->private;
 706         struct dw_desc          *desc;
 707         struct dw_desc          *first;
 708         struct dw_desc          *prev;
 709         size_t                  xfer_count;
 710         size_t                  offset;
 711         unsigned int            src_width;
 712         unsigned int            dst_width;
 713         unsigned int            data_width;
 714         u32                     ctllo;
 715
 716         dev_vdbg(chan2dev(chan),
 717                         "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__,
 718                         (unsigned long long)dest, (unsigned long long)src,
 719                         len, flags);
 720
 721         if (unlikely(!len)) {
 722                 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
 723                 return NULL;
 724         }
 725
 726         data_width = min_t(unsigned int, dwc->dw->data_width[dwc_get_sms(dws)],
 727                                          dwc->dw->data_width[dwc_get_dms(dws)]);
 728
 729         src_width = dst_width = min_t(unsigned int, data_width,
 730                                       dwc_fast_fls(src | dest | len));
 731
 732         ctllo = DWC_DEFAULT_CTLLO(chan)
 733                         | DWC_CTLL_DST_WIDTH(dst_width)
 734                         | DWC_CTLL_SRC_WIDTH(src_width)
 735                         | DWC_CTLL_DST_INC
 736                         | DWC_CTLL_SRC_INC
 737                         | DWC_CTLL_FC_M2M;
 738         prev = first = NULL;
 739
 740         for (offset = 0; offset < len; offset += xfer_count << src_width) {
 741                 xfer_count = min_t(size_t, (len - offset) >> src_width,
 742                                            dwc->block_size);
 743
 744                 desc = dwc_desc_get(dwc);
 745                 if (!desc)
 746                         goto err_desc_get;
 747
 748                 desc->lli.sar = src + offset;
 749                 desc->lli.dar = dest + offset;
 750                 desc->lli.ctllo = ctllo;
 751                 desc->lli.ctlhi = xfer_count;
 752
 753                 if (!first) {
 754                         first = desc;
 755                 } else {
 756                         prev->lli.llp = desc->txd.phys;
 757                         dma_sync_single_for_device(chan2parent(chan),
 758                                         prev->txd.phys, sizeof(prev->lli),
 759                                         DMA_TO_DEVICE);
 760                         list_add_tail(&desc->desc_node,
 761                                         &first->tx_list);
 762                 }
 763                 prev = desc;
 764         }
 765
 766
 767         if (flags & DMA_PREP_INTERRUPT)
 768                 /* Trigger interrupt after last block */
 769                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 770
 771         prev->lli.llp = 0;
 772         dma_sync_single_for_device(chan2parent(chan),
 773                         prev->txd.phys, sizeof(prev->lli),
 774                         DMA_TO_DEVICE);
 775
 776         first->txd.flags = flags;
 777         first->len = len;
 778
 779         return &first->txd;
 780
 781 err_desc_get:
 782         dwc_desc_put(dwc, first);
 783         return NULL;
 784 }
 785
 786 static struct dma_async_tx_descriptor *
 787 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 788                 unsigned int sg_len, enum dma_transfer_direction direction,
 789                 unsigned long flags, void *context)
 790 {
 791         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 792         struct dw_dma_slave     *dws = chan->private;
 793         struct dma_slave_config *sconfig = &dwc->dma_sconfig;
 794         struct dw_desc          *prev;
 795         struct dw_desc          *first;
 796         u32                     ctllo;
 797         dma_addr_t              reg;
 798         unsigned int            reg_width;
 799         unsigned int            mem_width;
 800         unsigned int            data_width;
 801         unsigned int            i;
 802         struct scatterlist      *sg;
 803         size_t                  total_len = 0;
 804
 805         dev_vdbg(chan2dev(chan), "%s\n", __func__);
 806
 807         if (unlikely(!dws || !sg_len))
 808                 return NULL;
 809
 810         prev = first = NULL;
 811
 812         switch (direction) {
 813         case DMA_MEM_TO_DEV:
 814                 reg_width = __fls(sconfig->dst_addr_width);
 815                 reg = sconfig->dst_addr;
 816                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 817                                 | DWC_CTLL_DST_WIDTH(reg_width)
 818                                 | DWC_CTLL_DST_FIX
 819                                 | DWC_CTLL_SRC_INC);
 820
 821                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
 822                         DWC_CTLL_FC(DW_DMA_FC_D_M2P);
 823
 824                 data_width = dwc->dw->data_width[dwc_get_sms(dws)];
 825
 826                 for_each_sg(sgl, sg, sg_len, i) {
 827                         struct dw_desc  *desc;
 828                         u32             len, dlen, mem;
 829
 830                         mem = sg_dma_address(sg);
 831                         len = sg_dma_len(sg);
 832
 833                         mem_width = min_t(unsigned int,
 834                                           data_width, dwc_fast_fls(mem | len));
 835
 836 slave_sg_todev_fill_desc:
 837                         desc = dwc_desc_get(dwc);
 838                         if (!desc) {
 839                                 dev_err(chan2dev(chan),
 840                                         "not enough descriptors available\n");
 841                                 goto err_desc_get;
 842                         }
 843
 844                         desc->lli.sar = mem;
 845                         desc->lli.dar = reg;
 846                         desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
 847                         if ((len >> mem_width) > dwc->block_size) {
 848                                 dlen = dwc->block_size << mem_width;
 849                                 mem += dlen;
 850                                 len -= dlen;
 851                         } else {
 852                                 dlen = len;
 853                                 len = 0;
 854                         }
 855
 856                         desc->lli.ctlhi = dlen >> mem_width;
 857
 858                         if (!first) {
 859                                 first = desc;
 860                         } else {
 861                                 prev->lli.llp = desc->txd.phys;
 862                                 dma_sync_single_for_device(chan2parent(chan),
 863                                                 prev->txd.phys,
 864                                                 sizeof(prev->lli),
 865                                                 DMA_TO_DEVICE);
 866                                 list_add_tail(&desc->desc_node,
 867                                                 &first->tx_list);
 868                         }
 869                         prev = desc;
 870                         total_len += dlen;
 871
 872                         if (len)
 873                                 goto slave_sg_todev_fill_desc;
 874                 }
 875                 break;
 876         case DMA_DEV_TO_MEM:
 877                 reg_width = __fls(sconfig->src_addr_width);
 878                 reg = sconfig->src_addr;
 879                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 880                                 | DWC_CTLL_SRC_WIDTH(reg_width)
 881                                 | DWC_CTLL_DST_INC
 882                                 | DWC_CTLL_SRC_FIX);
 883
 884                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
 885                         DWC_CTLL_FC(DW_DMA_FC_D_P2M);
 886
 887                 data_width = dwc->dw->data_width[dwc_get_dms(dws)];
 888
 889                 for_each_sg(sgl, sg, sg_len, i) {
 890                         struct dw_desc  *desc;
 891                         u32             len, dlen, mem;
 892
 893                         mem = sg_dma_address(sg);
 894                         len = sg_dma_len(sg);
 895
 896                         mem_width = min_t(unsigned int,
 897                                           data_width, dwc_fast_fls(mem | len));
 898
 899 slave_sg_fromdev_fill_desc:
 900                         desc = dwc_desc_get(dwc);
 901                         if (!desc) {
 902                                 dev_err(chan2dev(chan),
 903                                                 "not enough descriptors available\n");
 904                                 goto err_desc_get;
 905                         }
 906
 907                         desc->lli.sar = reg;
 908                         desc->lli.dar = mem;
 909                         desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
 910                         if ((len >> reg_width) > dwc->block_size) {
 911                                 dlen = dwc->block_size << reg_width;
 912                                 mem += dlen;
 913                                 len -= dlen;
 914                         } else {
 915                                 dlen = len;
 916                                 len = 0;
 917                         }
 918                         desc->lli.ctlhi = dlen >> reg_width;
 919
 920                         if (!first) {
 921                                 first = desc;
 922                         } else {
 923                                 prev->lli.llp = desc->txd.phys;
 924                                 dma_sync_single_for_device(chan2parent(chan),
 925                                                 prev->txd.phys,
 926                                                 sizeof(prev->lli),
 927                                                 DMA_TO_DEVICE);
 928                                 list_add_tail(&desc->desc_node,
 929                                                 &first->tx_list);
 930                         }
 931                         prev = desc;
 932                         total_len += dlen;
 933
 934                         if (len)
 935                                 goto slave_sg_fromdev_fill_desc;
 936                 }
 937                 break;
 938         default:
 939                 return NULL;
 940         }
 941
 942         if (flags & DMA_PREP_INTERRUPT)
 943                 /* Trigger interrupt after last block */
 944                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 945
 946         prev->lli.llp = 0;
 947         dma_sync_single_for_device(chan2parent(chan),
 948                         prev->txd.phys, sizeof(prev->lli),
 949                         DMA_TO_DEVICE);
 950
 951         first->len = total_len;
 952
 953         return &first->txd;
 954
 955 err_desc_get:
 956         dwc_desc_put(dwc, first);
 957         return NULL;
 958 }
 959
 960 /*
 961  * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
 962  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
 963  *
 964  * NOTE: burst size 2 is not supported by controller.
 965  *
 966  * This can be done by finding least significant bit set: n & (n - 1)
 967  */
 968 static inline void convert_burst(u32 *maxburst)
 969 {
 970         if (*maxburst > 1)
 971                 *maxburst = fls(*maxburst) - 2;
 972         else
 973                 *maxburst = 0;
 974 }
 975
 976 static int
 977 set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
 978 {
 979         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 980
 981         /* Check if it is chan is configured for slave transfers */
 982         if (!chan->private)
 983                 return -EINVAL;
 984
 985         memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
 986
 987         convert_burst(&dwc->dma_sconfig.src_maxburst);
 988         convert_burst(&dwc->dma_sconfig.dst_maxburst);
 989
 990         return 0;
 991 }
 992
 993 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 994                        unsigned long arg)
 995 {
 996         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 997         struct dw_dma           *dw = to_dw_dma(chan->device);
 998         struct dw_desc          *desc, *_desc;
 999         unsigned long           flags;
1000         u32                     cfglo;
1001         LIST_HEAD(list);
1002
1003         if (cmd == DMA_PAUSE) {
1004                 spin_lock_irqsave(&dwc->lock, flags);
1005
1006                 cfglo = channel_readl(dwc, CFG_LO);
1007                 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
1008                 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY))
1009                         cpu_relax();
1010
1011                 dwc->paused = true;
1012                 spin_unlock_irqrestore(&dwc->lock, flags);
1013         } else if (cmd == DMA_RESUME) {
1014                 if (!dwc->paused)
1015                         return 0;
1016
1017                 spin_lock_irqsave(&dwc->lock, flags);
1018
1019                 cfglo = channel_readl(dwc, CFG_LO);
1020                 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
1021                 dwc->paused = false;
1022
1023                 spin_unlock_irqrestore(&dwc->lock, flags);
1024         } else if (cmd == DMA_TERMINATE_ALL) {
1025                 spin_lock_irqsave(&dwc->lock, flags);
1026
1027                 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1028
1029                 dwc_chan_disable(dw, dwc);
1030
1031                 dwc->paused = false;
1032
1033                 /* active_list entries will end up before queued entries */
1034                 list_splice_init(&dwc->queue, &list);
1035                 list_splice_init(&dwc->active_list, &list);
1036
1037                 spin_unlock_irqrestore(&dwc->lock, flags);
1038
1039                 /* Flush all pending and queued descriptors */
1040                 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1041                         dwc_descriptor_complete(dwc, desc, false);
1042         } else if (cmd == DMA_SLAVE_CONFIG) {
1043                 return set_runtime_config(chan, (struct dma_slave_config *)arg);
1044         } else {
1045                 return -ENXIO;
1046         }
1047
1048         return 0;
1049 }
1050
1051 static enum dma_status
1052 dwc_tx_status(struct dma_chan *chan,
1053               dma_cookie_t cookie,
1054               struct dma_tx_state *txstate)
1055 {
1056         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1057         enum dma_status         ret;
1058
1059         ret = dma_cookie_status(chan, cookie, txstate);
1060         if (ret != DMA_SUCCESS) {
1061                 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1062
1063                 ret = dma_cookie_status(chan, cookie, txstate);
1064         }
1065
1066         if (ret != DMA_SUCCESS)
1067                 dma_set_residue(txstate, dwc_first_active(dwc)->len);
1068
1069         if (dwc->paused)
1070                 return DMA_PAUSED;
1071
1072         return ret;
1073 }
1074
1075 static void dwc_issue_pending(struct dma_chan *chan)
1076 {
1077         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1078
1079         if (!list_empty(&dwc->queue))
1080                 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1081 }
1082
1083 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1084 {
1085         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1086         struct dw_dma           *dw = to_dw_dma(chan->device);
1087         struct dw_desc          *desc;
1088         int                     i;
1089         unsigned long           flags;
1090         int                     ret;
1091
1092         dev_vdbg(chan2dev(chan), "%s\n", __func__);
1093
1094         /* ASSERT:  channel is idle */
1095         if (dma_readl(dw, CH_EN) & dwc->mask) {
1096                 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1097                 return -EIO;
1098         }
1099
1100         dma_cookie_init(chan);
1101
1102         /*
1103          * NOTE: some controllers may have additional features that we
1104          * need to initialize here, like "scatter-gather" (which
1105          * doesn't mean what you think it means), and status writeback.
1106          */
1107
1108         spin_lock_irqsave(&dwc->lock, flags);
1109         i = dwc->descs_allocated;
1110         while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1111                 spin_unlock_irqrestore(&dwc->lock, flags);
1112
1113                 desc = kzalloc(sizeof(struct dw_desc), GFP_KERNEL);
1114                 if (!desc)
1115                         goto err_desc_alloc;
1116
1117                 INIT_LIST_HEAD(&desc->tx_list);
1118                 dma_async_tx_descriptor_init(&desc->txd, chan);
1119                 desc->txd.tx_submit = dwc_tx_submit;
1120                 desc->txd.flags = DMA_CTRL_ACK;
1121                 desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli,
1122                                 sizeof(desc->lli), DMA_TO_DEVICE);
1123                 ret = dma_mapping_error(chan2parent(chan), desc->txd.phys);
1124                 if (ret)
1125                         goto err_desc_alloc;
1126
1127                 dwc_desc_put(dwc, desc);
1128
1129                 spin_lock_irqsave(&dwc->lock, flags);
1130                 i = ++dwc->descs_allocated;
1131         }
1132
1133         spin_unlock_irqrestore(&dwc->lock, flags);
1134
1135         dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1136
1137         return i;
1138
1139 err_desc_alloc:
1140         kfree(desc);
1141
1142         dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1143
1144         return i;
1145 }
1146
1147 static void dwc_free_chan_resources(struct dma_chan *chan)
1148 {
1149         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1150         struct dw_dma           *dw = to_dw_dma(chan->device);
1151         struct dw_desc          *desc, *_desc;
1152         unsigned long           flags;
1153         LIST_HEAD(list);
1154
1155         dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1156                         dwc->descs_allocated);
1157
1158         /* ASSERT:  channel is idle */
1159         BUG_ON(!list_empty(&dwc->active_list));
1160         BUG_ON(!list_empty(&dwc->queue));
1161         BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1162
1163         spin_lock_irqsave(&dwc->lock, flags);
1164         list_splice_init(&dwc->free_list, &list);
1165         dwc->descs_allocated = 0;
1166         dwc->initialized = false;
1167
1168         /* Disable interrupts */
1169         channel_clear_bit(dw, MASK.XFER, dwc->mask);
1170         channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1171
1172         spin_unlock_irqrestore(&dwc->lock, flags);
1173
1174         list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1175                 dev_vdbg(chan2dev(chan), "  freeing descriptor %p\n", desc);
1176                 dma_unmap_single(chan2parent(chan), desc->txd.phys,
1177                                 sizeof(desc->lli), DMA_TO_DEVICE);
1178                 kfree(desc);
1179         }
1180
1181         dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1182 }
1183
1184 bool dw_dma_generic_filter(struct dma_chan *chan, void *param)
1185 {
1186         struct dw_dma *dw = to_dw_dma(chan->device);
1187         static struct dw_dma *last_dw;
1188         static char *last_bus_id;
1189         int i = -1;
1190
1191         /*
1192          * dmaengine framework calls this routine for all channels of all dma
1193          * controller, until true is returned. If 'param' bus_id is not
1194          * registered with a dma controller (dw), then there is no need of
1195          * running below function for all channels of dw.
1196          *
1197          * This block of code does this by saving the parameters of last
1198          * failure. If dw and param are same, i.e. trying on same dw with
1199          * different channel, return false.
1200          */
1201         if ((last_dw == dw) && (last_bus_id == param))
1202                 return false;
1203         /*
1204          * Return true:
1205          * - If dw_dma's platform data is not filled with slave info, then all
1206          *   dma controllers are fine for transfer.
1207          * - Or if param is NULL
1208          */
1209         if (!dw->sd || !param)
1210                 return true;
1211
1212         while (++i < dw->sd_count) {
1213                 if (!strcmp(dw->sd[i].bus_id, param)) {
1214                         chan->private = &dw->sd[i];
1215                         last_dw = NULL;
1216                         last_bus_id = NULL;
1217
1218                         return true;
1219                 }
1220         }
1221
1222         last_dw = dw;
1223         last_bus_id = param;
1224         return false;
1225 }
1226 EXPORT_SYMBOL(dw_dma_generic_filter);
1227
1228 /* --------------------- Cyclic DMA API extensions -------------------- */
1229
1230 /**
1231  * dw_dma_cyclic_start - start the cyclic DMA transfer
1232  * @chan: the DMA channel to start
1233  *
1234  * Must be called with soft interrupts disabled. Returns zero on success or
1235  * -errno on failure.
1236  */
1237 int dw_dma_cyclic_start(struct dma_chan *chan)
1238 {
1239         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1240         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1241         unsigned long           flags;
1242
1243         if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1244                 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1245                 return -ENODEV;
1246         }
1247
1248         spin_lock_irqsave(&dwc->lock, flags);
1249
1250         /* assert channel is idle */
1251         if (dma_readl(dw, CH_EN) & dwc->mask) {
1252                 dev_err(chan2dev(&dwc->chan),
1253                         "BUG: Attempted to start non-idle channel\n");
1254                 dwc_dump_chan_regs(dwc);
1255                 spin_unlock_irqrestore(&dwc->lock, flags);
1256                 return -EBUSY;
1257         }
1258
1259         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1260         dma_writel(dw, CLEAR.XFER, dwc->mask);
1261
1262         /* setup DMAC channel registers */
1263         channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1264         channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1265         channel_writel(dwc, CTL_HI, 0);
1266
1267         channel_set_bit(dw, CH_EN, dwc->mask);
1268
1269         spin_unlock_irqrestore(&dwc->lock, flags);
1270
1271         return 0;
1272 }
1273 EXPORT_SYMBOL(dw_dma_cyclic_start);
1274
1275 /**
1276  * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1277  * @chan: the DMA channel to stop
1278  *
1279  * Must be called with soft interrupts disabled.
1280  */
1281 void dw_dma_cyclic_stop(struct dma_chan *chan)
1282 {
1283         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1284         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1285         unsigned long           flags;
1286
1287         spin_lock_irqsave(&dwc->lock, flags);
1288
1289         dwc_chan_disable(dw, dwc);
1290
1291         spin_unlock_irqrestore(&dwc->lock, flags);
1292 }
1293 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1294
1295 /**
1296  * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1297  * @chan: the DMA channel to prepare
1298  * @buf_addr: physical DMA address where the buffer starts
1299  * @buf_len: total number of bytes for the entire buffer
1300  * @period_len: number of bytes for each period
1301  * @direction: transfer direction, to or from device
1302  *
1303  * Must be called before trying to start the transfer. Returns a valid struct
1304  * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1305  */
1306 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1307                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1308                 enum dma_transfer_direction direction)
1309 {
1310         struct dw_dma_chan              *dwc = to_dw_dma_chan(chan);
1311         struct dma_slave_config         *sconfig = &dwc->dma_sconfig;
1312         struct dw_cyclic_desc           *cdesc;
1313         struct dw_cyclic_desc           *retval = NULL;
1314         struct dw_desc                  *desc;
1315         struct dw_desc                  *last = NULL;
1316         unsigned long                   was_cyclic;
1317         unsigned int                    reg_width;
1318         unsigned int                    periods;
1319         unsigned int                    i;
1320         unsigned long                   flags;
1321
1322         spin_lock_irqsave(&dwc->lock, flags);
1323         if (dwc->nollp) {
1324                 spin_unlock_irqrestore(&dwc->lock, flags);
1325                 dev_dbg(chan2dev(&dwc->chan),
1326                                 "channel doesn't support LLP transfers\n");
1327                 return ERR_PTR(-EINVAL);
1328         }
1329
1330         if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1331                 spin_unlock_irqrestore(&dwc->lock, flags);
1332                 dev_dbg(chan2dev(&dwc->chan),
1333                                 "queue and/or active list are not empty\n");
1334                 return ERR_PTR(-EBUSY);
1335         }
1336
1337         was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1338         spin_unlock_irqrestore(&dwc->lock, flags);
1339         if (was_cyclic) {
1340                 dev_dbg(chan2dev(&dwc->chan),
1341                                 "channel already prepared for cyclic DMA\n");
1342                 return ERR_PTR(-EBUSY);
1343         }
1344
1345         retval = ERR_PTR(-EINVAL);
1346
1347         if (direction == DMA_MEM_TO_DEV)
1348                 reg_width = __ffs(sconfig->dst_addr_width);
1349         else
1350                 reg_width = __ffs(sconfig->src_addr_width);
1351
1352         periods = buf_len / period_len;
1353
1354         /* Check for too big/unaligned periods and unaligned DMA buffer. */
1355         if (period_len > (dwc->block_size << reg_width))
1356                 goto out_err;
1357         if (unlikely(period_len & ((1 << reg_width) - 1)))
1358                 goto out_err;
1359         if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1360                 goto out_err;
1361         if (unlikely(!(direction & (DMA_MEM_TO_DEV | DMA_DEV_TO_MEM))))
1362                 goto out_err;
1363
1364         retval = ERR_PTR(-ENOMEM);
1365
1366         if (periods > NR_DESCS_PER_CHANNEL)
1367                 goto out_err;
1368
1369         cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1370         if (!cdesc)
1371                 goto out_err;
1372
1373         cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1374         if (!cdesc->desc)
1375                 goto out_err_alloc;
1376
1377         for (i = 0; i < periods; i++) {
1378                 desc = dwc_desc_get(dwc);
1379                 if (!desc)
1380                         goto out_err_desc_get;
1381
1382                 switch (direction) {
1383                 case DMA_MEM_TO_DEV:
1384                         desc->lli.dar = sconfig->dst_addr;
1385                         desc->lli.sar = buf_addr + (period_len * i);
1386                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1387                                         | DWC_CTLL_DST_WIDTH(reg_width)
1388                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1389                                         | DWC_CTLL_DST_FIX
1390                                         | DWC_CTLL_SRC_INC
1391                                         | DWC_CTLL_INT_EN);
1392
1393                         desc->lli.ctllo |= sconfig->device_fc ?
1394                                 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1395                                 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1396
1397                         break;
1398                 case DMA_DEV_TO_MEM:
1399                         desc->lli.dar = buf_addr + (period_len * i);
1400                         desc->lli.sar = sconfig->src_addr;
1401                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1402                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1403                                         | DWC_CTLL_DST_WIDTH(reg_width)
1404                                         | DWC_CTLL_DST_INC
1405                                         | DWC_CTLL_SRC_FIX
1406                                         | DWC_CTLL_INT_EN);
1407
1408                         desc->lli.ctllo |= sconfig->device_fc ?
1409                                 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1410                                 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1411
1412                         break;
1413                 default:
1414                         break;
1415                 }
1416
1417                 desc->lli.ctlhi = (period_len >> reg_width);
1418                 cdesc->desc[i] = desc;
1419
1420                 if (last) {
1421                         last->lli.llp = desc->txd.phys;
1422                         dma_sync_single_for_device(chan2parent(chan),
1423                                         last->txd.phys, sizeof(last->lli),
1424                                         DMA_TO_DEVICE);
1425                 }
1426
1427                 last = desc;
1428         }
1429
1430         /* lets make a cyclic list */
1431         last->lli.llp = cdesc->desc[0]->txd.phys;
1432         dma_sync_single_for_device(chan2parent(chan), last->txd.phys,
1433                         sizeof(last->lli), DMA_TO_DEVICE);
1434
1435         dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu "
1436                         "period %zu periods %d\n", (unsigned long long)buf_addr,
1437                         buf_len, period_len, periods);
1438
1439         cdesc->periods = periods;
1440         dwc->cdesc = cdesc;
1441
1442         return cdesc;
1443
1444 out_err_desc_get:
1445         while (i--)
1446                 dwc_desc_put(dwc, cdesc->desc[i]);
1447 out_err_alloc:
1448         kfree(cdesc);
1449 out_err:
1450         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1451         return (struct dw_cyclic_desc *)retval;
1452 }
1453 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1454
1455 /**
1456  * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1457  * @chan: the DMA channel to free
1458  */
1459 void dw_dma_cyclic_free(struct dma_chan *chan)
1460 {
1461         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1462         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1463         struct dw_cyclic_desc   *cdesc = dwc->cdesc;
1464         int                     i;
1465         unsigned long           flags;
1466
1467         dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1468
1469         if (!cdesc)
1470                 return;
1471
1472         spin_lock_irqsave(&dwc->lock, flags);
1473
1474         dwc_chan_disable(dw, dwc);
1475
1476         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1477         dma_writel(dw, CLEAR.XFER, dwc->mask);
1478
1479         spin_unlock_irqrestore(&dwc->lock, flags);
1480
1481         for (i = 0; i < cdesc->periods; i++)
1482                 dwc_desc_put(dwc, cdesc->desc[i]);
1483
1484         kfree(cdesc->desc);
1485         kfree(cdesc);
1486
1487         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1488 }
1489 EXPORT_SYMBOL(dw_dma_cyclic_free);
1490
1491 /*----------------------------------------------------------------------*/
1492
1493 static void dw_dma_off(struct dw_dma *dw)
1494 {
1495         int i;
1496
1497         dma_writel(dw, CFG, 0);
1498
1499         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1500         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1501         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1502         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1503
1504         while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1505                 cpu_relax();
1506
1507         for (i = 0; i < dw->dma.chancnt; i++)
1508                 dw->chan[i].initialized = false;
1509 }
1510
1511 #ifdef CONFIG_OF
1512 static struct dw_dma_platform_data *
1513 dw_dma_parse_dt(struct platform_device *pdev)
1514 {
1515         struct device_node *sn, *cn, *np = pdev->dev.of_node;
1516         struct dw_dma_platform_data *pdata;
1517         struct dw_dma_slave *sd;
1518         u32 tmp, arr[4];
1519
1520         if (!np) {
1521                 dev_err(&pdev->dev, "Missing DT data\n");
1522                 return NULL;
1523         }
1524
1525         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1526         if (!pdata)
1527                 return NULL;
1528
1529         if (of_property_read_u32(np, "nr_channels", &pdata->nr_channels))
1530                 return NULL;
1531
1532         if (of_property_read_bool(np, "is_private"))
1533                 pdata->is_private = true;
1534
1535         if (!of_property_read_u32(np, "chan_allocation_order", &tmp))
1536                 pdata->chan_allocation_order = (unsigned char)tmp;
1537
1538         if (!of_property_read_u32(np, "chan_priority", &tmp))
1539                 pdata->chan_priority = tmp;
1540
1541         if (!of_property_read_u32(np, "block_size", &tmp))
1542                 pdata->block_size = tmp;
1543
1544         if (!of_property_read_u32(np, "nr_masters", &tmp)) {
1545                 if (tmp > 4)
1546                         return NULL;
1547
1548                 pdata->nr_masters = tmp;
1549         }
1550
1551         if (!of_property_read_u32_array(np, "data_width", arr,
1552                                 pdata->nr_masters))
1553                 for (tmp = 0; tmp < pdata->nr_masters; tmp++)
1554                         pdata->data_width[tmp] = arr[tmp];
1555
1556         /* parse slave data */
1557         sn = of_find_node_by_name(np, "slave_info");
1558         if (!sn)
1559                 return pdata;
1560
1561         /* calculate number of slaves */
1562         tmp = of_get_child_count(sn);
1563         if (!tmp)
1564                 return NULL;
1565
1566         sd = devm_kzalloc(&pdev->dev, sizeof(*sd) * tmp, GFP_KERNEL);
1567         if (!sd)
1568                 return NULL;
1569
1570         pdata->sd = sd;
1571         pdata->sd_count = tmp;
1572
1573         for_each_child_of_node(sn, cn) {
1574                 sd->dma_dev = &pdev->dev;
1575                 of_property_read_string(cn, "bus_id", &sd->bus_id);
1576                 of_property_read_u32(cn, "cfg_hi", &sd->cfg_hi);
1577                 of_property_read_u32(cn, "cfg_lo", &sd->cfg_lo);
1578                 if (!of_property_read_u32(cn, "src_master", &tmp))
1579                         sd->src_master = tmp;
1580
1581                 if (!of_property_read_u32(cn, "dst_master", &tmp))
1582                         sd->dst_master = tmp;
1583                 sd++;
1584         }
1585
1586         return pdata;
1587 }
1588 #else
1589 static inline struct dw_dma_platform_data *
1590 dw_dma_parse_dt(struct platform_device *pdev)
1591 {
1592         return NULL;
1593 }
1594 #endif
1595
1596 static int dw_probe(struct platform_device *pdev)
1597 {
1598         struct dw_dma_platform_data *pdata;
1599         struct resource         *io;
1600         struct dw_dma           *dw;
1601         size_t                  size;
1602         void __iomem            *regs;
1603         bool                    autocfg;
1604         unsigned int            dw_params;
1605         unsigned int            nr_channels;
1606         unsigned int            max_blk_size = 0;
1607         int                     irq;
1608         int                     err;
1609         int                     i;
1610
1611         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1612         if (!io)
1613                 return -EINVAL;
1614
1615         irq = platform_get_irq(pdev, 0);
1616         if (irq < 0)
1617                 return irq;
1618
1619         regs = devm_request_and_ioremap(&pdev->dev, io);
1620         if (!regs)
1621                 return -EBUSY;
1622
1623         dw_params = dma_read_byaddr(regs, DW_PARAMS);
1624         autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1625
1626         pdata = dev_get_platdata(&pdev->dev);
1627         if (!pdata)
1628                 pdata = dw_dma_parse_dt(pdev);
1629
1630         if (!pdata && autocfg) {
1631                 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1632                 if (!pdata)
1633                         return -ENOMEM;
1634
1635                 /* Fill platform data with the default values */
1636                 pdata->is_private = true;
1637                 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1638                 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1639         } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
1640                 return -EINVAL;
1641
1642         if (autocfg)
1643                 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
1644         else
1645                 nr_channels = pdata->nr_channels;
1646
1647         size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan);
1648         dw = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1649         if (!dw)
1650                 return -ENOMEM;
1651
1652         dw->clk = devm_clk_get(&pdev->dev, "hclk");
1653         if (IS_ERR(dw->clk))
1654                 return PTR_ERR(dw->clk);
1655         clk_prepare_enable(dw->clk);
1656
1657         dw->regs = regs;
1658         dw->sd = pdata->sd;
1659         dw->sd_count = pdata->sd_count;
1660
1661         /* get hardware configuration parameters */
1662         if (autocfg) {
1663                 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1664
1665                 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1666                 for (i = 0; i < dw->nr_masters; i++) {
1667                         dw->data_width[i] =
1668                                 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1669                 }
1670         } else {
1671                 dw->nr_masters = pdata->nr_masters;
1672                 memcpy(dw->data_width, pdata->data_width, 4);
1673         }
1674
1675         /* Calculate all channel mask before DMA setup */
1676         dw->all_chan_mask = (1 << nr_channels) - 1;
1677
1678         /* force dma off, just in case */
1679         dw_dma_off(dw);
1680
1681         /* disable BLOCK interrupts as well */
1682         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1683
1684         err = devm_request_irq(&pdev->dev, irq, dw_dma_interrupt, 0,
1685                                "dw_dmac", dw);
1686         if (err)
1687                 return err;
1688
1689         platform_set_drvdata(pdev, dw);
1690
1691         tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1692
1693         INIT_LIST_HEAD(&dw->dma.channels);
1694         for (i = 0; i < nr_channels; i++) {
1695                 struct dw_dma_chan      *dwc = &dw->chan[i];
1696                 int                     r = nr_channels - i - 1;
1697
1698                 dwc->chan.device = &dw->dma;
1699                 dma_cookie_init(&dwc->chan);
1700                 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1701                         list_add_tail(&dwc->chan.device_node,
1702                                         &dw->dma.channels);
1703                 else
1704                         list_add(&dwc->chan.device_node, &dw->dma.channels);
1705
1706                 /* 7 is highest priority & 0 is lowest. */
1707                 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1708                         dwc->priority = r;
1709                 else
1710                         dwc->priority = i;
1711
1712                 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1713                 spin_lock_init(&dwc->lock);
1714                 dwc->mask = 1 << i;
1715
1716                 INIT_LIST_HEAD(&dwc->active_list);
1717                 INIT_LIST_HEAD(&dwc->queue);
1718                 INIT_LIST_HEAD(&dwc->free_list);
1719
1720                 channel_clear_bit(dw, CH_EN, dwc->mask);
1721
1722                 dwc->dw = dw;
1723
1724                 /* hardware configuration */
1725                 if (autocfg) {
1726                         unsigned int dwc_params;
1727
1728                         dwc_params = dma_read_byaddr(regs + r * sizeof(u32),
1729                                                      DWC_PARAMS);
1730
1731                         /* Decode maximum block size for given channel. The
1732                          * stored 4 bit value represents blocks from 0x00 for 3
1733                          * up to 0x0a for 4095. */
1734                         dwc->block_size =
1735                                 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1736                         dwc->nollp =
1737                                 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1738                 } else {
1739                         dwc->block_size = pdata->block_size;
1740
1741                         /* Check if channel supports multi block transfer */
1742                         channel_writel(dwc, LLP, 0xfffffffc);
1743                         dwc->nollp =
1744                                 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1745                         channel_writel(dwc, LLP, 0);
1746                 }
1747         }
1748
1749         /* Clear all interrupts on all channels. */
1750         dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1751         dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1752         dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1753         dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1754         dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1755
1756         dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1757         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1758         if (pdata->is_private)
1759                 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1760         dw->dma.dev = &pdev->dev;
1761         dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1762         dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1763
1764         dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1765
1766         dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1767         dw->dma.device_control = dwc_control;
1768
1769         dw->dma.device_tx_status = dwc_tx_status;
1770         dw->dma.device_issue_pending = dwc_issue_pending;
1771
1772         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1773
1774         dev_info(&pdev->dev, "DesignWare DMA Controller, %d channels\n",
1775                  nr_channels);
1776
1777         dma_async_device_register(&dw->dma);
1778
1779         return 0;
1780 }
1781
1782 static int __devexit dw_remove(struct platform_device *pdev)
1783 {
1784         struct dw_dma           *dw = platform_get_drvdata(pdev);
1785         struct dw_dma_chan      *dwc, *_dwc;
1786
1787         dw_dma_off(dw);
1788         dma_async_device_unregister(&dw->dma);
1789
1790         tasklet_kill(&dw->tasklet);
1791
1792         list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1793                         chan.device_node) {
1794                 list_del(&dwc->chan.device_node);
1795                 channel_clear_bit(dw, CH_EN, dwc->mask);
1796         }
1797
1798         return 0;
1799 }
1800
1801 static void dw_shutdown(struct platform_device *pdev)
1802 {
1803         struct dw_dma   *dw = platform_get_drvdata(pdev);
1804
1805         dw_dma_off(dw);
1806         clk_disable_unprepare(dw->clk);
1807 }
1808
1809 static int dw_suspend_noirq(struct device *dev)
1810 {
1811         struct platform_device *pdev = to_platform_device(dev);
1812         struct dw_dma   *dw = platform_get_drvdata(pdev);
1813
1814         dw_dma_off(dw);
1815         clk_disable_unprepare(dw->clk);
1816
1817         return 0;
1818 }
1819
1820 static int dw_resume_noirq(struct device *dev)
1821 {
1822         struct platform_device *pdev = to_platform_device(dev);
1823         struct dw_dma   *dw = platform_get_drvdata(pdev);
1824
1825         clk_prepare_enable(dw->clk);
1826         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1827
1828         return 0;
1829 }
1830
1831 static const struct dev_pm_ops dw_dev_pm_ops = {
1832         .suspend_noirq = dw_suspend_noirq,
1833         .resume_noirq = dw_resume_noirq,
1834         .freeze_noirq = dw_suspend_noirq,
1835         .thaw_noirq = dw_resume_noirq,
1836         .restore_noirq = dw_resume_noirq,
1837         .poweroff_noirq = dw_suspend_noirq,
1838 };
1839
1840 #ifdef CONFIG_OF
1841 static const struct of_device_id dw_dma_id_table[] = {
1842         { .compatible = "snps,dma-spear1340" },
1843         {}
1844 };
1845 MODULE_DEVICE_TABLE(of, dw_dma_id_table);
1846 #endif
1847
1848 static struct platform_driver dw_driver = {
1849         .remove         = dw_remove,
1850         .shutdown       = dw_shutdown,
1851         .driver = {
1852                 .name   = "dw_dmac",
1853                 .pm     = &dw_dev_pm_ops,
1854                 .of_match_table = of_match_ptr(dw_dma_id_table),
1855         },
1856 };
1857
1858 static int __init dw_init(void)
1859 {
1860         return platform_driver_probe(&dw_driver, dw_probe);
1861 }
1862 subsys_initcall(dw_init);
1863
1864 static void __exit dw_exit(void)
1865 {
1866         platform_driver_unregister(&dw_driver);
1867 }
1868 module_exit(dw_exit);
1869
1870 MODULE_LICENSE("GPL v2");
1871 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
1872 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1873 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");