drivers/dma/dw_dmac.c

   1 /*
   2  * Core driver for the Synopsys DesignWare DMA Controller
   3  *
   4  * Copyright (C) 2007-2008 Atmel Corporation
   5  * Copyright (C) 2010-2011 ST Microelectronics
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/init.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/of.h>
  21 #include <linux/mm.h>
  22 #include <linux/module.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/slab.h>
  25
  26 #include "dw_dmac_regs.h"
  27 #include "dmaengine.h"
  28
  29 /*
  30  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
  31  * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
  32  * of which use ARM any more).  See the "Databook" from Synopsys for
  33  * information beyond what licensees probably provide.
  34  *
  35  * The driver has currently been tested only with the Atmel AT32AP7000,
  36  * which does not support descriptor writeback.
  37  */
  38
  39 static inline unsigned int dwc_get_dms(struct dw_dma_slave *slave)
  40 {
  41         return slave ? slave->dst_master : 0;
  42 }
  43
  44 static inline unsigned int dwc_get_sms(struct dw_dma_slave *slave)
  45 {
  46         return slave ? slave->src_master : 1;
  47 }
  48
  49 #define DWC_DEFAULT_CTLLO(_chan) ({                             \
  50                 struct dw_dma_slave *__slave = (_chan->private);        \
  51                 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan);       \
  52                 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
  53                 int _dms = dwc_get_dms(__slave);                \
  54                 int _sms = dwc_get_sms(__slave);                \
  55                 u8 _smsize = __slave ? _sconfig->src_maxburst : \
  56                         DW_DMA_MSIZE_16;                        \
  57                 u8 _dmsize = __slave ? _sconfig->dst_maxburst : \
  58                         DW_DMA_MSIZE_16;                        \
  59                                                                 \
  60                 (DWC_CTLL_DST_MSIZE(_dmsize)                    \
  61                  | DWC_CTLL_SRC_MSIZE(_smsize)                  \
  62                  | DWC_CTLL_LLP_D_EN                            \
  63                  | DWC_CTLL_LLP_S_EN                            \
  64                  | DWC_CTLL_DMS(_dms)                           \
  65                  | DWC_CTLL_SMS(_sms));                         \
  66         })
  67
  68 /*
  69  * Number of descriptors to allocate for each channel. This should be
  70  * made configurable somehow; preferably, the clients (at least the
  71  * ones using slave transfers) should be able to give us a hint.
  72  */
  73 #define NR_DESCS_PER_CHANNEL    64
  74
  75 /*----------------------------------------------------------------------*/
  76
  77 /*
  78  * Because we're not relying on writeback from the controller (it may not
  79  * even be configured into the core!) we don't need to use dma_pool.  These
  80  * descriptors -- and associated data -- are cacheable.  We do need to make
  81  * sure their dcache entries are written back before handing them off to
  82  * the controller, though.
  83  */
  84
  85 static struct device *chan2dev(struct dma_chan *chan)
  86 {
  87         return &chan->dev->device;
  88 }
  89 static struct device *chan2parent(struct dma_chan *chan)
  90 {
  91         return chan->dev->device.parent;
  92 }
  93
  94 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
  95 {
  96         return to_dw_desc(dwc->active_list.next);
  97 }
  98
  99 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
 100 {
 101         struct dw_desc *desc, *_desc;
 102         struct dw_desc *ret = NULL;
 103         unsigned int i = 0;
 104         unsigned long flags;
 105
 106         spin_lock_irqsave(&dwc->lock, flags);
 107         list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
 108                 i++;
 109                 if (async_tx_test_ack(&desc->txd)) {
 110                         list_del(&desc->desc_node);
 111                         ret = desc;
 112                         break;
 113                 }
 114                 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
 115         }
 116         spin_unlock_irqrestore(&dwc->lock, flags);
 117
 118         dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
 119
 120         return ret;
 121 }
 122
 123 static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc)
 124 {
 125         struct dw_desc  *child;
 126
 127         list_for_each_entry(child, &desc->tx_list, desc_node)
 128                 dma_sync_single_for_cpu(chan2parent(&dwc->chan),
 129                                 child->txd.phys, sizeof(child->lli),
 130                                 DMA_TO_DEVICE);
 131         dma_sync_single_for_cpu(chan2parent(&dwc->chan),
 132                         desc->txd.phys, sizeof(desc->lli),
 133                         DMA_TO_DEVICE);
 134 }
 135
 136 /*
 137  * Move a descriptor, including any children, to the free list.
 138  * `desc' must not be on any lists.
 139  */
 140 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
 141 {
 142         unsigned long flags;
 143
 144         if (desc) {
 145                 struct dw_desc *child;
 146
 147                 dwc_sync_desc_for_cpu(dwc, desc);
 148
 149                 spin_lock_irqsave(&dwc->lock, flags);
 150                 list_for_each_entry(child, &desc->tx_list, desc_node)
 151                         dev_vdbg(chan2dev(&dwc->chan),
 152                                         "moving child desc %p to freelist\n",
 153                                         child);
 154                 list_splice_init(&desc->tx_list, &dwc->free_list);
 155                 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
 156                 list_add(&desc->desc_node, &dwc->free_list);
 157                 spin_unlock_irqrestore(&dwc->lock, flags);
 158         }
 159 }
 160
 161 static void dwc_initialize(struct dw_dma_chan *dwc)
 162 {
 163         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
 164         struct dw_dma_slave *dws = dwc->chan.private;
 165         u32 cfghi = DWC_CFGH_FIFO_MODE;
 166         u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
 167
 168         if (dwc->initialized == true)
 169                 return;
 170
 171         if (dws) {
 172                 /*
 173                  * We need controller-specific data to set up slave
 174                  * transfers.
 175                  */
 176                 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
 177
 178                 cfghi = dws->cfg_hi;
 179                 cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
 180         } else {
 181                 if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV)
 182                         cfghi = DWC_CFGH_DST_PER(dwc->dma_sconfig.slave_id);
 183                 else if (dwc->dma_sconfig.direction == DMA_DEV_TO_MEM)
 184                         cfghi = DWC_CFGH_SRC_PER(dwc->dma_sconfig.slave_id);
 185         }
 186
 187         channel_writel(dwc, CFG_LO, cfglo);
 188         channel_writel(dwc, CFG_HI, cfghi);
 189
 190         /* Enable interrupts */
 191         channel_set_bit(dw, MASK.XFER, dwc->mask);
 192         channel_set_bit(dw, MASK.ERROR, dwc->mask);
 193
 194         dwc->initialized = true;
 195 }
 196
 197 /*----------------------------------------------------------------------*/
 198
 199 static inline unsigned int dwc_fast_fls(unsigned long long v)
 200 {
 201         /*
 202          * We can be a lot more clever here, but this should take care
 203          * of the most common optimization.
 204          */
 205         if (!(v & 7))
 206                 return 3;
 207         else if (!(v & 3))
 208                 return 2;
 209         else if (!(v & 1))
 210                 return 1;
 211         return 0;
 212 }
 213
 214 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
 215 {
 216         dev_err(chan2dev(&dwc->chan),
 217                 "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
 218                 channel_readl(dwc, SAR),
 219                 channel_readl(dwc, DAR),
 220                 channel_readl(dwc, LLP),
 221                 channel_readl(dwc, CTL_HI),
 222                 channel_readl(dwc, CTL_LO));
 223 }
 224
 225 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
 226 {
 227         channel_clear_bit(dw, CH_EN, dwc->mask);
 228         while (dma_readl(dw, CH_EN) & dwc->mask)
 229                 cpu_relax();
 230 }
 231
 232 /*----------------------------------------------------------------------*/
 233
 234 /* Perform single block transfer */
 235 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
 236                                        struct dw_desc *desc)
 237 {
 238         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 239         u32             ctllo;
 240
 241         /* Software emulation of LLP mode relies on interrupts to continue
 242          * multi block transfer. */
 243         ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
 244
 245         channel_writel(dwc, SAR, desc->lli.sar);
 246         channel_writel(dwc, DAR, desc->lli.dar);
 247         channel_writel(dwc, CTL_LO, ctllo);
 248         channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
 249         channel_set_bit(dw, CH_EN, dwc->mask);
 250
 251         /* Move pointer to next descriptor */
 252         dwc->tx_node_active = dwc->tx_node_active->next;
 253 }
 254
 255 /* Called with dwc->lock held and bh disabled */
 256 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
 257 {
 258         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 259         unsigned long   was_soft_llp;
 260
 261         /* ASSERT:  channel is idle */
 262         if (dma_readl(dw, CH_EN) & dwc->mask) {
 263                 dev_err(chan2dev(&dwc->chan),
 264                         "BUG: Attempted to start non-idle channel\n");
 265                 dwc_dump_chan_regs(dwc);
 266
 267                 /* The tasklet will hopefully advance the queue... */
 268                 return;
 269         }
 270
 271         if (dwc->nollp) {
 272                 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
 273                                                 &dwc->flags);
 274                 if (was_soft_llp) {
 275                         dev_err(chan2dev(&dwc->chan),
 276                                 "BUG: Attempted to start new LLP transfer "
 277                                 "inside ongoing one\n");
 278                         return;
 279                 }
 280
 281                 dwc_initialize(dwc);
 282
 283                 dwc->tx_list = &first->tx_list;
 284                 dwc->tx_node_active = &first->tx_list;
 285
 286                 dwc_do_single_block(dwc, first);
 287
 288                 return;
 289         }
 290
 291         dwc_initialize(dwc);
 292
 293         channel_writel(dwc, LLP, first->txd.phys);
 294         channel_writel(dwc, CTL_LO,
 295                         DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 296         channel_writel(dwc, CTL_HI, 0);
 297         channel_set_bit(dw, CH_EN, dwc->mask);
 298 }
 299
 300 /*----------------------------------------------------------------------*/
 301
 302 static void
 303 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
 304                 bool callback_required)
 305 {
 306         dma_async_tx_callback           callback = NULL;
 307         void                            *param = NULL;
 308         struct dma_async_tx_descriptor  *txd = &desc->txd;
 309         struct dw_desc                  *child;
 310         unsigned long                   flags;
 311
 312         dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 313
 314         spin_lock_irqsave(&dwc->lock, flags);
 315         dma_cookie_complete(txd);
 316         if (callback_required) {
 317                 callback = txd->callback;
 318                 param = txd->callback_param;
 319         }
 320
 321         dwc_sync_desc_for_cpu(dwc, desc);
 322
 323         /* async_tx_ack */
 324         list_for_each_entry(child, &desc->tx_list, desc_node)
 325                 async_tx_ack(&child->txd);
 326         async_tx_ack(&desc->txd);
 327
 328         list_splice_init(&desc->tx_list, &dwc->free_list);
 329         list_move(&desc->desc_node, &dwc->free_list);
 330
 331         if (!dwc->chan.private) {
 332                 struct device *parent = chan2parent(&dwc->chan);
 333                 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
 334                         if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
 335                                 dma_unmap_single(parent, desc->lli.dar,
 336                                                 desc->len, DMA_FROM_DEVICE);
 337                         else
 338                                 dma_unmap_page(parent, desc->lli.dar,
 339                                                 desc->len, DMA_FROM_DEVICE);
 340                 }
 341                 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
 342                         if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
 343                                 dma_unmap_single(parent, desc->lli.sar,
 344                                                 desc->len, DMA_TO_DEVICE);
 345                         else
 346                                 dma_unmap_page(parent, desc->lli.sar,
 347                                                 desc->len, DMA_TO_DEVICE);
 348                 }
 349         }
 350
 351         spin_unlock_irqrestore(&dwc->lock, flags);
 352
 353         if (callback)
 354                 callback(param);
 355 }
 356
 357 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
 358 {
 359         struct dw_desc *desc, *_desc;
 360         LIST_HEAD(list);
 361         unsigned long flags;
 362
 363         spin_lock_irqsave(&dwc->lock, flags);
 364         if (dma_readl(dw, CH_EN) & dwc->mask) {
 365                 dev_err(chan2dev(&dwc->chan),
 366                         "BUG: XFER bit set, but channel not idle!\n");
 367
 368                 /* Try to continue after resetting the channel... */
 369                 dwc_chan_disable(dw, dwc);
 370         }
 371
 372         /*
 373          * Submit queued descriptors ASAP, i.e. before we go through
 374          * the completed ones.
 375          */
 376         list_splice_init(&dwc->active_list, &list);
 377         if (!list_empty(&dwc->queue)) {
 378                 list_move(dwc->queue.next, &dwc->active_list);
 379                 dwc_dostart(dwc, dwc_first_active(dwc));
 380         }
 381
 382         spin_unlock_irqrestore(&dwc->lock, flags);
 383
 384         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 385                 dwc_descriptor_complete(dwc, desc, true);
 386 }
 387
 388 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 389 {
 390         dma_addr_t llp;
 391         struct dw_desc *desc, *_desc;
 392         struct dw_desc *child;
 393         u32 status_xfer;
 394         unsigned long flags;
 395
 396         spin_lock_irqsave(&dwc->lock, flags);
 397         llp = channel_readl(dwc, LLP);
 398         status_xfer = dma_readl(dw, RAW.XFER);
 399
 400         if (status_xfer & dwc->mask) {
 401                 /* Everything we've submitted is done */
 402                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 403                 spin_unlock_irqrestore(&dwc->lock, flags);
 404
 405                 dwc_complete_all(dw, dwc);
 406                 return;
 407         }
 408
 409         if (list_empty(&dwc->active_list)) {
 410                 spin_unlock_irqrestore(&dwc->lock, flags);
 411                 return;
 412         }
 413
 414         dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__,
 415                         (unsigned long long)llp);
 416
 417         list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
 418                 /* check first descriptors addr */
 419                 if (desc->txd.phys == llp) {
 420                         spin_unlock_irqrestore(&dwc->lock, flags);
 421                         return;
 422                 }
 423
 424                 /* check first descriptors llp */
 425                 if (desc->lli.llp == llp) {
 426                         /* This one is currently in progress */
 427                         spin_unlock_irqrestore(&dwc->lock, flags);
 428                         return;
 429                 }
 430
 431                 list_for_each_entry(child, &desc->tx_list, desc_node)
 432                         if (child->lli.llp == llp) {
 433                                 /* Currently in progress */
 434                                 spin_unlock_irqrestore(&dwc->lock, flags);
 435                                 return;
 436                         }
 437
 438                 /*
 439                  * No descriptors so far seem to be in progress, i.e.
 440                  * this one must be done.
 441                  */
 442                 spin_unlock_irqrestore(&dwc->lock, flags);
 443                 dwc_descriptor_complete(dwc, desc, true);
 444                 spin_lock_irqsave(&dwc->lock, flags);
 445         }
 446
 447         dev_err(chan2dev(&dwc->chan),
 448                 "BUG: All descriptors done, but channel not idle!\n");
 449
 450         /* Try to continue after resetting the channel... */
 451         dwc_chan_disable(dw, dwc);
 452
 453         if (!list_empty(&dwc->queue)) {
 454                 list_move(dwc->queue.next, &dwc->active_list);
 455                 dwc_dostart(dwc, dwc_first_active(dwc));
 456         }
 457         spin_unlock_irqrestore(&dwc->lock, flags);
 458 }
 459
 460 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
 461 {
 462         dev_crit(chan2dev(&dwc->chan), "  desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
 463                  lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
 464 }
 465
 466 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
 467 {
 468         struct dw_desc *bad_desc;
 469         struct dw_desc *child;
 470         unsigned long flags;
 471
 472         dwc_scan_descriptors(dw, dwc);
 473
 474         spin_lock_irqsave(&dwc->lock, flags);
 475
 476         /*
 477          * The descriptor currently at the head of the active list is
 478          * borked. Since we don't have any way to report errors, we'll
 479          * just have to scream loudly and try to carry on.
 480          */
 481         bad_desc = dwc_first_active(dwc);
 482         list_del_init(&bad_desc->desc_node);
 483         list_move(dwc->queue.next, dwc->active_list.prev);
 484
 485         /* Clear the error flag and try to restart the controller */
 486         dma_writel(dw, CLEAR.ERROR, dwc->mask);
 487         if (!list_empty(&dwc->active_list))
 488                 dwc_dostart(dwc, dwc_first_active(dwc));
 489
 490         /*
 491          * WARN may seem harsh, but since this only happens
 492          * when someone submits a bad physical address in a
 493          * descriptor, we should consider ourselves lucky that the
 494          * controller flagged an error instead of scribbling over
 495          * random memory locations.
 496          */
 497         dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
 498                                        "  cookie: %d\n", bad_desc->txd.cookie);
 499         dwc_dump_lli(dwc, &bad_desc->lli);
 500         list_for_each_entry(child, &bad_desc->tx_list, desc_node)
 501                 dwc_dump_lli(dwc, &child->lli);
 502
 503         spin_unlock_irqrestore(&dwc->lock, flags);
 504
 505         /* Pretend the descriptor completed successfully */
 506         dwc_descriptor_complete(dwc, bad_desc, true);
 507 }
 508
 509 /* --------------------- Cyclic DMA API extensions -------------------- */
 510
 511 inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
 512 {
 513         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 514         return channel_readl(dwc, SAR);
 515 }
 516 EXPORT_SYMBOL(dw_dma_get_src_addr);
 517
 518 inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
 519 {
 520         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 521         return channel_readl(dwc, DAR);
 522 }
 523 EXPORT_SYMBOL(dw_dma_get_dst_addr);
 524
 525 /* called with dwc->lock held and all DMAC interrupts disabled */
 526 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
 527                 u32 status_err, u32 status_xfer)
 528 {
 529         unsigned long flags;
 530
 531         if (dwc->mask) {
 532                 void (*callback)(void *param);
 533                 void *callback_param;
 534
 535                 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
 536                                 channel_readl(dwc, LLP));
 537
 538                 callback = dwc->cdesc->period_callback;
 539                 callback_param = dwc->cdesc->period_callback_param;
 540
 541                 if (callback)
 542                         callback(callback_param);
 543         }
 544
 545         /*
 546          * Error and transfer complete are highly unlikely, and will most
 547          * likely be due to a configuration error by the user.
 548          */
 549         if (unlikely(status_err & dwc->mask) ||
 550                         unlikely(status_xfer & dwc->mask)) {
 551                 int i;
 552
 553                 dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s "
 554                                 "interrupt, stopping DMA transfer\n",
 555                                 status_xfer ? "xfer" : "error");
 556
 557                 spin_lock_irqsave(&dwc->lock, flags);
 558
 559                 dwc_dump_chan_regs(dwc);
 560
 561                 dwc_chan_disable(dw, dwc);
 562
 563                 /* make sure DMA does not restart by loading a new list */
 564                 channel_writel(dwc, LLP, 0);
 565                 channel_writel(dwc, CTL_LO, 0);
 566                 channel_writel(dwc, CTL_HI, 0);
 567
 568                 dma_writel(dw, CLEAR.ERROR, dwc->mask);
 569                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 570
 571                 for (i = 0; i < dwc->cdesc->periods; i++)
 572                         dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
 573
 574                 spin_unlock_irqrestore(&dwc->lock, flags);
 575         }
 576 }
 577
 578 /* ------------------------------------------------------------------------- */
 579
 580 static void dw_dma_tasklet(unsigned long data)
 581 {
 582         struct dw_dma *dw = (struct dw_dma *)data;
 583         struct dw_dma_chan *dwc;
 584         u32 status_xfer;
 585         u32 status_err;
 586         int i;
 587
 588         status_xfer = dma_readl(dw, RAW.XFER);
 589         status_err = dma_readl(dw, RAW.ERROR);
 590
 591         dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
 592
 593         for (i = 0; i < dw->dma.chancnt; i++) {
 594                 dwc = &dw->chan[i];
 595                 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
 596                         dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
 597                 else if (status_err & (1 << i))
 598                         dwc_handle_error(dw, dwc);
 599                 else if (status_xfer & (1 << i)) {
 600                         unsigned long flags;
 601
 602                         spin_lock_irqsave(&dwc->lock, flags);
 603                         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 604                                 if (dwc->tx_node_active != dwc->tx_list) {
 605                                         struct dw_desc *desc =
 606                                                 to_dw_desc(dwc->tx_node_active);
 607
 608                                         dma_writel(dw, CLEAR.XFER, dwc->mask);
 609
 610                                         dwc_do_single_block(dwc, desc);
 611
 612                                         spin_unlock_irqrestore(&dwc->lock, flags);
 613                                         continue;
 614                                 }
 615                                 /* we are done here */
 616                                 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
 617                         }
 618                         spin_unlock_irqrestore(&dwc->lock, flags);
 619
 620                         dwc_scan_descriptors(dw, dwc);
 621                 }
 622         }
 623
 624         /*
 625          * Re-enable interrupts.
 626          */
 627         channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
 628         channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
 629 }
 630
 631 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
 632 {
 633         struct dw_dma *dw = dev_id;
 634         u32 status;
 635
 636         dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__,
 637                         dma_readl(dw, STATUS_INT));
 638
 639         /*
 640          * Just disable the interrupts. We'll turn them back on in the
 641          * softirq handler.
 642          */
 643         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
 644         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
 645
 646         status = dma_readl(dw, STATUS_INT);
 647         if (status) {
 648                 dev_err(dw->dma.dev,
 649                         "BUG: Unexpected interrupts pending: 0x%x\n",
 650                         status);
 651
 652                 /* Try to recover */
 653                 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
 654                 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
 655                 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
 656                 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
 657         }
 658
 659         tasklet_schedule(&dw->tasklet);
 660
 661         return IRQ_HANDLED;
 662 }
 663
 664 /*----------------------------------------------------------------------*/
 665
 666 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
 667 {
 668         struct dw_desc          *desc = txd_to_dw_desc(tx);
 669         struct dw_dma_chan      *dwc = to_dw_dma_chan(tx->chan);
 670         dma_cookie_t            cookie;
 671         unsigned long           flags;
 672
 673         spin_lock_irqsave(&dwc->lock, flags);
 674         cookie = dma_cookie_assign(tx);
 675
 676         /*
 677          * REVISIT: We should attempt to chain as many descriptors as
 678          * possible, perhaps even appending to those already submitted
 679          * for DMA. But this is hard to do in a race-free manner.
 680          */
 681         if (list_empty(&dwc->active_list)) {
 682                 dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__,
 683                                 desc->txd.cookie);
 684                 list_add_tail(&desc->desc_node, &dwc->active_list);
 685                 dwc_dostart(dwc, dwc_first_active(dwc));
 686         } else {
 687                 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__,
 688                                 desc->txd.cookie);
 689
 690                 list_add_tail(&desc->desc_node, &dwc->queue);
 691         }
 692
 693         spin_unlock_irqrestore(&dwc->lock, flags);
 694
 695         return cookie;
 696 }
 697
 698 static struct dma_async_tx_descriptor *
 699 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 700                 size_t len, unsigned long flags)
 701 {
 702         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 703         struct dw_dma_slave     *dws = chan->private;
 704         struct dw_desc          *desc;
 705         struct dw_desc          *first;
 706         struct dw_desc          *prev;
 707         size_t                  xfer_count;
 708         size_t                  offset;
 709         unsigned int            src_width;
 710         unsigned int            dst_width;
 711         unsigned int            data_width;
 712         u32                     ctllo;
 713
 714         dev_vdbg(chan2dev(chan),
 715                         "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__,
 716                         (unsigned long long)dest, (unsigned long long)src,
 717                         len, flags);
 718
 719         if (unlikely(!len)) {
 720                 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
 721                 return NULL;
 722         }
 723
 724         data_width = min_t(unsigned int, dwc->dw->data_width[dwc_get_sms(dws)],
 725                                          dwc->dw->data_width[dwc_get_dms(dws)]);
 726
 727         src_width = dst_width = min_t(unsigned int, data_width,
 728                                       dwc_fast_fls(src | dest | len));
 729
 730         ctllo = DWC_DEFAULT_CTLLO(chan)
 731                         | DWC_CTLL_DST_WIDTH(dst_width)
 732                         | DWC_CTLL_SRC_WIDTH(src_width)
 733                         | DWC_CTLL_DST_INC
 734                         | DWC_CTLL_SRC_INC
 735                         | DWC_CTLL_FC_M2M;
 736         prev = first = NULL;
 737
 738         for (offset = 0; offset < len; offset += xfer_count << src_width) {
 739                 xfer_count = min_t(size_t, (len - offset) >> src_width,
 740                                            dwc->block_size);
 741
 742                 desc = dwc_desc_get(dwc);
 743                 if (!desc)
 744                         goto err_desc_get;
 745
 746                 desc->lli.sar = src + offset;
 747                 desc->lli.dar = dest + offset;
 748                 desc->lli.ctllo = ctllo;
 749                 desc->lli.ctlhi = xfer_count;
 750
 751                 if (!first) {
 752                         first = desc;
 753                 } else {
 754                         prev->lli.llp = desc->txd.phys;
 755                         dma_sync_single_for_device(chan2parent(chan),
 756                                         prev->txd.phys, sizeof(prev->lli),
 757                                         DMA_TO_DEVICE);
 758                         list_add_tail(&desc->desc_node,
 759                                         &first->tx_list);
 760                 }
 761                 prev = desc;
 762         }
 763
 764
 765         if (flags & DMA_PREP_INTERRUPT)
 766                 /* Trigger interrupt after last block */
 767                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 768
 769         prev->lli.llp = 0;
 770         dma_sync_single_for_device(chan2parent(chan),
 771                         prev->txd.phys, sizeof(prev->lli),
 772                         DMA_TO_DEVICE);
 773
 774         first->txd.flags = flags;
 775         first->len = len;
 776
 777         return &first->txd;
 778
 779 err_desc_get:
 780         dwc_desc_put(dwc, first);
 781         return NULL;
 782 }
 783
 784 static struct dma_async_tx_descriptor *
 785 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 786                 unsigned int sg_len, enum dma_transfer_direction direction,
 787                 unsigned long flags, void *context)
 788 {
 789         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 790         struct dw_dma_slave     *dws = chan->private;
 791         struct dma_slave_config *sconfig = &dwc->dma_sconfig;
 792         struct dw_desc          *prev;
 793         struct dw_desc          *first;
 794         u32                     ctllo;
 795         dma_addr_t              reg;
 796         unsigned int            reg_width;
 797         unsigned int            mem_width;
 798         unsigned int            data_width;
 799         unsigned int            i;
 800         struct scatterlist      *sg;
 801         size_t                  total_len = 0;
 802
 803         dev_vdbg(chan2dev(chan), "%s\n", __func__);
 804
 805         if (unlikely(!dws || !sg_len))
 806                 return NULL;
 807
 808         prev = first = NULL;
 809
 810         switch (direction) {
 811         case DMA_MEM_TO_DEV:
 812                 reg_width = __fls(sconfig->dst_addr_width);
 813                 reg = sconfig->dst_addr;
 814                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 815                                 | DWC_CTLL_DST_WIDTH(reg_width)
 816                                 | DWC_CTLL_DST_FIX
 817                                 | DWC_CTLL_SRC_INC);
 818
 819                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
 820                         DWC_CTLL_FC(DW_DMA_FC_D_M2P);
 821
 822                 data_width = dwc->dw->data_width[dwc_get_sms(dws)];
 823
 824                 for_each_sg(sgl, sg, sg_len, i) {
 825                         struct dw_desc  *desc;
 826                         u32             len, dlen, mem;
 827
 828                         mem = sg_dma_address(sg);
 829                         len = sg_dma_len(sg);
 830
 831                         mem_width = min_t(unsigned int,
 832                                           data_width, dwc_fast_fls(mem | len));
 833
 834 slave_sg_todev_fill_desc:
 835                         desc = dwc_desc_get(dwc);
 836                         if (!desc) {
 837                                 dev_err(chan2dev(chan),
 838                                         "not enough descriptors available\n");
 839                                 goto err_desc_get;
 840                         }
 841
 842                         desc->lli.sar = mem;
 843                         desc->lli.dar = reg;
 844                         desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
 845                         if ((len >> mem_width) > dwc->block_size) {
 846                                 dlen = dwc->block_size << mem_width;
 847                                 mem += dlen;
 848                                 len -= dlen;
 849                         } else {
 850                                 dlen = len;
 851                                 len = 0;
 852                         }
 853
 854                         desc->lli.ctlhi = dlen >> mem_width;
 855
 856                         if (!first) {
 857                                 first = desc;
 858                         } else {
 859                                 prev->lli.llp = desc->txd.phys;
 860                                 dma_sync_single_for_device(chan2parent(chan),
 861                                                 prev->txd.phys,
 862                                                 sizeof(prev->lli),
 863                                                 DMA_TO_DEVICE);
 864                                 list_add_tail(&desc->desc_node,
 865                                                 &first->tx_list);
 866                         }
 867                         prev = desc;
 868                         total_len += dlen;
 869
 870                         if (len)
 871                                 goto slave_sg_todev_fill_desc;
 872                 }
 873                 break;
 874         case DMA_DEV_TO_MEM:
 875                 reg_width = __fls(sconfig->src_addr_width);
 876                 reg = sconfig->src_addr;
 877                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 878                                 | DWC_CTLL_SRC_WIDTH(reg_width)
 879                                 | DWC_CTLL_DST_INC
 880                                 | DWC_CTLL_SRC_FIX);
 881
 882                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
 883                         DWC_CTLL_FC(DW_DMA_FC_D_P2M);
 884
 885                 data_width = dwc->dw->data_width[dwc_get_dms(dws)];
 886
 887                 for_each_sg(sgl, sg, sg_len, i) {
 888                         struct dw_desc  *desc;
 889                         u32             len, dlen, mem;
 890
 891                         mem = sg_dma_address(sg);
 892                         len = sg_dma_len(sg);
 893
 894                         mem_width = min_t(unsigned int,
 895                                           data_width, dwc_fast_fls(mem | len));
 896
 897 slave_sg_fromdev_fill_desc:
 898                         desc = dwc_desc_get(dwc);
 899                         if (!desc) {
 900                                 dev_err(chan2dev(chan),
 901                                                 "not enough descriptors available\n");
 902                                 goto err_desc_get;
 903                         }
 904
 905                         desc->lli.sar = reg;
 906                         desc->lli.dar = mem;
 907                         desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
 908                         if ((len >> reg_width) > dwc->block_size) {
 909                                 dlen = dwc->block_size << reg_width;
 910                                 mem += dlen;
 911                                 len -= dlen;
 912                         } else {
 913                                 dlen = len;
 914                                 len = 0;
 915                         }
 916                         desc->lli.ctlhi = dlen >> reg_width;
 917
 918                         if (!first) {
 919                                 first = desc;
 920                         } else {
 921                                 prev->lli.llp = desc->txd.phys;
 922                                 dma_sync_single_for_device(chan2parent(chan),
 923                                                 prev->txd.phys,
 924                                                 sizeof(prev->lli),
 925                                                 DMA_TO_DEVICE);
 926                                 list_add_tail(&desc->desc_node,
 927                                                 &first->tx_list);
 928                         }
 929                         prev = desc;
 930                         total_len += dlen;
 931
 932                         if (len)
 933                                 goto slave_sg_fromdev_fill_desc;
 934                 }
 935                 break;
 936         default:
 937                 return NULL;
 938         }
 939
 940         if (flags & DMA_PREP_INTERRUPT)
 941                 /* Trigger interrupt after last block */
 942                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 943
 944         prev->lli.llp = 0;
 945         dma_sync_single_for_device(chan2parent(chan),
 946                         prev->txd.phys, sizeof(prev->lli),
 947                         DMA_TO_DEVICE);
 948
 949         first->len = total_len;
 950
 951         return &first->txd;
 952
 953 err_desc_get:
 954         dwc_desc_put(dwc, first);
 955         return NULL;
 956 }
 957
 958 /*
 959  * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
 960  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
 961  *
 962  * NOTE: burst size 2 is not supported by controller.
 963  *
 964  * This can be done by finding least significant bit set: n & (n - 1)
 965  */
 966 static inline void convert_burst(u32 *maxburst)
 967 {
 968         if (*maxburst > 1)
 969                 *maxburst = fls(*maxburst) - 2;
 970         else
 971                 *maxburst = 0;
 972 }
 973
 974 static int
 975 set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
 976 {
 977         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 978
 979         /* Check if it is chan is configured for slave transfers */
 980         if (!chan->private)
 981                 return -EINVAL;
 982
 983         memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
 984
 985         convert_burst(&dwc->dma_sconfig.src_maxburst);
 986         convert_burst(&dwc->dma_sconfig.dst_maxburst);
 987
 988         return 0;
 989 }
 990
 991 static inline void dwc_chan_pause(struct dw_dma_chan *dwc)
 992 {
 993         u32 cfglo = channel_readl(dwc, CFG_LO);
 994
 995         channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
 996         while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY))
 997                 cpu_relax();
 998
 999         dwc->paused = true;
1000 }
1001
1002 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
1003 {
1004         u32 cfglo = channel_readl(dwc, CFG_LO);
1005
1006         channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
1007
1008         dwc->paused = false;
1009 }
1010
1011 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1012                        unsigned long arg)
1013 {
1014         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1015         struct dw_dma           *dw = to_dw_dma(chan->device);
1016         struct dw_desc          *desc, *_desc;
1017         unsigned long           flags;
1018         LIST_HEAD(list);
1019
1020         if (cmd == DMA_PAUSE) {
1021                 spin_lock_irqsave(&dwc->lock, flags);
1022
1023                 dwc_chan_pause(dwc);
1024
1025                 spin_unlock_irqrestore(&dwc->lock, flags);
1026         } else if (cmd == DMA_RESUME) {
1027                 if (!dwc->paused)
1028                         return 0;
1029
1030                 spin_lock_irqsave(&dwc->lock, flags);
1031
1032                 dwc_chan_resume(dwc);
1033
1034                 spin_unlock_irqrestore(&dwc->lock, flags);
1035         } else if (cmd == DMA_TERMINATE_ALL) {
1036                 spin_lock_irqsave(&dwc->lock, flags);
1037
1038                 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1039
1040                 dwc_chan_disable(dw, dwc);
1041
1042                 dwc->paused = false;
1043
1044                 /* active_list entries will end up before queued entries */
1045                 list_splice_init(&dwc->queue, &list);
1046                 list_splice_init(&dwc->active_list, &list);
1047
1048                 spin_unlock_irqrestore(&dwc->lock, flags);
1049
1050                 /* Flush all pending and queued descriptors */
1051                 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1052                         dwc_descriptor_complete(dwc, desc, false);
1053         } else if (cmd == DMA_SLAVE_CONFIG) {
1054                 return set_runtime_config(chan, (struct dma_slave_config *)arg);
1055         } else {
1056                 return -ENXIO;
1057         }
1058
1059         return 0;
1060 }
1061
1062 static enum dma_status
1063 dwc_tx_status(struct dma_chan *chan,
1064               dma_cookie_t cookie,
1065               struct dma_tx_state *txstate)
1066 {
1067         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1068         enum dma_status         ret;
1069
1070         ret = dma_cookie_status(chan, cookie, txstate);
1071         if (ret != DMA_SUCCESS) {
1072                 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1073
1074                 ret = dma_cookie_status(chan, cookie, txstate);
1075         }
1076
1077         if (ret != DMA_SUCCESS)
1078                 dma_set_residue(txstate, dwc_first_active(dwc)->len);
1079
1080         if (dwc->paused)
1081                 return DMA_PAUSED;
1082
1083         return ret;
1084 }
1085
1086 static void dwc_issue_pending(struct dma_chan *chan)
1087 {
1088         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1089
1090         if (!list_empty(&dwc->queue))
1091                 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1092 }
1093
1094 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1095 {
1096         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1097         struct dw_dma           *dw = to_dw_dma(chan->device);
1098         struct dw_desc          *desc;
1099         int                     i;
1100         unsigned long           flags;
1101         int                     ret;
1102
1103         dev_vdbg(chan2dev(chan), "%s\n", __func__);
1104
1105         /* ASSERT:  channel is idle */
1106         if (dma_readl(dw, CH_EN) & dwc->mask) {
1107                 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1108                 return -EIO;
1109         }
1110
1111         dma_cookie_init(chan);
1112
1113         /*
1114          * NOTE: some controllers may have additional features that we
1115          * need to initialize here, like "scatter-gather" (which
1116          * doesn't mean what you think it means), and status writeback.
1117          */
1118
1119         spin_lock_irqsave(&dwc->lock, flags);
1120         i = dwc->descs_allocated;
1121         while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1122                 spin_unlock_irqrestore(&dwc->lock, flags);
1123
1124                 desc = kzalloc(sizeof(struct dw_desc), GFP_KERNEL);
1125                 if (!desc)
1126                         goto err_desc_alloc;
1127
1128                 INIT_LIST_HEAD(&desc->tx_list);
1129                 dma_async_tx_descriptor_init(&desc->txd, chan);
1130                 desc->txd.tx_submit = dwc_tx_submit;
1131                 desc->txd.flags = DMA_CTRL_ACK;
1132                 desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli,
1133                                 sizeof(desc->lli), DMA_TO_DEVICE);
1134                 ret = dma_mapping_error(chan2parent(chan), desc->txd.phys);
1135                 if (ret)
1136                         goto err_desc_alloc;
1137
1138                 dwc_desc_put(dwc, desc);
1139
1140                 spin_lock_irqsave(&dwc->lock, flags);
1141                 i = ++dwc->descs_allocated;
1142         }
1143
1144         spin_unlock_irqrestore(&dwc->lock, flags);
1145
1146         dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1147
1148         return i;
1149
1150 err_desc_alloc:
1151         kfree(desc);
1152
1153         dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1154
1155         return i;
1156 }
1157
1158 static void dwc_free_chan_resources(struct dma_chan *chan)
1159 {
1160         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1161         struct dw_dma           *dw = to_dw_dma(chan->device);
1162         struct dw_desc          *desc, *_desc;
1163         unsigned long           flags;
1164         LIST_HEAD(list);
1165
1166         dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1167                         dwc->descs_allocated);
1168
1169         /* ASSERT:  channel is idle */
1170         BUG_ON(!list_empty(&dwc->active_list));
1171         BUG_ON(!list_empty(&dwc->queue));
1172         BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1173
1174         spin_lock_irqsave(&dwc->lock, flags);
1175         list_splice_init(&dwc->free_list, &list);
1176         dwc->descs_allocated = 0;
1177         dwc->initialized = false;
1178
1179         /* Disable interrupts */
1180         channel_clear_bit(dw, MASK.XFER, dwc->mask);
1181         channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1182
1183         spin_unlock_irqrestore(&dwc->lock, flags);
1184
1185         list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1186                 dev_vdbg(chan2dev(chan), "  freeing descriptor %p\n", desc);
1187                 dma_unmap_single(chan2parent(chan), desc->txd.phys,
1188                                 sizeof(desc->lli), DMA_TO_DEVICE);
1189                 kfree(desc);
1190         }
1191
1192         dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1193 }
1194
1195 bool dw_dma_generic_filter(struct dma_chan *chan, void *param)
1196 {
1197         struct dw_dma *dw = to_dw_dma(chan->device);
1198         static struct dw_dma *last_dw;
1199         static char *last_bus_id;
1200         int i = -1;
1201
1202         /*
1203          * dmaengine framework calls this routine for all channels of all dma
1204          * controller, until true is returned. If 'param' bus_id is not
1205          * registered with a dma controller (dw), then there is no need of
1206          * running below function for all channels of dw.
1207          *
1208          * This block of code does this by saving the parameters of last
1209          * failure. If dw and param are same, i.e. trying on same dw with
1210          * different channel, return false.
1211          */
1212         if ((last_dw == dw) && (last_bus_id == param))
1213                 return false;
1214         /*
1215          * Return true:
1216          * - If dw_dma's platform data is not filled with slave info, then all
1217          *   dma controllers are fine for transfer.
1218          * - Or if param is NULL
1219          */
1220         if (!dw->sd || !param)
1221                 return true;
1222
1223         while (++i < dw->sd_count) {
1224                 if (!strcmp(dw->sd[i].bus_id, param)) {
1225                         chan->private = &dw->sd[i];
1226                         last_dw = NULL;
1227                         last_bus_id = NULL;
1228
1229                         return true;
1230                 }
1231         }
1232
1233         last_dw = dw;
1234         last_bus_id = param;
1235         return false;
1236 }
1237 EXPORT_SYMBOL(dw_dma_generic_filter);
1238
1239 /* --------------------- Cyclic DMA API extensions -------------------- */
1240
1241 /**
1242  * dw_dma_cyclic_start - start the cyclic DMA transfer
1243  * @chan: the DMA channel to start
1244  *
1245  * Must be called with soft interrupts disabled. Returns zero on success or
1246  * -errno on failure.
1247  */
1248 int dw_dma_cyclic_start(struct dma_chan *chan)
1249 {
1250         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1251         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1252         unsigned long           flags;
1253
1254         if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1255                 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1256                 return -ENODEV;
1257         }
1258
1259         spin_lock_irqsave(&dwc->lock, flags);
1260
1261         /* assert channel is idle */
1262         if (dma_readl(dw, CH_EN) & dwc->mask) {
1263                 dev_err(chan2dev(&dwc->chan),
1264                         "BUG: Attempted to start non-idle channel\n");
1265                 dwc_dump_chan_regs(dwc);
1266                 spin_unlock_irqrestore(&dwc->lock, flags);
1267                 return -EBUSY;
1268         }
1269
1270         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1271         dma_writel(dw, CLEAR.XFER, dwc->mask);
1272
1273         /* setup DMAC channel registers */
1274         channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1275         channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1276         channel_writel(dwc, CTL_HI, 0);
1277
1278         channel_set_bit(dw, CH_EN, dwc->mask);
1279
1280         spin_unlock_irqrestore(&dwc->lock, flags);
1281
1282         return 0;
1283 }
1284 EXPORT_SYMBOL(dw_dma_cyclic_start);
1285
1286 /**
1287  * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1288  * @chan: the DMA channel to stop
1289  *
1290  * Must be called with soft interrupts disabled.
1291  */
1292 void dw_dma_cyclic_stop(struct dma_chan *chan)
1293 {
1294         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1295         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1296         unsigned long           flags;
1297
1298         spin_lock_irqsave(&dwc->lock, flags);
1299
1300         dwc_chan_disable(dw, dwc);
1301
1302         spin_unlock_irqrestore(&dwc->lock, flags);
1303 }
1304 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1305
1306 /**
1307  * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1308  * @chan: the DMA channel to prepare
1309  * @buf_addr: physical DMA address where the buffer starts
1310  * @buf_len: total number of bytes for the entire buffer
1311  * @period_len: number of bytes for each period
1312  * @direction: transfer direction, to or from device
1313  *
1314  * Must be called before trying to start the transfer. Returns a valid struct
1315  * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1316  */
1317 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1318                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1319                 enum dma_transfer_direction direction)
1320 {
1321         struct dw_dma_chan              *dwc = to_dw_dma_chan(chan);
1322         struct dma_slave_config         *sconfig = &dwc->dma_sconfig;
1323         struct dw_cyclic_desc           *cdesc;
1324         struct dw_cyclic_desc           *retval = NULL;
1325         struct dw_desc                  *desc;
1326         struct dw_desc                  *last = NULL;
1327         unsigned long                   was_cyclic;
1328         unsigned int                    reg_width;
1329         unsigned int                    periods;
1330         unsigned int                    i;
1331         unsigned long                   flags;
1332
1333         spin_lock_irqsave(&dwc->lock, flags);
1334         if (dwc->nollp) {
1335                 spin_unlock_irqrestore(&dwc->lock, flags);
1336                 dev_dbg(chan2dev(&dwc->chan),
1337                                 "channel doesn't support LLP transfers\n");
1338                 return ERR_PTR(-EINVAL);
1339         }
1340
1341         if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1342                 spin_unlock_irqrestore(&dwc->lock, flags);
1343                 dev_dbg(chan2dev(&dwc->chan),
1344                                 "queue and/or active list are not empty\n");
1345                 return ERR_PTR(-EBUSY);
1346         }
1347
1348         was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1349         spin_unlock_irqrestore(&dwc->lock, flags);
1350         if (was_cyclic) {
1351                 dev_dbg(chan2dev(&dwc->chan),
1352                                 "channel already prepared for cyclic DMA\n");
1353                 return ERR_PTR(-EBUSY);
1354         }
1355
1356         retval = ERR_PTR(-EINVAL);
1357
1358         if (direction == DMA_MEM_TO_DEV)
1359                 reg_width = __ffs(sconfig->dst_addr_width);
1360         else
1361                 reg_width = __ffs(sconfig->src_addr_width);
1362
1363         periods = buf_len / period_len;
1364
1365         /* Check for too big/unaligned periods and unaligned DMA buffer. */
1366         if (period_len > (dwc->block_size << reg_width))
1367                 goto out_err;
1368         if (unlikely(period_len & ((1 << reg_width) - 1)))
1369                 goto out_err;
1370         if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1371                 goto out_err;
1372         if (unlikely(!(direction & (DMA_MEM_TO_DEV | DMA_DEV_TO_MEM))))
1373                 goto out_err;
1374
1375         retval = ERR_PTR(-ENOMEM);
1376
1377         if (periods > NR_DESCS_PER_CHANNEL)
1378                 goto out_err;
1379
1380         cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1381         if (!cdesc)
1382                 goto out_err;
1383
1384         cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1385         if (!cdesc->desc)
1386                 goto out_err_alloc;
1387
1388         for (i = 0; i < periods; i++) {
1389                 desc = dwc_desc_get(dwc);
1390                 if (!desc)
1391                         goto out_err_desc_get;
1392
1393                 switch (direction) {
1394                 case DMA_MEM_TO_DEV:
1395                         desc->lli.dar = sconfig->dst_addr;
1396                         desc->lli.sar = buf_addr + (period_len * i);
1397                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1398                                         | DWC_CTLL_DST_WIDTH(reg_width)
1399                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1400                                         | DWC_CTLL_DST_FIX
1401                                         | DWC_CTLL_SRC_INC
1402                                         | DWC_CTLL_INT_EN);
1403
1404                         desc->lli.ctllo |= sconfig->device_fc ?
1405                                 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1406                                 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1407
1408                         break;
1409                 case DMA_DEV_TO_MEM:
1410                         desc->lli.dar = buf_addr + (period_len * i);
1411                         desc->lli.sar = sconfig->src_addr;
1412                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1413                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1414                                         | DWC_CTLL_DST_WIDTH(reg_width)
1415                                         | DWC_CTLL_DST_INC
1416                                         | DWC_CTLL_SRC_FIX
1417                                         | DWC_CTLL_INT_EN);
1418
1419                         desc->lli.ctllo |= sconfig->device_fc ?
1420                                 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1421                                 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1422
1423                         break;
1424                 default:
1425                         break;
1426                 }
1427
1428                 desc->lli.ctlhi = (period_len >> reg_width);
1429                 cdesc->desc[i] = desc;
1430
1431                 if (last) {
1432                         last->lli.llp = desc->txd.phys;
1433                         dma_sync_single_for_device(chan2parent(chan),
1434                                         last->txd.phys, sizeof(last->lli),
1435                                         DMA_TO_DEVICE);
1436                 }
1437
1438                 last = desc;
1439         }
1440
1441         /* lets make a cyclic list */
1442         last->lli.llp = cdesc->desc[0]->txd.phys;
1443         dma_sync_single_for_device(chan2parent(chan), last->txd.phys,
1444                         sizeof(last->lli), DMA_TO_DEVICE);
1445
1446         dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu "
1447                         "period %zu periods %d\n", (unsigned long long)buf_addr,
1448                         buf_len, period_len, periods);
1449
1450         cdesc->periods = periods;
1451         dwc->cdesc = cdesc;
1452
1453         return cdesc;
1454
1455 out_err_desc_get:
1456         while (i--)
1457                 dwc_desc_put(dwc, cdesc->desc[i]);
1458 out_err_alloc:
1459         kfree(cdesc);
1460 out_err:
1461         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1462         return (struct dw_cyclic_desc *)retval;
1463 }
1464 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1465
1466 /**
1467  * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1468  * @chan: the DMA channel to free
1469  */
1470 void dw_dma_cyclic_free(struct dma_chan *chan)
1471 {
1472         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1473         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1474         struct dw_cyclic_desc   *cdesc = dwc->cdesc;
1475         int                     i;
1476         unsigned long           flags;
1477
1478         dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1479
1480         if (!cdesc)
1481                 return;
1482
1483         spin_lock_irqsave(&dwc->lock, flags);
1484
1485         dwc_chan_disable(dw, dwc);
1486
1487         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1488         dma_writel(dw, CLEAR.XFER, dwc->mask);
1489
1490         spin_unlock_irqrestore(&dwc->lock, flags);
1491
1492         for (i = 0; i < cdesc->periods; i++)
1493                 dwc_desc_put(dwc, cdesc->desc[i]);
1494
1495         kfree(cdesc->desc);
1496         kfree(cdesc);
1497
1498         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1499 }
1500 EXPORT_SYMBOL(dw_dma_cyclic_free);
1501
1502 /*----------------------------------------------------------------------*/
1503
1504 static void dw_dma_off(struct dw_dma *dw)
1505 {
1506         int i;
1507
1508         dma_writel(dw, CFG, 0);
1509
1510         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1511         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1512         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1513         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1514
1515         while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1516                 cpu_relax();
1517
1518         for (i = 0; i < dw->dma.chancnt; i++)
1519                 dw->chan[i].initialized = false;
1520 }
1521
1522 #ifdef CONFIG_OF
1523 static struct dw_dma_platform_data *
1524 dw_dma_parse_dt(struct platform_device *pdev)
1525 {
1526         struct device_node *sn, *cn, *np = pdev->dev.of_node;
1527         struct dw_dma_platform_data *pdata;
1528         struct dw_dma_slave *sd;
1529         u32 tmp, arr[4];
1530
1531         if (!np) {
1532                 dev_err(&pdev->dev, "Missing DT data\n");
1533                 return NULL;
1534         }
1535
1536         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1537         if (!pdata)
1538                 return NULL;
1539
1540         if (of_property_read_u32(np, "nr_channels", &pdata->nr_channels))
1541                 return NULL;
1542
1543         if (of_property_read_bool(np, "is_private"))
1544                 pdata->is_private = true;
1545
1546         if (!of_property_read_u32(np, "chan_allocation_order", &tmp))
1547                 pdata->chan_allocation_order = (unsigned char)tmp;
1548
1549         if (!of_property_read_u32(np, "chan_priority", &tmp))
1550                 pdata->chan_priority = tmp;
1551
1552         if (!of_property_read_u32(np, "block_size", &tmp))
1553                 pdata->block_size = tmp;
1554
1555         if (!of_property_read_u32(np, "nr_masters", &tmp)) {
1556                 if (tmp > 4)
1557                         return NULL;
1558
1559                 pdata->nr_masters = tmp;
1560         }
1561
1562         if (!of_property_read_u32_array(np, "data_width", arr,
1563                                 pdata->nr_masters))
1564                 for (tmp = 0; tmp < pdata->nr_masters; tmp++)
1565                         pdata->data_width[tmp] = arr[tmp];
1566
1567         /* parse slave data */
1568         sn = of_find_node_by_name(np, "slave_info");
1569         if (!sn)
1570                 return pdata;
1571
1572         /* calculate number of slaves */
1573         tmp = of_get_child_count(sn);
1574         if (!tmp)
1575                 return NULL;
1576
1577         sd = devm_kzalloc(&pdev->dev, sizeof(*sd) * tmp, GFP_KERNEL);
1578         if (!sd)
1579                 return NULL;
1580
1581         pdata->sd = sd;
1582         pdata->sd_count = tmp;
1583
1584         for_each_child_of_node(sn, cn) {
1585                 sd->dma_dev = &pdev->dev;
1586                 of_property_read_string(cn, "bus_id", &sd->bus_id);
1587                 of_property_read_u32(cn, "cfg_hi", &sd->cfg_hi);
1588                 of_property_read_u32(cn, "cfg_lo", &sd->cfg_lo);
1589                 if (!of_property_read_u32(cn, "src_master", &tmp))
1590                         sd->src_master = tmp;
1591
1592                 if (!of_property_read_u32(cn, "dst_master", &tmp))
1593                         sd->dst_master = tmp;
1594                 sd++;
1595         }
1596
1597         return pdata;
1598 }
1599 #else
1600 static inline struct dw_dma_platform_data *
1601 dw_dma_parse_dt(struct platform_device *pdev)
1602 {
1603         return NULL;
1604 }
1605 #endif
1606
1607 static int dw_probe(struct platform_device *pdev)
1608 {
1609         struct dw_dma_platform_data *pdata;
1610         struct resource         *io;
1611         struct dw_dma           *dw;
1612         size_t                  size;
1613         void __iomem            *regs;
1614         bool                    autocfg;
1615         unsigned int            dw_params;
1616         unsigned int            nr_channels;
1617         unsigned int            max_blk_size = 0;
1618         int                     irq;
1619         int                     err;
1620         int                     i;
1621
1622         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1623         if (!io)
1624                 return -EINVAL;
1625
1626         irq = platform_get_irq(pdev, 0);
1627         if (irq < 0)
1628                 return irq;
1629
1630         regs = devm_request_and_ioremap(&pdev->dev, io);
1631         if (!regs)
1632                 return -EBUSY;
1633
1634         dw_params = dma_read_byaddr(regs, DW_PARAMS);
1635         autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1636
1637         pdata = dev_get_platdata(&pdev->dev);
1638         if (!pdata)
1639                 pdata = dw_dma_parse_dt(pdev);
1640
1641         if (!pdata && autocfg) {
1642                 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1643                 if (!pdata)
1644                         return -ENOMEM;
1645
1646                 /* Fill platform data with the default values */
1647                 pdata->is_private = true;
1648                 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1649                 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1650         } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
1651                 return -EINVAL;
1652
1653         if (autocfg)
1654                 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
1655         else
1656                 nr_channels = pdata->nr_channels;
1657
1658         size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan);
1659         dw = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1660         if (!dw)
1661                 return -ENOMEM;
1662
1663         dw->clk = devm_clk_get(&pdev->dev, "hclk");
1664         if (IS_ERR(dw->clk))
1665                 return PTR_ERR(dw->clk);
1666         clk_prepare_enable(dw->clk);
1667
1668         dw->regs = regs;
1669         dw->sd = pdata->sd;
1670         dw->sd_count = pdata->sd_count;
1671
1672         /* get hardware configuration parameters */
1673         if (autocfg) {
1674                 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1675
1676                 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1677                 for (i = 0; i < dw->nr_masters; i++) {
1678                         dw->data_width[i] =
1679                                 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1680                 }
1681         } else {
1682                 dw->nr_masters = pdata->nr_masters;
1683                 memcpy(dw->data_width, pdata->data_width, 4);
1684         }
1685
1686         /* Calculate all channel mask before DMA setup */
1687         dw->all_chan_mask = (1 << nr_channels) - 1;
1688
1689         /* force dma off, just in case */
1690         dw_dma_off(dw);
1691
1692         /* disable BLOCK interrupts as well */
1693         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1694
1695         err = devm_request_irq(&pdev->dev, irq, dw_dma_interrupt, 0,
1696                                "dw_dmac", dw);
1697         if (err)
1698                 return err;
1699
1700         platform_set_drvdata(pdev, dw);
1701
1702         tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1703
1704         INIT_LIST_HEAD(&dw->dma.channels);
1705         for (i = 0; i < nr_channels; i++) {
1706                 struct dw_dma_chan      *dwc = &dw->chan[i];
1707                 int                     r = nr_channels - i - 1;
1708
1709                 dwc->chan.device = &dw->dma;
1710                 dma_cookie_init(&dwc->chan);
1711                 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1712                         list_add_tail(&dwc->chan.device_node,
1713                                         &dw->dma.channels);
1714                 else
1715                         list_add(&dwc->chan.device_node, &dw->dma.channels);
1716
1717                 /* 7 is highest priority & 0 is lowest. */
1718                 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1719                         dwc->priority = r;
1720                 else
1721                         dwc->priority = i;
1722
1723                 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1724                 spin_lock_init(&dwc->lock);
1725                 dwc->mask = 1 << i;
1726
1727                 INIT_LIST_HEAD(&dwc->active_list);
1728                 INIT_LIST_HEAD(&dwc->queue);
1729                 INIT_LIST_HEAD(&dwc->free_list);
1730
1731                 channel_clear_bit(dw, CH_EN, dwc->mask);
1732
1733                 dwc->dw = dw;
1734
1735                 /* hardware configuration */
1736                 if (autocfg) {
1737                         unsigned int dwc_params;
1738
1739                         dwc_params = dma_read_byaddr(regs + r * sizeof(u32),
1740                                                      DWC_PARAMS);
1741
1742                         /* Decode maximum block size for given channel. The
1743                          * stored 4 bit value represents blocks from 0x00 for 3
1744                          * up to 0x0a for 4095. */
1745                         dwc->block_size =
1746                                 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1747                         dwc->nollp =
1748                                 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1749                 } else {
1750                         dwc->block_size = pdata->block_size;
1751
1752                         /* Check if channel supports multi block transfer */
1753                         channel_writel(dwc, LLP, 0xfffffffc);
1754                         dwc->nollp =
1755                                 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1756                         channel_writel(dwc, LLP, 0);
1757                 }
1758         }
1759
1760         /* Clear all interrupts on all channels. */
1761         dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1762         dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1763         dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1764         dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1765         dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1766
1767         dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1768         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1769         if (pdata->is_private)
1770                 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1771         dw->dma.dev = &pdev->dev;
1772         dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1773         dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1774
1775         dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1776
1777         dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1778         dw->dma.device_control = dwc_control;
1779
1780         dw->dma.device_tx_status = dwc_tx_status;
1781         dw->dma.device_issue_pending = dwc_issue_pending;
1782
1783         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1784
1785         dev_info(&pdev->dev, "DesignWare DMA Controller, %d channels\n",
1786                  nr_channels);
1787
1788         dma_async_device_register(&dw->dma);
1789
1790         return 0;
1791 }
1792
1793 static int __devexit dw_remove(struct platform_device *pdev)
1794 {
1795         struct dw_dma           *dw = platform_get_drvdata(pdev);
1796         struct dw_dma_chan      *dwc, *_dwc;
1797
1798         dw_dma_off(dw);
1799         dma_async_device_unregister(&dw->dma);
1800
1801         tasklet_kill(&dw->tasklet);
1802
1803         list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1804                         chan.device_node) {
1805                 list_del(&dwc->chan.device_node);
1806                 channel_clear_bit(dw, CH_EN, dwc->mask);
1807         }
1808
1809         return 0;
1810 }
1811
1812 static void dw_shutdown(struct platform_device *pdev)
1813 {
1814         struct dw_dma   *dw = platform_get_drvdata(pdev);
1815
1816         dw_dma_off(dw);
1817         clk_disable_unprepare(dw->clk);
1818 }
1819
1820 static int dw_suspend_noirq(struct device *dev)
1821 {
1822         struct platform_device *pdev = to_platform_device(dev);
1823         struct dw_dma   *dw = platform_get_drvdata(pdev);
1824
1825         dw_dma_off(dw);
1826         clk_disable_unprepare(dw->clk);
1827
1828         return 0;
1829 }
1830
1831 static int dw_resume_noirq(struct device *dev)
1832 {
1833         struct platform_device *pdev = to_platform_device(dev);
1834         struct dw_dma   *dw = platform_get_drvdata(pdev);
1835
1836         clk_prepare_enable(dw->clk);
1837         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1838
1839         return 0;
1840 }
1841
1842 static const struct dev_pm_ops dw_dev_pm_ops = {
1843         .suspend_noirq = dw_suspend_noirq,
1844         .resume_noirq = dw_resume_noirq,
1845         .freeze_noirq = dw_suspend_noirq,
1846         .thaw_noirq = dw_resume_noirq,
1847         .restore_noirq = dw_resume_noirq,
1848         .poweroff_noirq = dw_suspend_noirq,
1849 };
1850
1851 #ifdef CONFIG_OF
1852 static const struct of_device_id dw_dma_id_table[] = {
1853         { .compatible = "snps,dma-spear1340" },
1854         {}
1855 };
1856 MODULE_DEVICE_TABLE(of, dw_dma_id_table);
1857 #endif
1858
1859 static struct platform_driver dw_driver = {
1860         .remove         = dw_remove,
1861         .shutdown       = dw_shutdown,
1862         .driver = {
1863                 .name   = "dw_dmac",
1864                 .pm     = &dw_dev_pm_ops,
1865                 .of_match_table = of_match_ptr(dw_dma_id_table),
1866         },
1867 };
1868
1869 static int __init dw_init(void)
1870 {
1871         return platform_driver_probe(&dw_driver, dw_probe);
1872 }
1873 subsys_initcall(dw_init);
1874
1875 static void __exit dw_exit(void)
1876 {
1877         platform_driver_unregister(&dw_driver);
1878 }
1879 module_exit(dw_exit);
1880
1881 MODULE_LICENSE("GPL v2");
1882 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
1883 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1884 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");