drivers/dma/dw_dmac.c

   1 /*
   2  * Core driver for the Synopsys DesignWare DMA Controller
   3  *
   4  * Copyright (C) 2007-2008 Atmel Corporation
   5  * Copyright (C) 2010-2011 ST Microelectronics
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/dmapool.h>
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/io.h>
  21 #include <linux/of.h>
  22 #include <linux/mm.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/slab.h>
  26
  27 #include "dw_dmac_regs.h"
  28 #include "dmaengine.h"
  29
  30 /*
  31  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
  32  * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
  33  * of which use ARM any more).  See the "Databook" from Synopsys for
  34  * information beyond what licensees probably provide.
  35  *
  36  * The driver has currently been tested only with the Atmel AT32AP7000,
  37  * which does not support descriptor writeback.
  38  */
  39
  40 static inline unsigned int dwc_get_dms(struct dw_dma_slave *slave)
  41 {
  42         return slave ? slave->dst_master : 0;
  43 }
  44
  45 static inline unsigned int dwc_get_sms(struct dw_dma_slave *slave)
  46 {
  47         return slave ? slave->src_master : 1;
  48 }
  49
  50 #define SRC_MASTER      0
  51 #define DST_MASTER      1
  52
  53 static inline unsigned int dwc_get_master(struct dma_chan *chan, int master)
  54 {
  55         struct dw_dma *dw = to_dw_dma(chan->device);
  56         struct dw_dma_slave *dws = chan->private;
  57         unsigned int m;
  58
  59         if (master == SRC_MASTER)
  60                 m = dwc_get_sms(dws);
  61         else
  62                 m = dwc_get_dms(dws);
  63
  64         return min_t(unsigned int, dw->nr_masters - 1, m);
  65 }
  66
  67 #define DWC_DEFAULT_CTLLO(_chan) ({                             \
  68                 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan);       \
  69                 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
  70                 bool _is_slave = is_slave_direction(_dwc->direction);   \
  71                 int _dms = dwc_get_master(_chan, DST_MASTER);           \
  72                 int _sms = dwc_get_master(_chan, SRC_MASTER);           \
  73                 u8 _smsize = _is_slave ? _sconfig->src_maxburst :       \
  74                         DW_DMA_MSIZE_16;                        \
  75                 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst :       \
  76                         DW_DMA_MSIZE_16;                        \
  77                                                                 \
  78                 (DWC_CTLL_DST_MSIZE(_dmsize)                    \
  79                  | DWC_CTLL_SRC_MSIZE(_smsize)                  \
  80                  | DWC_CTLL_LLP_D_EN                            \
  81                  | DWC_CTLL_LLP_S_EN                            \
  82                  | DWC_CTLL_DMS(_dms)                           \
  83                  | DWC_CTLL_SMS(_sms));                         \
  84         })
  85
  86 /*
  87  * Number of descriptors to allocate for each channel. This should be
  88  * made configurable somehow; preferably, the clients (at least the
  89  * ones using slave transfers) should be able to give us a hint.
  90  */
  91 #define NR_DESCS_PER_CHANNEL    64
  92
  93 static inline unsigned int dwc_get_data_width(struct dma_chan *chan, int master)
  94 {
  95         struct dw_dma *dw = to_dw_dma(chan->device);
  96
  97         return dw->data_width[dwc_get_master(chan, master)];
  98 }
  99
 100 /*----------------------------------------------------------------------*/
 101
 102 static struct device *chan2dev(struct dma_chan *chan)
 103 {
 104         return &chan->dev->device;
 105 }
 106 static struct device *chan2parent(struct dma_chan *chan)
 107 {
 108         return chan->dev->device.parent;
 109 }
 110
 111 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
 112 {
 113         return to_dw_desc(dwc->active_list.next);
 114 }
 115
 116 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
 117 {
 118         struct dw_desc *desc, *_desc;
 119         struct dw_desc *ret = NULL;
 120         unsigned int i = 0;
 121         unsigned long flags;
 122
 123         spin_lock_irqsave(&dwc->lock, flags);
 124         list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
 125                 i++;
 126                 if (async_tx_test_ack(&desc->txd)) {
 127                         list_del(&desc->desc_node);
 128                         ret = desc;
 129                         break;
 130                 }
 131                 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
 132         }
 133         spin_unlock_irqrestore(&dwc->lock, flags);
 134
 135         dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
 136
 137         return ret;
 138 }
 139
 140 /*
 141  * Move a descriptor, including any children, to the free list.
 142  * `desc' must not be on any lists.
 143  */
 144 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
 145 {
 146         unsigned long flags;
 147
 148         if (desc) {
 149                 struct dw_desc *child;
 150
 151                 spin_lock_irqsave(&dwc->lock, flags);
 152                 list_for_each_entry(child, &desc->tx_list, desc_node)
 153                         dev_vdbg(chan2dev(&dwc->chan),
 154                                         "moving child desc %p to freelist\n",
 155                                         child);
 156                 list_splice_init(&desc->tx_list, &dwc->free_list);
 157                 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
 158                 list_add(&desc->desc_node, &dwc->free_list);
 159                 spin_unlock_irqrestore(&dwc->lock, flags);
 160         }
 161 }
 162
 163 static void dwc_initialize(struct dw_dma_chan *dwc)
 164 {
 165         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
 166         struct dw_dma_slave *dws = dwc->chan.private;
 167         u32 cfghi = DWC_CFGH_FIFO_MODE;
 168         u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
 169
 170         if (dwc->initialized == true)
 171                 return;
 172
 173         if (dws) {
 174                 /*
 175                  * We need controller-specific data to set up slave
 176                  * transfers.
 177                  */
 178                 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
 179
 180                 cfghi = dws->cfg_hi;
 181                 cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
 182         } else {
 183                 if (dwc->direction == DMA_MEM_TO_DEV)
 184                         cfghi = DWC_CFGH_DST_PER(dwc->dma_sconfig.slave_id);
 185                 else if (dwc->direction == DMA_DEV_TO_MEM)
 186                         cfghi = DWC_CFGH_SRC_PER(dwc->dma_sconfig.slave_id);
 187         }
 188
 189         channel_writel(dwc, CFG_LO, cfglo);
 190         channel_writel(dwc, CFG_HI, cfghi);
 191
 192         /* Enable interrupts */
 193         channel_set_bit(dw, MASK.XFER, dwc->mask);
 194         channel_set_bit(dw, MASK.ERROR, dwc->mask);
 195
 196         dwc->initialized = true;
 197 }
 198
 199 /*----------------------------------------------------------------------*/
 200
 201 static inline unsigned int dwc_fast_fls(unsigned long long v)
 202 {
 203         /*
 204          * We can be a lot more clever here, but this should take care
 205          * of the most common optimization.
 206          */
 207         if (!(v & 7))
 208                 return 3;
 209         else if (!(v & 3))
 210                 return 2;
 211         else if (!(v & 1))
 212                 return 1;
 213         return 0;
 214 }
 215
 216 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
 217 {
 218         dev_err(chan2dev(&dwc->chan),
 219                 "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
 220                 channel_readl(dwc, SAR),
 221                 channel_readl(dwc, DAR),
 222                 channel_readl(dwc, LLP),
 223                 channel_readl(dwc, CTL_HI),
 224                 channel_readl(dwc, CTL_LO));
 225 }
 226
 227 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
 228 {
 229         channel_clear_bit(dw, CH_EN, dwc->mask);
 230         while (dma_readl(dw, CH_EN) & dwc->mask)
 231                 cpu_relax();
 232 }
 233
 234 /*----------------------------------------------------------------------*/
 235
 236 /* Perform single block transfer */
 237 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
 238                                        struct dw_desc *desc)
 239 {
 240         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 241         u32             ctllo;
 242
 243         /* Software emulation of LLP mode relies on interrupts to continue
 244          * multi block transfer. */
 245         ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
 246
 247         channel_writel(dwc, SAR, desc->lli.sar);
 248         channel_writel(dwc, DAR, desc->lli.dar);
 249         channel_writel(dwc, CTL_LO, ctllo);
 250         channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
 251         channel_set_bit(dw, CH_EN, dwc->mask);
 252
 253         /* Move pointer to next descriptor */
 254         dwc->tx_node_active = dwc->tx_node_active->next;
 255 }
 256
 257 /* Called with dwc->lock held and bh disabled */
 258 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
 259 {
 260         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 261         unsigned long   was_soft_llp;
 262
 263         /* ASSERT:  channel is idle */
 264         if (dma_readl(dw, CH_EN) & dwc->mask) {
 265                 dev_err(chan2dev(&dwc->chan),
 266                         "BUG: Attempted to start non-idle channel\n");
 267                 dwc_dump_chan_regs(dwc);
 268
 269                 /* The tasklet will hopefully advance the queue... */
 270                 return;
 271         }
 272
 273         if (dwc->nollp) {
 274                 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
 275                                                 &dwc->flags);
 276                 if (was_soft_llp) {
 277                         dev_err(chan2dev(&dwc->chan),
 278                                 "BUG: Attempted to start new LLP transfer "
 279                                 "inside ongoing one\n");
 280                         return;
 281                 }
 282
 283                 dwc_initialize(dwc);
 284
 285                 dwc->tx_list = &first->tx_list;
 286                 dwc->tx_node_active = &first->tx_list;
 287
 288                 dwc_do_single_block(dwc, first);
 289
 290                 return;
 291         }
 292
 293         dwc_initialize(dwc);
 294
 295         channel_writel(dwc, LLP, first->txd.phys);
 296         channel_writel(dwc, CTL_LO,
 297                         DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 298         channel_writel(dwc, CTL_HI, 0);
 299         channel_set_bit(dw, CH_EN, dwc->mask);
 300 }
 301
 302 /*----------------------------------------------------------------------*/
 303
 304 static void
 305 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
 306                 bool callback_required)
 307 {
 308         dma_async_tx_callback           callback = NULL;
 309         void                            *param = NULL;
 310         struct dma_async_tx_descriptor  *txd = &desc->txd;
 311         struct dw_desc                  *child;
 312         unsigned long                   flags;
 313
 314         dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 315
 316         spin_lock_irqsave(&dwc->lock, flags);
 317         dma_cookie_complete(txd);
 318         if (callback_required) {
 319                 callback = txd->callback;
 320                 param = txd->callback_param;
 321         }
 322
 323         /* async_tx_ack */
 324         list_for_each_entry(child, &desc->tx_list, desc_node)
 325                 async_tx_ack(&child->txd);
 326         async_tx_ack(&desc->txd);
 327
 328         list_splice_init(&desc->tx_list, &dwc->free_list);
 329         list_move(&desc->desc_node, &dwc->free_list);
 330
 331         if (!is_slave_direction(dwc->direction)) {
 332                 struct device *parent = chan2parent(&dwc->chan);
 333                 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
 334                         if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
 335                                 dma_unmap_single(parent, desc->lli.dar,
 336                                                 desc->len, DMA_FROM_DEVICE);
 337                         else
 338                                 dma_unmap_page(parent, desc->lli.dar,
 339                                                 desc->len, DMA_FROM_DEVICE);
 340                 }
 341                 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
 342                         if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
 343                                 dma_unmap_single(parent, desc->lli.sar,
 344                                                 desc->len, DMA_TO_DEVICE);
 345                         else
 346                                 dma_unmap_page(parent, desc->lli.sar,
 347                                                 desc->len, DMA_TO_DEVICE);
 348                 }
 349         }
 350
 351         spin_unlock_irqrestore(&dwc->lock, flags);
 352
 353         if (callback)
 354                 callback(param);
 355 }
 356
 357 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
 358 {
 359         struct dw_desc *desc, *_desc;
 360         LIST_HEAD(list);
 361         unsigned long flags;
 362
 363         spin_lock_irqsave(&dwc->lock, flags);
 364         if (dma_readl(dw, CH_EN) & dwc->mask) {
 365                 dev_err(chan2dev(&dwc->chan),
 366                         "BUG: XFER bit set, but channel not idle!\n");
 367
 368                 /* Try to continue after resetting the channel... */
 369                 dwc_chan_disable(dw, dwc);
 370         }
 371
 372         /*
 373          * Submit queued descriptors ASAP, i.e. before we go through
 374          * the completed ones.
 375          */
 376         list_splice_init(&dwc->active_list, &list);
 377         if (!list_empty(&dwc->queue)) {
 378                 list_move(dwc->queue.next, &dwc->active_list);
 379                 dwc_dostart(dwc, dwc_first_active(dwc));
 380         }
 381
 382         spin_unlock_irqrestore(&dwc->lock, flags);
 383
 384         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 385                 dwc_descriptor_complete(dwc, desc, true);
 386 }
 387
 388 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 389 {
 390         dma_addr_t llp;
 391         struct dw_desc *desc, *_desc;
 392         struct dw_desc *child;
 393         u32 status_xfer;
 394         unsigned long flags;
 395
 396         spin_lock_irqsave(&dwc->lock, flags);
 397         llp = channel_readl(dwc, LLP);
 398         status_xfer = dma_readl(dw, RAW.XFER);
 399
 400         if (status_xfer & dwc->mask) {
 401                 /* Everything we've submitted is done */
 402                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 403                 spin_unlock_irqrestore(&dwc->lock, flags);
 404
 405                 dwc_complete_all(dw, dwc);
 406                 return;
 407         }
 408
 409         if (list_empty(&dwc->active_list)) {
 410                 spin_unlock_irqrestore(&dwc->lock, flags);
 411                 return;
 412         }
 413
 414         dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__,
 415                         (unsigned long long)llp);
 416
 417         list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
 418                 /* check first descriptors addr */
 419                 if (desc->txd.phys == llp) {
 420                         spin_unlock_irqrestore(&dwc->lock, flags);
 421                         return;
 422                 }
 423
 424                 /* check first descriptors llp */
 425                 if (desc->lli.llp == llp) {
 426                         /* This one is currently in progress */
 427                         spin_unlock_irqrestore(&dwc->lock, flags);
 428                         return;
 429                 }
 430
 431                 list_for_each_entry(child, &desc->tx_list, desc_node)
 432                         if (child->lli.llp == llp) {
 433                                 /* Currently in progress */
 434                                 spin_unlock_irqrestore(&dwc->lock, flags);
 435                                 return;
 436                         }
 437
 438                 /*
 439                  * No descriptors so far seem to be in progress, i.e.
 440                  * this one must be done.
 441                  */
 442                 spin_unlock_irqrestore(&dwc->lock, flags);
 443                 dwc_descriptor_complete(dwc, desc, true);
 444                 spin_lock_irqsave(&dwc->lock, flags);
 445         }
 446
 447         dev_err(chan2dev(&dwc->chan),
 448                 "BUG: All descriptors done, but channel not idle!\n");
 449
 450         /* Try to continue after resetting the channel... */
 451         dwc_chan_disable(dw, dwc);
 452
 453         if (!list_empty(&dwc->queue)) {
 454                 list_move(dwc->queue.next, &dwc->active_list);
 455                 dwc_dostart(dwc, dwc_first_active(dwc));
 456         }
 457         spin_unlock_irqrestore(&dwc->lock, flags);
 458 }
 459
 460 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
 461 {
 462         dev_crit(chan2dev(&dwc->chan), "  desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
 463                  lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
 464 }
 465
 466 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
 467 {
 468         struct dw_desc *bad_desc;
 469         struct dw_desc *child;
 470         unsigned long flags;
 471
 472         dwc_scan_descriptors(dw, dwc);
 473
 474         spin_lock_irqsave(&dwc->lock, flags);
 475
 476         /*
 477          * The descriptor currently at the head of the active list is
 478          * borked. Since we don't have any way to report errors, we'll
 479          * just have to scream loudly and try to carry on.
 480          */
 481         bad_desc = dwc_first_active(dwc);
 482         list_del_init(&bad_desc->desc_node);
 483         list_move(dwc->queue.next, dwc->active_list.prev);
 484
 485         /* Clear the error flag and try to restart the controller */
 486         dma_writel(dw, CLEAR.ERROR, dwc->mask);
 487         if (!list_empty(&dwc->active_list))
 488                 dwc_dostart(dwc, dwc_first_active(dwc));
 489
 490         /*
 491          * WARN may seem harsh, but since this only happens
 492          * when someone submits a bad physical address in a
 493          * descriptor, we should consider ourselves lucky that the
 494          * controller flagged an error instead of scribbling over
 495          * random memory locations.
 496          */
 497         dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
 498                                        "  cookie: %d\n", bad_desc->txd.cookie);
 499         dwc_dump_lli(dwc, &bad_desc->lli);
 500         list_for_each_entry(child, &bad_desc->tx_list, desc_node)
 501                 dwc_dump_lli(dwc, &child->lli);
 502
 503         spin_unlock_irqrestore(&dwc->lock, flags);
 504
 505         /* Pretend the descriptor completed successfully */
 506         dwc_descriptor_complete(dwc, bad_desc, true);
 507 }
 508
 509 /* --------------------- Cyclic DMA API extensions -------------------- */
 510
 511 inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
 512 {
 513         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 514         return channel_readl(dwc, SAR);
 515 }
 516 EXPORT_SYMBOL(dw_dma_get_src_addr);
 517
 518 inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
 519 {
 520         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 521         return channel_readl(dwc, DAR);
 522 }
 523 EXPORT_SYMBOL(dw_dma_get_dst_addr);
 524
 525 /* called with dwc->lock held and all DMAC interrupts disabled */
 526 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
 527                 u32 status_err, u32 status_xfer)
 528 {
 529         unsigned long flags;
 530
 531         if (dwc->mask) {
 532                 void (*callback)(void *param);
 533                 void *callback_param;
 534
 535                 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
 536                                 channel_readl(dwc, LLP));
 537
 538                 callback = dwc->cdesc->period_callback;
 539                 callback_param = dwc->cdesc->period_callback_param;
 540
 541                 if (callback)
 542                         callback(callback_param);
 543         }
 544
 545         /*
 546          * Error and transfer complete are highly unlikely, and will most
 547          * likely be due to a configuration error by the user.
 548          */
 549         if (unlikely(status_err & dwc->mask) ||
 550                         unlikely(status_xfer & dwc->mask)) {
 551                 int i;
 552
 553                 dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s "
 554                                 "interrupt, stopping DMA transfer\n",
 555                                 status_xfer ? "xfer" : "error");
 556
 557                 spin_lock_irqsave(&dwc->lock, flags);
 558
 559                 dwc_dump_chan_regs(dwc);
 560
 561                 dwc_chan_disable(dw, dwc);
 562
 563                 /* make sure DMA does not restart by loading a new list */
 564                 channel_writel(dwc, LLP, 0);
 565                 channel_writel(dwc, CTL_LO, 0);
 566                 channel_writel(dwc, CTL_HI, 0);
 567
 568                 dma_writel(dw, CLEAR.ERROR, dwc->mask);
 569                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 570
 571                 for (i = 0; i < dwc->cdesc->periods; i++)
 572                         dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
 573
 574                 spin_unlock_irqrestore(&dwc->lock, flags);
 575         }
 576 }
 577
 578 /* ------------------------------------------------------------------------- */
 579
 580 static void dw_dma_tasklet(unsigned long data)
 581 {
 582         struct dw_dma *dw = (struct dw_dma *)data;
 583         struct dw_dma_chan *dwc;
 584         u32 status_xfer;
 585         u32 status_err;
 586         int i;
 587
 588         status_xfer = dma_readl(dw, RAW.XFER);
 589         status_err = dma_readl(dw, RAW.ERROR);
 590
 591         dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
 592
 593         for (i = 0; i < dw->dma.chancnt; i++) {
 594                 dwc = &dw->chan[i];
 595                 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
 596                         dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
 597                 else if (status_err & (1 << i))
 598                         dwc_handle_error(dw, dwc);
 599                 else if (status_xfer & (1 << i)) {
 600                         unsigned long flags;
 601
 602                         spin_lock_irqsave(&dwc->lock, flags);
 603                         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 604                                 if (dwc->tx_node_active != dwc->tx_list) {
 605                                         struct dw_desc *desc =
 606                                                 to_dw_desc(dwc->tx_node_active);
 607
 608                                         dma_writel(dw, CLEAR.XFER, dwc->mask);
 609
 610                                         dwc_do_single_block(dwc, desc);
 611
 612                                         spin_unlock_irqrestore(&dwc->lock, flags);
 613                                         continue;
 614                                 }
 615                                 /* we are done here */
 616                                 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
 617                         }
 618                         spin_unlock_irqrestore(&dwc->lock, flags);
 619
 620                         dwc_scan_descriptors(dw, dwc);
 621                 }
 622         }
 623
 624         /*
 625          * Re-enable interrupts.
 626          */
 627         channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
 628         channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
 629 }
 630
 631 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
 632 {
 633         struct dw_dma *dw = dev_id;
 634         u32 status;
 635
 636         dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__,
 637                         dma_readl(dw, STATUS_INT));
 638
 639         /*
 640          * Just disable the interrupts. We'll turn them back on in the
 641          * softirq handler.
 642          */
 643         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
 644         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
 645
 646         status = dma_readl(dw, STATUS_INT);
 647         if (status) {
 648                 dev_err(dw->dma.dev,
 649                         "BUG: Unexpected interrupts pending: 0x%x\n",
 650                         status);
 651
 652                 /* Try to recover */
 653                 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
 654                 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
 655                 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
 656                 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
 657         }
 658
 659         tasklet_schedule(&dw->tasklet);
 660
 661         return IRQ_HANDLED;
 662 }
 663
 664 /*----------------------------------------------------------------------*/
 665
 666 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
 667 {
 668         struct dw_desc          *desc = txd_to_dw_desc(tx);
 669         struct dw_dma_chan      *dwc = to_dw_dma_chan(tx->chan);
 670         dma_cookie_t            cookie;
 671         unsigned long           flags;
 672
 673         spin_lock_irqsave(&dwc->lock, flags);
 674         cookie = dma_cookie_assign(tx);
 675
 676         /*
 677          * REVISIT: We should attempt to chain as many descriptors as
 678          * possible, perhaps even appending to those already submitted
 679          * for DMA. But this is hard to do in a race-free manner.
 680          */
 681         if (list_empty(&dwc->active_list)) {
 682                 dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__,
 683                                 desc->txd.cookie);
 684                 list_add_tail(&desc->desc_node, &dwc->active_list);
 685                 dwc_dostart(dwc, dwc_first_active(dwc));
 686         } else {
 687                 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__,
 688                                 desc->txd.cookie);
 689
 690                 list_add_tail(&desc->desc_node, &dwc->queue);
 691         }
 692
 693         spin_unlock_irqrestore(&dwc->lock, flags);
 694
 695         return cookie;
 696 }
 697
 698 static struct dma_async_tx_descriptor *
 699 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 700                 size_t len, unsigned long flags)
 701 {
 702         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 703         struct dw_desc          *desc;
 704         struct dw_desc          *first;
 705         struct dw_desc          *prev;
 706         size_t                  xfer_count;
 707         size_t                  offset;
 708         unsigned int            src_width;
 709         unsigned int            dst_width;
 710         unsigned int            data_width;
 711         u32                     ctllo;
 712
 713         dev_vdbg(chan2dev(chan),
 714                         "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__,
 715                         (unsigned long long)dest, (unsigned long long)src,
 716                         len, flags);
 717
 718         if (unlikely(!len)) {
 719                 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
 720                 return NULL;
 721         }
 722
 723         dwc->direction = DMA_MEM_TO_MEM;
 724
 725         data_width = min_t(unsigned int, dwc_get_data_width(chan, SRC_MASTER),
 726                            dwc_get_data_width(chan, DST_MASTER));
 727
 728         src_width = dst_width = min_t(unsigned int, data_width,
 729                                       dwc_fast_fls(src | dest | len));
 730
 731         ctllo = DWC_DEFAULT_CTLLO(chan)
 732                         | DWC_CTLL_DST_WIDTH(dst_width)
 733                         | DWC_CTLL_SRC_WIDTH(src_width)
 734                         | DWC_CTLL_DST_INC
 735                         | DWC_CTLL_SRC_INC
 736                         | DWC_CTLL_FC_M2M;
 737         prev = first = NULL;
 738
 739         for (offset = 0; offset < len; offset += xfer_count << src_width) {
 740                 xfer_count = min_t(size_t, (len - offset) >> src_width,
 741                                            dwc->block_size);
 742
 743                 desc = dwc_desc_get(dwc);
 744                 if (!desc)
 745                         goto err_desc_get;
 746
 747                 desc->lli.sar = src + offset;
 748                 desc->lli.dar = dest + offset;
 749                 desc->lli.ctllo = ctllo;
 750                 desc->lli.ctlhi = xfer_count;
 751
 752                 if (!first) {
 753                         first = desc;
 754                 } else {
 755                         prev->lli.llp = desc->txd.phys;
 756                         list_add_tail(&desc->desc_node,
 757                                         &first->tx_list);
 758                 }
 759                 prev = desc;
 760         }
 761
 762         if (flags & DMA_PREP_INTERRUPT)
 763                 /* Trigger interrupt after last block */
 764                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 765
 766         prev->lli.llp = 0;
 767         first->txd.flags = flags;
 768         first->len = len;
 769
 770         return &first->txd;
 771
 772 err_desc_get:
 773         dwc_desc_put(dwc, first);
 774         return NULL;
 775 }
 776
 777 static struct dma_async_tx_descriptor *
 778 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 779                 unsigned int sg_len, enum dma_transfer_direction direction,
 780                 unsigned long flags, void *context)
 781 {
 782         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 783         struct dma_slave_config *sconfig = &dwc->dma_sconfig;
 784         struct dw_desc          *prev;
 785         struct dw_desc          *first;
 786         u32                     ctllo;
 787         dma_addr_t              reg;
 788         unsigned int            reg_width;
 789         unsigned int            mem_width;
 790         unsigned int            data_width;
 791         unsigned int            i;
 792         struct scatterlist      *sg;
 793         size_t                  total_len = 0;
 794
 795         dev_vdbg(chan2dev(chan), "%s\n", __func__);
 796
 797         if (unlikely(!is_slave_direction(direction) || !sg_len))
 798                 return NULL;
 799
 800         dwc->direction = direction;
 801
 802         prev = first = NULL;
 803
 804         switch (direction) {
 805         case DMA_MEM_TO_DEV:
 806                 reg_width = __fls(sconfig->dst_addr_width);
 807                 reg = sconfig->dst_addr;
 808                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 809                                 | DWC_CTLL_DST_WIDTH(reg_width)
 810                                 | DWC_CTLL_DST_FIX
 811                                 | DWC_CTLL_SRC_INC);
 812
 813                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
 814                         DWC_CTLL_FC(DW_DMA_FC_D_M2P);
 815
 816                 data_width = dwc_get_data_width(chan, SRC_MASTER);
 817
 818                 for_each_sg(sgl, sg, sg_len, i) {
 819                         struct dw_desc  *desc;
 820                         u32             len, dlen, mem;
 821
 822                         mem = sg_dma_address(sg);
 823                         len = sg_dma_len(sg);
 824
 825                         mem_width = min_t(unsigned int,
 826                                           data_width, dwc_fast_fls(mem | len));
 827
 828 slave_sg_todev_fill_desc:
 829                         desc = dwc_desc_get(dwc);
 830                         if (!desc) {
 831                                 dev_err(chan2dev(chan),
 832                                         "not enough descriptors available\n");
 833                                 goto err_desc_get;
 834                         }
 835
 836                         desc->lli.sar = mem;
 837                         desc->lli.dar = reg;
 838                         desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
 839                         if ((len >> mem_width) > dwc->block_size) {
 840                                 dlen = dwc->block_size << mem_width;
 841                                 mem += dlen;
 842                                 len -= dlen;
 843                         } else {
 844                                 dlen = len;
 845                                 len = 0;
 846                         }
 847
 848                         desc->lli.ctlhi = dlen >> mem_width;
 849
 850                         if (!first) {
 851                                 first = desc;
 852                         } else {
 853                                 prev->lli.llp = desc->txd.phys;
 854                                 list_add_tail(&desc->desc_node,
 855                                                 &first->tx_list);
 856                         }
 857                         prev = desc;
 858                         total_len += dlen;
 859
 860                         if (len)
 861                                 goto slave_sg_todev_fill_desc;
 862                 }
 863                 break;
 864         case DMA_DEV_TO_MEM:
 865                 reg_width = __fls(sconfig->src_addr_width);
 866                 reg = sconfig->src_addr;
 867                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 868                                 | DWC_CTLL_SRC_WIDTH(reg_width)
 869                                 | DWC_CTLL_DST_INC
 870                                 | DWC_CTLL_SRC_FIX);
 871
 872                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
 873                         DWC_CTLL_FC(DW_DMA_FC_D_P2M);
 874
 875                 data_width = dwc_get_data_width(chan, DST_MASTER);
 876
 877                 for_each_sg(sgl, sg, sg_len, i) {
 878                         struct dw_desc  *desc;
 879                         u32             len, dlen, mem;
 880
 881                         mem = sg_dma_address(sg);
 882                         len = sg_dma_len(sg);
 883
 884                         mem_width = min_t(unsigned int,
 885                                           data_width, dwc_fast_fls(mem | len));
 886
 887 slave_sg_fromdev_fill_desc:
 888                         desc = dwc_desc_get(dwc);
 889                         if (!desc) {
 890                                 dev_err(chan2dev(chan),
 891                                                 "not enough descriptors available\n");
 892                                 goto err_desc_get;
 893                         }
 894
 895                         desc->lli.sar = reg;
 896                         desc->lli.dar = mem;
 897                         desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
 898                         if ((len >> reg_width) > dwc->block_size) {
 899                                 dlen = dwc->block_size << reg_width;
 900                                 mem += dlen;
 901                                 len -= dlen;
 902                         } else {
 903                                 dlen = len;
 904                                 len = 0;
 905                         }
 906                         desc->lli.ctlhi = dlen >> reg_width;
 907
 908                         if (!first) {
 909                                 first = desc;
 910                         } else {
 911                                 prev->lli.llp = desc->txd.phys;
 912                                 list_add_tail(&desc->desc_node,
 913                                                 &first->tx_list);
 914                         }
 915                         prev = desc;
 916                         total_len += dlen;
 917
 918                         if (len)
 919                                 goto slave_sg_fromdev_fill_desc;
 920                 }
 921                 break;
 922         default:
 923                 return NULL;
 924         }
 925
 926         if (flags & DMA_PREP_INTERRUPT)
 927                 /* Trigger interrupt after last block */
 928                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 929
 930         prev->lli.llp = 0;
 931         first->len = total_len;
 932
 933         return &first->txd;
 934
 935 err_desc_get:
 936         dwc_desc_put(dwc, first);
 937         return NULL;
 938 }
 939
 940 /*
 941  * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
 942  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
 943  *
 944  * NOTE: burst size 2 is not supported by controller.
 945  *
 946  * This can be done by finding least significant bit set: n & (n - 1)
 947  */
 948 static inline void convert_burst(u32 *maxburst)
 949 {
 950         if (*maxburst > 1)
 951                 *maxburst = fls(*maxburst) - 2;
 952         else
 953                 *maxburst = 0;
 954 }
 955
 956 static int
 957 set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
 958 {
 959         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 960
 961         /* Check if chan will be configured for slave transfers */
 962         if (!is_slave_direction(sconfig->direction))
 963                 return -EINVAL;
 964
 965         memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
 966         dwc->direction = sconfig->direction;
 967
 968         convert_burst(&dwc->dma_sconfig.src_maxburst);
 969         convert_burst(&dwc->dma_sconfig.dst_maxburst);
 970
 971         return 0;
 972 }
 973
 974 static inline void dwc_chan_pause(struct dw_dma_chan *dwc)
 975 {
 976         u32 cfglo = channel_readl(dwc, CFG_LO);
 977
 978         channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
 979         while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY))
 980                 cpu_relax();
 981
 982         dwc->paused = true;
 983 }
 984
 985 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
 986 {
 987         u32 cfglo = channel_readl(dwc, CFG_LO);
 988
 989         channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
 990
 991         dwc->paused = false;
 992 }
 993
 994 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 995                        unsigned long arg)
 996 {
 997         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 998         struct dw_dma           *dw = to_dw_dma(chan->device);
 999         struct dw_desc          *desc, *_desc;
1000         unsigned long           flags;
1001         LIST_HEAD(list);
1002
1003         if (cmd == DMA_PAUSE) {
1004                 spin_lock_irqsave(&dwc->lock, flags);
1005
1006                 dwc_chan_pause(dwc);
1007
1008                 spin_unlock_irqrestore(&dwc->lock, flags);
1009         } else if (cmd == DMA_RESUME) {
1010                 if (!dwc->paused)
1011                         return 0;
1012
1013                 spin_lock_irqsave(&dwc->lock, flags);
1014
1015                 dwc_chan_resume(dwc);
1016
1017                 spin_unlock_irqrestore(&dwc->lock, flags);
1018         } else if (cmd == DMA_TERMINATE_ALL) {
1019                 spin_lock_irqsave(&dwc->lock, flags);
1020
1021                 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1022
1023                 dwc_chan_disable(dw, dwc);
1024
1025                 dwc_chan_resume(dwc);
1026
1027                 /* active_list entries will end up before queued entries */
1028                 list_splice_init(&dwc->queue, &list);
1029                 list_splice_init(&dwc->active_list, &list);
1030
1031                 spin_unlock_irqrestore(&dwc->lock, flags);
1032
1033                 /* Flush all pending and queued descriptors */
1034                 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1035                         dwc_descriptor_complete(dwc, desc, false);
1036         } else if (cmd == DMA_SLAVE_CONFIG) {
1037                 return set_runtime_config(chan, (struct dma_slave_config *)arg);
1038         } else {
1039                 return -ENXIO;
1040         }
1041
1042         return 0;
1043 }
1044
1045 static enum dma_status
1046 dwc_tx_status(struct dma_chan *chan,
1047               dma_cookie_t cookie,
1048               struct dma_tx_state *txstate)
1049 {
1050         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1051         enum dma_status         ret;
1052
1053         ret = dma_cookie_status(chan, cookie, txstate);
1054         if (ret != DMA_SUCCESS) {
1055                 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1056
1057                 ret = dma_cookie_status(chan, cookie, txstate);
1058         }
1059
1060         if (ret != DMA_SUCCESS)
1061                 dma_set_residue(txstate, dwc_first_active(dwc)->len);
1062
1063         if (dwc->paused)
1064                 return DMA_PAUSED;
1065
1066         return ret;
1067 }
1068
1069 static void dwc_issue_pending(struct dma_chan *chan)
1070 {
1071         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1072
1073         if (!list_empty(&dwc->queue))
1074                 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1075 }
1076
1077 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1078 {
1079         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1080         struct dw_dma           *dw = to_dw_dma(chan->device);
1081         struct dw_desc          *desc;
1082         int                     i;
1083         unsigned long           flags;
1084
1085         dev_vdbg(chan2dev(chan), "%s\n", __func__);
1086
1087         /* ASSERT:  channel is idle */
1088         if (dma_readl(dw, CH_EN) & dwc->mask) {
1089                 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1090                 return -EIO;
1091         }
1092
1093         dma_cookie_init(chan);
1094
1095         /*
1096          * NOTE: some controllers may have additional features that we
1097          * need to initialize here, like "scatter-gather" (which
1098          * doesn't mean what you think it means), and status writeback.
1099          */
1100
1101         spin_lock_irqsave(&dwc->lock, flags);
1102         i = dwc->descs_allocated;
1103         while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1104                 dma_addr_t phys;
1105
1106                 spin_unlock_irqrestore(&dwc->lock, flags);
1107
1108                 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1109                 if (!desc)
1110                         goto err_desc_alloc;
1111
1112                 memset(desc, 0, sizeof(struct dw_desc));
1113
1114                 INIT_LIST_HEAD(&desc->tx_list);
1115                 dma_async_tx_descriptor_init(&desc->txd, chan);
1116                 desc->txd.tx_submit = dwc_tx_submit;
1117                 desc->txd.flags = DMA_CTRL_ACK;
1118                 desc->txd.phys = phys;
1119
1120                 dwc_desc_put(dwc, desc);
1121
1122                 spin_lock_irqsave(&dwc->lock, flags);
1123                 i = ++dwc->descs_allocated;
1124         }
1125
1126         spin_unlock_irqrestore(&dwc->lock, flags);
1127
1128         dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1129
1130         return i;
1131
1132 err_desc_alloc:
1133         dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1134
1135         return i;
1136 }
1137
1138 static void dwc_free_chan_resources(struct dma_chan *chan)
1139 {
1140         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1141         struct dw_dma           *dw = to_dw_dma(chan->device);
1142         struct dw_desc          *desc, *_desc;
1143         unsigned long           flags;
1144         LIST_HEAD(list);
1145
1146         dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1147                         dwc->descs_allocated);
1148
1149         /* ASSERT:  channel is idle */
1150         BUG_ON(!list_empty(&dwc->active_list));
1151         BUG_ON(!list_empty(&dwc->queue));
1152         BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1153
1154         spin_lock_irqsave(&dwc->lock, flags);
1155         list_splice_init(&dwc->free_list, &list);
1156         dwc->descs_allocated = 0;
1157         dwc->initialized = false;
1158
1159         /* Disable interrupts */
1160         channel_clear_bit(dw, MASK.XFER, dwc->mask);
1161         channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1162
1163         spin_unlock_irqrestore(&dwc->lock, flags);
1164
1165         list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1166                 dev_vdbg(chan2dev(chan), "  freeing descriptor %p\n", desc);
1167                 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1168         }
1169
1170         dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1171 }
1172
1173 bool dw_dma_generic_filter(struct dma_chan *chan, void *param)
1174 {
1175         struct dw_dma *dw = to_dw_dma(chan->device);
1176         static struct dw_dma *last_dw;
1177         static char *last_bus_id;
1178         int i = -1;
1179
1180         /*
1181          * dmaengine framework calls this routine for all channels of all dma
1182          * controller, until true is returned. If 'param' bus_id is not
1183          * registered with a dma controller (dw), then there is no need of
1184          * running below function for all channels of dw.
1185          *
1186          * This block of code does this by saving the parameters of last
1187          * failure. If dw and param are same, i.e. trying on same dw with
1188          * different channel, return false.
1189          */
1190         if ((last_dw == dw) && (last_bus_id == param))
1191                 return false;
1192         /*
1193          * Return true:
1194          * - If dw_dma's platform data is not filled with slave info, then all
1195          *   dma controllers are fine for transfer.
1196          * - Or if param is NULL
1197          */
1198         if (!dw->sd || !param)
1199                 return true;
1200
1201         while (++i < dw->sd_count) {
1202                 if (!strcmp(dw->sd[i].bus_id, param)) {
1203                         chan->private = &dw->sd[i];
1204                         last_dw = NULL;
1205                         last_bus_id = NULL;
1206
1207                         return true;
1208                 }
1209         }
1210
1211         last_dw = dw;
1212         last_bus_id = param;
1213         return false;
1214 }
1215 EXPORT_SYMBOL(dw_dma_generic_filter);
1216
1217 /* --------------------- Cyclic DMA API extensions -------------------- */
1218
1219 /**
1220  * dw_dma_cyclic_start - start the cyclic DMA transfer
1221  * @chan: the DMA channel to start
1222  *
1223  * Must be called with soft interrupts disabled. Returns zero on success or
1224  * -errno on failure.
1225  */
1226 int dw_dma_cyclic_start(struct dma_chan *chan)
1227 {
1228         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1229         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1230         unsigned long           flags;
1231
1232         if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1233                 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1234                 return -ENODEV;
1235         }
1236
1237         spin_lock_irqsave(&dwc->lock, flags);
1238
1239         /* assert channel is idle */
1240         if (dma_readl(dw, CH_EN) & dwc->mask) {
1241                 dev_err(chan2dev(&dwc->chan),
1242                         "BUG: Attempted to start non-idle channel\n");
1243                 dwc_dump_chan_regs(dwc);
1244                 spin_unlock_irqrestore(&dwc->lock, flags);
1245                 return -EBUSY;
1246         }
1247
1248         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1249         dma_writel(dw, CLEAR.XFER, dwc->mask);
1250
1251         /* setup DMAC channel registers */
1252         channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1253         channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1254         channel_writel(dwc, CTL_HI, 0);
1255
1256         channel_set_bit(dw, CH_EN, dwc->mask);
1257
1258         spin_unlock_irqrestore(&dwc->lock, flags);
1259
1260         return 0;
1261 }
1262 EXPORT_SYMBOL(dw_dma_cyclic_start);
1263
1264 /**
1265  * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1266  * @chan: the DMA channel to stop
1267  *
1268  * Must be called with soft interrupts disabled.
1269  */
1270 void dw_dma_cyclic_stop(struct dma_chan *chan)
1271 {
1272         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1273         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1274         unsigned long           flags;
1275
1276         spin_lock_irqsave(&dwc->lock, flags);
1277
1278         dwc_chan_disable(dw, dwc);
1279
1280         spin_unlock_irqrestore(&dwc->lock, flags);
1281 }
1282 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1283
1284 /**
1285  * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1286  * @chan: the DMA channel to prepare
1287  * @buf_addr: physical DMA address where the buffer starts
1288  * @buf_len: total number of bytes for the entire buffer
1289  * @period_len: number of bytes for each period
1290  * @direction: transfer direction, to or from device
1291  *
1292  * Must be called before trying to start the transfer. Returns a valid struct
1293  * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1294  */
1295 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1296                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1297                 enum dma_transfer_direction direction)
1298 {
1299         struct dw_dma_chan              *dwc = to_dw_dma_chan(chan);
1300         struct dma_slave_config         *sconfig = &dwc->dma_sconfig;
1301         struct dw_cyclic_desc           *cdesc;
1302         struct dw_cyclic_desc           *retval = NULL;
1303         struct dw_desc                  *desc;
1304         struct dw_desc                  *last = NULL;
1305         unsigned long                   was_cyclic;
1306         unsigned int                    reg_width;
1307         unsigned int                    periods;
1308         unsigned int                    i;
1309         unsigned long                   flags;
1310
1311         spin_lock_irqsave(&dwc->lock, flags);
1312         if (dwc->nollp) {
1313                 spin_unlock_irqrestore(&dwc->lock, flags);
1314                 dev_dbg(chan2dev(&dwc->chan),
1315                                 "channel doesn't support LLP transfers\n");
1316                 return ERR_PTR(-EINVAL);
1317         }
1318
1319         if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1320                 spin_unlock_irqrestore(&dwc->lock, flags);
1321                 dev_dbg(chan2dev(&dwc->chan),
1322                                 "queue and/or active list are not empty\n");
1323                 return ERR_PTR(-EBUSY);
1324         }
1325
1326         was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1327         spin_unlock_irqrestore(&dwc->lock, flags);
1328         if (was_cyclic) {
1329                 dev_dbg(chan2dev(&dwc->chan),
1330                                 "channel already prepared for cyclic DMA\n");
1331                 return ERR_PTR(-EBUSY);
1332         }
1333
1334         retval = ERR_PTR(-EINVAL);
1335
1336         if (unlikely(!is_slave_direction(direction)))
1337                 goto out_err;
1338
1339         dwc->direction = direction;
1340
1341         if (direction == DMA_MEM_TO_DEV)
1342                 reg_width = __ffs(sconfig->dst_addr_width);
1343         else
1344                 reg_width = __ffs(sconfig->src_addr_width);
1345
1346         periods = buf_len / period_len;
1347
1348         /* Check for too big/unaligned periods and unaligned DMA buffer. */
1349         if (period_len > (dwc->block_size << reg_width))
1350                 goto out_err;
1351         if (unlikely(period_len & ((1 << reg_width) - 1)))
1352                 goto out_err;
1353         if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1354                 goto out_err;
1355
1356         retval = ERR_PTR(-ENOMEM);
1357
1358         if (periods > NR_DESCS_PER_CHANNEL)
1359                 goto out_err;
1360
1361         cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1362         if (!cdesc)
1363                 goto out_err;
1364
1365         cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1366         if (!cdesc->desc)
1367                 goto out_err_alloc;
1368
1369         for (i = 0; i < periods; i++) {
1370                 desc = dwc_desc_get(dwc);
1371                 if (!desc)
1372                         goto out_err_desc_get;
1373
1374                 switch (direction) {
1375                 case DMA_MEM_TO_DEV:
1376                         desc->lli.dar = sconfig->dst_addr;
1377                         desc->lli.sar = buf_addr + (period_len * i);
1378                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1379                                         | DWC_CTLL_DST_WIDTH(reg_width)
1380                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1381                                         | DWC_CTLL_DST_FIX
1382                                         | DWC_CTLL_SRC_INC
1383                                         | DWC_CTLL_INT_EN);
1384
1385                         desc->lli.ctllo |= sconfig->device_fc ?
1386                                 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1387                                 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1388
1389                         break;
1390                 case DMA_DEV_TO_MEM:
1391                         desc->lli.dar = buf_addr + (period_len * i);
1392                         desc->lli.sar = sconfig->src_addr;
1393                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1394                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1395                                         | DWC_CTLL_DST_WIDTH(reg_width)
1396                                         | DWC_CTLL_DST_INC
1397                                         | DWC_CTLL_SRC_FIX
1398                                         | DWC_CTLL_INT_EN);
1399
1400                         desc->lli.ctllo |= sconfig->device_fc ?
1401                                 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1402                                 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1403
1404                         break;
1405                 default:
1406                         break;
1407                 }
1408
1409                 desc->lli.ctlhi = (period_len >> reg_width);
1410                 cdesc->desc[i] = desc;
1411
1412                 if (last)
1413                         last->lli.llp = desc->txd.phys;
1414
1415                 last = desc;
1416         }
1417
1418         /* lets make a cyclic list */
1419         last->lli.llp = cdesc->desc[0]->txd.phys;
1420
1421         dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu "
1422                         "period %zu periods %d\n", (unsigned long long)buf_addr,
1423                         buf_len, period_len, periods);
1424
1425         cdesc->periods = periods;
1426         dwc->cdesc = cdesc;
1427
1428         return cdesc;
1429
1430 out_err_desc_get:
1431         while (i--)
1432                 dwc_desc_put(dwc, cdesc->desc[i]);
1433 out_err_alloc:
1434         kfree(cdesc);
1435 out_err:
1436         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1437         return (struct dw_cyclic_desc *)retval;
1438 }
1439 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1440
1441 /**
1442  * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1443  * @chan: the DMA channel to free
1444  */
1445 void dw_dma_cyclic_free(struct dma_chan *chan)
1446 {
1447         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1448         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1449         struct dw_cyclic_desc   *cdesc = dwc->cdesc;
1450         int                     i;
1451         unsigned long           flags;
1452
1453         dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1454
1455         if (!cdesc)
1456                 return;
1457
1458         spin_lock_irqsave(&dwc->lock, flags);
1459
1460         dwc_chan_disable(dw, dwc);
1461
1462         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1463         dma_writel(dw, CLEAR.XFER, dwc->mask);
1464
1465         spin_unlock_irqrestore(&dwc->lock, flags);
1466
1467         for (i = 0; i < cdesc->periods; i++)
1468                 dwc_desc_put(dwc, cdesc->desc[i]);
1469
1470         kfree(cdesc->desc);
1471         kfree(cdesc);
1472
1473         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1474 }
1475 EXPORT_SYMBOL(dw_dma_cyclic_free);
1476
1477 /*----------------------------------------------------------------------*/
1478
1479 static void dw_dma_off(struct dw_dma *dw)
1480 {
1481         int i;
1482
1483         dma_writel(dw, CFG, 0);
1484
1485         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1486         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1487         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1488         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1489
1490         while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1491                 cpu_relax();
1492
1493         for (i = 0; i < dw->dma.chancnt; i++)
1494                 dw->chan[i].initialized = false;
1495 }
1496
1497 #ifdef CONFIG_OF
1498 static struct dw_dma_platform_data *
1499 dw_dma_parse_dt(struct platform_device *pdev)
1500 {
1501         struct device_node *sn, *cn, *np = pdev->dev.of_node;
1502         struct dw_dma_platform_data *pdata;
1503         struct dw_dma_slave *sd;
1504         u32 tmp, arr[4];
1505
1506         if (!np) {
1507                 dev_err(&pdev->dev, "Missing DT data\n");
1508                 return NULL;
1509         }
1510
1511         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1512         if (!pdata)
1513                 return NULL;
1514
1515         if (of_property_read_u32(np, "nr_channels", &pdata->nr_channels))
1516                 return NULL;
1517
1518         if (of_property_read_bool(np, "is_private"))
1519                 pdata->is_private = true;
1520
1521         if (!of_property_read_u32(np, "chan_allocation_order", &tmp))
1522                 pdata->chan_allocation_order = (unsigned char)tmp;
1523
1524         if (!of_property_read_u32(np, "chan_priority", &tmp))
1525                 pdata->chan_priority = tmp;
1526
1527         if (!of_property_read_u32(np, "block_size", &tmp))
1528                 pdata->block_size = tmp;
1529
1530         if (!of_property_read_u32(np, "nr_masters", &tmp)) {
1531                 if (tmp > 4)
1532                         return NULL;
1533
1534                 pdata->nr_masters = tmp;
1535         }
1536
1537         if (!of_property_read_u32_array(np, "data_width", arr,
1538                                 pdata->nr_masters))
1539                 for (tmp = 0; tmp < pdata->nr_masters; tmp++)
1540                         pdata->data_width[tmp] = arr[tmp];
1541
1542         /* parse slave data */
1543         sn = of_find_node_by_name(np, "slave_info");
1544         if (!sn)
1545                 return pdata;
1546
1547         /* calculate number of slaves */
1548         tmp = of_get_child_count(sn);
1549         if (!tmp)
1550                 return NULL;
1551
1552         sd = devm_kzalloc(&pdev->dev, sizeof(*sd) * tmp, GFP_KERNEL);
1553         if (!sd)
1554                 return NULL;
1555
1556         pdata->sd = sd;
1557         pdata->sd_count = tmp;
1558
1559         for_each_child_of_node(sn, cn) {
1560                 sd->dma_dev = &pdev->dev;
1561                 of_property_read_string(cn, "bus_id", &sd->bus_id);
1562                 of_property_read_u32(cn, "cfg_hi", &sd->cfg_hi);
1563                 of_property_read_u32(cn, "cfg_lo", &sd->cfg_lo);
1564                 if (!of_property_read_u32(cn, "src_master", &tmp))
1565                         sd->src_master = tmp;
1566
1567                 if (!of_property_read_u32(cn, "dst_master", &tmp))
1568                         sd->dst_master = tmp;
1569                 sd++;
1570         }
1571
1572         return pdata;
1573 }
1574 #else
1575 static inline struct dw_dma_platform_data *
1576 dw_dma_parse_dt(struct platform_device *pdev)
1577 {
1578         return NULL;
1579 }
1580 #endif
1581
1582 static int dw_probe(struct platform_device *pdev)
1583 {
1584         struct dw_dma_platform_data *pdata;
1585         struct resource         *io;
1586         struct dw_dma           *dw;
1587         size_t                  size;
1588         void __iomem            *regs;
1589         bool                    autocfg;
1590         unsigned int            dw_params;
1591         unsigned int            nr_channels;
1592         unsigned int            max_blk_size = 0;
1593         int                     irq;
1594         int                     err;
1595         int                     i;
1596
1597         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1598         if (!io)
1599                 return -EINVAL;
1600
1601         irq = platform_get_irq(pdev, 0);
1602         if (irq < 0)
1603                 return irq;
1604
1605         regs = devm_request_and_ioremap(&pdev->dev, io);
1606         if (!regs)
1607                 return -EBUSY;
1608
1609         dw_params = dma_read_byaddr(regs, DW_PARAMS);
1610         autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1611
1612         pdata = dev_get_platdata(&pdev->dev);
1613         if (!pdata)
1614                 pdata = dw_dma_parse_dt(pdev);
1615
1616         if (!pdata && autocfg) {
1617                 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1618                 if (!pdata)
1619                         return -ENOMEM;
1620
1621                 /* Fill platform data with the default values */
1622                 pdata->is_private = true;
1623                 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1624                 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1625         } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
1626                 return -EINVAL;
1627
1628         if (autocfg)
1629                 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
1630         else
1631                 nr_channels = pdata->nr_channels;
1632
1633         size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan);
1634         dw = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1635         if (!dw)
1636                 return -ENOMEM;
1637
1638         dw->clk = devm_clk_get(&pdev->dev, "hclk");
1639         if (IS_ERR(dw->clk))
1640                 return PTR_ERR(dw->clk);
1641         clk_prepare_enable(dw->clk);
1642
1643         dw->regs = regs;
1644         dw->sd = pdata->sd;
1645         dw->sd_count = pdata->sd_count;
1646
1647         /* get hardware configuration parameters */
1648         if (autocfg) {
1649                 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1650
1651                 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1652                 for (i = 0; i < dw->nr_masters; i++) {
1653                         dw->data_width[i] =
1654                                 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1655                 }
1656         } else {
1657                 dw->nr_masters = pdata->nr_masters;
1658                 memcpy(dw->data_width, pdata->data_width, 4);
1659         }
1660
1661         /* Calculate all channel mask before DMA setup */
1662         dw->all_chan_mask = (1 << nr_channels) - 1;
1663
1664         /* force dma off, just in case */
1665         dw_dma_off(dw);
1666
1667         /* disable BLOCK interrupts as well */
1668         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1669
1670         err = devm_request_irq(&pdev->dev, irq, dw_dma_interrupt, 0,
1671                                "dw_dmac", dw);
1672         if (err)
1673                 return err;
1674
1675         platform_set_drvdata(pdev, dw);
1676
1677         /* create a pool of consistent memory blocks for hardware descriptors */
1678         dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", &pdev->dev,
1679                                          sizeof(struct dw_desc), 4, 0);
1680         if (!dw->desc_pool) {
1681                 dev_err(&pdev->dev, "No memory for descriptors dma pool\n");
1682                 return -ENOMEM;
1683         }
1684
1685         tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1686
1687         INIT_LIST_HEAD(&dw->dma.channels);
1688         for (i = 0; i < nr_channels; i++) {
1689                 struct dw_dma_chan      *dwc = &dw->chan[i];
1690                 int                     r = nr_channels - i - 1;
1691
1692                 dwc->chan.device = &dw->dma;
1693                 dma_cookie_init(&dwc->chan);
1694                 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1695                         list_add_tail(&dwc->chan.device_node,
1696                                         &dw->dma.channels);
1697                 else
1698                         list_add(&dwc->chan.device_node, &dw->dma.channels);
1699
1700                 /* 7 is highest priority & 0 is lowest. */
1701                 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1702                         dwc->priority = r;
1703                 else
1704                         dwc->priority = i;
1705
1706                 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1707                 spin_lock_init(&dwc->lock);
1708                 dwc->mask = 1 << i;
1709
1710                 INIT_LIST_HEAD(&dwc->active_list);
1711                 INIT_LIST_HEAD(&dwc->queue);
1712                 INIT_LIST_HEAD(&dwc->free_list);
1713
1714                 channel_clear_bit(dw, CH_EN, dwc->mask);
1715
1716                 dwc->direction = DMA_TRANS_NONE;
1717
1718                 /* hardware configuration */
1719                 if (autocfg) {
1720                         unsigned int dwc_params;
1721
1722                         dwc_params = dma_read_byaddr(regs + r * sizeof(u32),
1723                                                      DWC_PARAMS);
1724
1725                         /* Decode maximum block size for given channel. The
1726                          * stored 4 bit value represents blocks from 0x00 for 3
1727                          * up to 0x0a for 4095. */
1728                         dwc->block_size =
1729                                 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1730                         dwc->nollp =
1731                                 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1732                 } else {
1733                         dwc->block_size = pdata->block_size;
1734
1735                         /* Check if channel supports multi block transfer */
1736                         channel_writel(dwc, LLP, 0xfffffffc);
1737                         dwc->nollp =
1738                                 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1739                         channel_writel(dwc, LLP, 0);
1740                 }
1741         }
1742
1743         /* Clear all interrupts on all channels. */
1744         dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1745         dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1746         dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1747         dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1748         dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1749
1750         dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1751         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1752         if (pdata->is_private)
1753                 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1754         dw->dma.dev = &pdev->dev;
1755         dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1756         dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1757
1758         dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1759
1760         dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1761         dw->dma.device_control = dwc_control;
1762
1763         dw->dma.device_tx_status = dwc_tx_status;
1764         dw->dma.device_issue_pending = dwc_issue_pending;
1765
1766         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1767
1768         dev_info(&pdev->dev, "DesignWare DMA Controller, %d channels\n",
1769                  nr_channels);
1770
1771         dma_async_device_register(&dw->dma);
1772
1773         return 0;
1774 }
1775
1776 static int __devexit dw_remove(struct platform_device *pdev)
1777 {
1778         struct dw_dma           *dw = platform_get_drvdata(pdev);
1779         struct dw_dma_chan      *dwc, *_dwc;
1780
1781         dw_dma_off(dw);
1782         dma_async_device_unregister(&dw->dma);
1783
1784         tasklet_kill(&dw->tasklet);
1785
1786         list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1787                         chan.device_node) {
1788                 list_del(&dwc->chan.device_node);
1789                 channel_clear_bit(dw, CH_EN, dwc->mask);
1790         }
1791
1792         return 0;
1793 }
1794
1795 static void dw_shutdown(struct platform_device *pdev)
1796 {
1797         struct dw_dma   *dw = platform_get_drvdata(pdev);
1798
1799         dw_dma_off(dw);
1800         clk_disable_unprepare(dw->clk);
1801 }
1802
1803 static int dw_suspend_noirq(struct device *dev)
1804 {
1805         struct platform_device *pdev = to_platform_device(dev);
1806         struct dw_dma   *dw = platform_get_drvdata(pdev);
1807
1808         dw_dma_off(dw);
1809         clk_disable_unprepare(dw->clk);
1810
1811         return 0;
1812 }
1813
1814 static int dw_resume_noirq(struct device *dev)
1815 {
1816         struct platform_device *pdev = to_platform_device(dev);
1817         struct dw_dma   *dw = platform_get_drvdata(pdev);
1818
1819         clk_prepare_enable(dw->clk);
1820         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1821
1822         return 0;
1823 }
1824
1825 static const struct dev_pm_ops dw_dev_pm_ops = {
1826         .suspend_noirq = dw_suspend_noirq,
1827         .resume_noirq = dw_resume_noirq,
1828         .freeze_noirq = dw_suspend_noirq,
1829         .thaw_noirq = dw_resume_noirq,
1830         .restore_noirq = dw_resume_noirq,
1831         .poweroff_noirq = dw_suspend_noirq,
1832 };
1833
1834 #ifdef CONFIG_OF
1835 static const struct of_device_id dw_dma_id_table[] = {
1836         { .compatible = "snps,dma-spear1340" },
1837         {}
1838 };
1839 MODULE_DEVICE_TABLE(of, dw_dma_id_table);
1840 #endif
1841
1842 static struct platform_driver dw_driver = {
1843         .probe          = dw_probe,
1844         .remove         = dw_remove,
1845         .shutdown       = dw_shutdown,
1846         .driver = {
1847                 .name   = "dw_dmac",
1848                 .pm     = &dw_dev_pm_ops,
1849                 .of_match_table = of_match_ptr(dw_dma_id_table),
1850         },
1851 };
1852
1853 static int __init dw_init(void)
1854 {
1855         return platform_driver_register(&dw_driver);
1856 }
1857 subsys_initcall(dw_init);
1858
1859 static void __exit dw_exit(void)
1860 {
1861         platform_driver_unregister(&dw_driver);
1862 }
1863 module_exit(dw_exit);
1864
1865 MODULE_LICENSE("GPL v2");
1866 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
1867 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1868 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");