2 * Freescale MPC85xx, MPC83xx DMA Engine support
4 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
7 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
8 * Ebony Zhu <ebony.zhu@freescale.com>, May 2007
11 * DMA engine driver for Freescale MPC8540 DMA controller, which is
12 * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
13 * The support for MPC8349 DMA contorller is also added.
15 * This driver instructs the DMA controller to issue the PCI Read Multiple
16 * command for PCI read operations, instead of using the default PCI Read Line
17 * command. Please be aware that this setting may result in read pre-fetching
20 * This is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/interrupt.h>
31 #include <linux/dmaengine.h>
32 #include <linux/delay.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/dmapool.h>
35 #include <linux/of_platform.h>
37 #include <asm/fsldma.h>
40 static void dma_init(struct fsldma_chan *chan)
42 /* Reset the channel */
43 DMA_OUT(chan, &chan->regs->mr, 0, 32);
45 switch (chan->feature & FSL_DMA_IP_MASK) {
47 /* Set the channel to below modes:
48 * EIE - Error interrupt enable
49 * EOSIE - End of segments interrupt enable (basic mode)
50 * EOLNIE - End of links interrupt enable
52 DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE
53 | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);
56 /* Set the channel to below modes:
57 * EOTIE - End-of-transfer interrupt enable
58 * PRC_RM - PCI read multiple
60 DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE
61 | FSL_DMA_MR_PRC_RM, 32);
66 static void set_sr(struct fsldma_chan *chan, u32 val)
68 DMA_OUT(chan, &chan->regs->sr, val, 32);
71 static u32 get_sr(struct fsldma_chan *chan)
73 return DMA_IN(chan, &chan->regs->sr, 32);
76 static void set_desc_cnt(struct fsldma_chan *chan,
77 struct fsl_dma_ld_hw *hw, u32 count)
79 hw->count = CPU_TO_DMA(chan, count, 32);
82 static void set_desc_src(struct fsldma_chan *chan,
83 struct fsl_dma_ld_hw *hw, dma_addr_t src)
87 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
88 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
89 hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
92 static void set_desc_dst(struct fsldma_chan *chan,
93 struct fsl_dma_ld_hw *hw, dma_addr_t dst)
97 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
98 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
99 hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
102 static void set_desc_next(struct fsldma_chan *chan,
103 struct fsl_dma_ld_hw *hw, dma_addr_t next)
107 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
109 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
112 static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
114 DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
117 static dma_addr_t get_cdar(struct fsldma_chan *chan)
119 return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
122 static dma_addr_t get_ndar(struct fsldma_chan *chan)
124 return DMA_IN(chan, &chan->regs->ndar, 64);
127 static u32 get_bcr(struct fsldma_chan *chan)
129 return DMA_IN(chan, &chan->regs->bcr, 32);
132 static int dma_is_idle(struct fsldma_chan *chan)
134 u32 sr = get_sr(chan);
135 return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
138 static void dma_start(struct fsldma_chan *chan)
142 mode = DMA_IN(chan, &chan->regs->mr, 32);
144 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
145 if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
146 DMA_OUT(chan, &chan->regs->bcr, 0, 32);
147 mode |= FSL_DMA_MR_EMP_EN;
149 mode &= ~FSL_DMA_MR_EMP_EN;
153 if (chan->feature & FSL_DMA_CHAN_START_EXT)
154 mode |= FSL_DMA_MR_EMS_EN;
156 mode |= FSL_DMA_MR_CS;
158 DMA_OUT(chan, &chan->regs->mr, mode, 32);
161 static void dma_halt(struct fsldma_chan *chan)
166 mode = DMA_IN(chan, &chan->regs->mr, 32);
167 mode |= FSL_DMA_MR_CA;
168 DMA_OUT(chan, &chan->regs->mr, mode, 32);
170 mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA);
171 DMA_OUT(chan, &chan->regs->mr, mode, 32);
173 for (i = 0; i < 100; i++) {
174 if (dma_is_idle(chan))
180 if (!dma_is_idle(chan))
181 dev_err(chan->dev, "DMA halt timeout!\n");
184 static void set_ld_eol(struct fsldma_chan *chan,
185 struct fsl_desc_sw *desc)
189 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
192 desc->hw.next_ln_addr = CPU_TO_DMA(chan,
193 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
198 * fsl_chan_set_src_loop_size - Set source address hold transfer size
199 * @chan : Freescale DMA channel
200 * @size : Address loop size, 0 for disable loop
202 * The set source address hold transfer size. The source
203 * address hold or loop transfer size is when the DMA transfer
204 * data from source address (SA), if the loop size is 4, the DMA will
205 * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
206 * SA + 1 ... and so on.
208 static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
212 mode = DMA_IN(chan, &chan->regs->mr, 32);
216 mode &= ~FSL_DMA_MR_SAHE;
222 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
226 DMA_OUT(chan, &chan->regs->mr, mode, 32);
230 * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
231 * @chan : Freescale DMA channel
232 * @size : Address loop size, 0 for disable loop
234 * The set destination address hold transfer size. The destination
235 * address hold or loop transfer size is when the DMA transfer
236 * data to destination address (TA), if the loop size is 4, the DMA will
237 * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
238 * TA + 1 ... and so on.
240 static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
244 mode = DMA_IN(chan, &chan->regs->mr, 32);
248 mode &= ~FSL_DMA_MR_DAHE;
254 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
258 DMA_OUT(chan, &chan->regs->mr, mode, 32);
262 * fsl_chan_set_request_count - Set DMA Request Count for external control
263 * @chan : Freescale DMA channel
264 * @size : Number of bytes to transfer in a single request
266 * The Freescale DMA channel can be controlled by the external signal DREQ#.
267 * The DMA request count is how many bytes are allowed to transfer before
268 * pausing the channel, after which a new assertion of DREQ# resumes channel
271 * A size of 0 disables external pause control. The maximum size is 1024.
273 static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
279 mode = DMA_IN(chan, &chan->regs->mr, 32);
280 mode |= (__ilog2(size) << 24) & 0x0f000000;
282 DMA_OUT(chan, &chan->regs->mr, mode, 32);
286 * fsl_chan_toggle_ext_pause - Toggle channel external pause status
287 * @chan : Freescale DMA channel
288 * @enable : 0 is disabled, 1 is enabled.
290 * The Freescale DMA channel can be controlled by the external signal DREQ#.
291 * The DMA Request Count feature should be used in addition to this feature
292 * to set the number of bytes to transfer before pausing the channel.
294 static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
297 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
299 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
303 * fsl_chan_toggle_ext_start - Toggle channel external start status
304 * @chan : Freescale DMA channel
305 * @enable : 0 is disabled, 1 is enabled.
307 * If enable the external start, the channel can be started by an
308 * external DMA start pin. So the dma_start() does not start the
309 * transfer immediately. The DMA channel will wait for the
310 * control pin asserted.
312 static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
315 chan->feature |= FSL_DMA_CHAN_START_EXT;
317 chan->feature &= ~FSL_DMA_CHAN_START_EXT;
320 static void append_ld_queue(struct fsldma_chan *chan,
321 struct fsl_desc_sw *desc)
323 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
325 if (list_empty(&chan->ld_pending))
329 * Add the hardware descriptor to the chain of hardware descriptors
330 * that already exists in memory.
332 * This will un-set the EOL bit of the existing transaction, and the
333 * last link in this transaction will become the EOL descriptor.
335 set_desc_next(chan, &tail->hw, desc->async_tx.phys);
338 * Add the software descriptor and all children to the list
339 * of pending transactions
342 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
345 static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
347 struct fsldma_chan *chan = to_fsl_chan(tx->chan);
348 struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
349 struct fsl_desc_sw *child;
353 spin_lock_irqsave(&chan->desc_lock, flags);
356 * assign cookies to all of the software descriptors
357 * that make up this transaction
359 cookie = chan->common.cookie;
360 list_for_each_entry(child, &desc->tx_list, node) {
365 child->async_tx.cookie = cookie;
368 chan->common.cookie = cookie;
370 /* put this transaction onto the tail of the pending queue */
371 append_ld_queue(chan, desc);
373 spin_unlock_irqrestore(&chan->desc_lock, flags);
379 * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
380 * @chan : Freescale DMA channel
382 * Return - The descriptor allocated. NULL for failed.
384 static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
385 struct fsldma_chan *chan)
387 struct fsl_desc_sw *desc;
390 desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
392 dev_dbg(chan->dev, "out of memory for link desc\n");
396 memset(desc, 0, sizeof(*desc));
397 INIT_LIST_HEAD(&desc->tx_list);
398 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
399 desc->async_tx.tx_submit = fsl_dma_tx_submit;
400 desc->async_tx.phys = pdesc;
407 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
408 * @chan : Freescale DMA channel
410 * This function will create a dma pool for descriptor allocation.
412 * Return - The number of descriptors allocated.
414 static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
416 struct fsldma_chan *chan = to_fsl_chan(dchan);
418 /* Has this channel already been allocated? */
423 * We need the descriptor to be aligned to 32bytes
424 * for meeting FSL DMA specification requirement.
426 chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool",
428 sizeof(struct fsl_desc_sw),
429 __alignof__(struct fsl_desc_sw), 0);
430 if (!chan->desc_pool) {
431 dev_err(chan->dev, "unable to allocate channel %d "
432 "descriptor pool\n", chan->id);
436 /* there is at least one descriptor free to be allocated */
441 * fsldma_free_desc_list - Free all descriptors in a queue
442 * @chan: Freescae DMA channel
443 * @list: the list to free
445 * LOCKING: must hold chan->desc_lock
447 static void fsldma_free_desc_list(struct fsldma_chan *chan,
448 struct list_head *list)
450 struct fsl_desc_sw *desc, *_desc;
452 list_for_each_entry_safe(desc, _desc, list, node) {
453 list_del(&desc->node);
454 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
458 static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
459 struct list_head *list)
461 struct fsl_desc_sw *desc, *_desc;
463 list_for_each_entry_safe_reverse(desc, _desc, list, node) {
464 list_del(&desc->node);
465 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
470 * fsl_dma_free_chan_resources - Free all resources of the channel.
471 * @chan : Freescale DMA channel
473 static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
475 struct fsldma_chan *chan = to_fsl_chan(dchan);
478 dev_dbg(chan->dev, "Free all channel resources.\n");
479 spin_lock_irqsave(&chan->desc_lock, flags);
480 fsldma_free_desc_list(chan, &chan->ld_pending);
481 fsldma_free_desc_list(chan, &chan->ld_running);
482 spin_unlock_irqrestore(&chan->desc_lock, flags);
484 dma_pool_destroy(chan->desc_pool);
485 chan->desc_pool = NULL;
488 static struct dma_async_tx_descriptor *
489 fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags)
491 struct fsldma_chan *chan;
492 struct fsl_desc_sw *new;
497 chan = to_fsl_chan(dchan);
499 new = fsl_dma_alloc_descriptor(chan);
501 dev_err(chan->dev, "No free memory for link descriptor\n");
505 new->async_tx.cookie = -EBUSY;
506 new->async_tx.flags = flags;
508 /* Insert the link descriptor to the LD ring */
509 list_add_tail(&new->node, &new->tx_list);
511 /* Set End-of-link to the last link descriptor of new list*/
512 set_ld_eol(chan, new);
514 return &new->async_tx;
517 static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
518 struct dma_chan *dchan, dma_addr_t dma_dst, dma_addr_t dma_src,
519 size_t len, unsigned long flags)
521 struct fsldma_chan *chan;
522 struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
531 chan = to_fsl_chan(dchan);
535 /* Allocate the link descriptor from DMA pool */
536 new = fsl_dma_alloc_descriptor(chan);
539 "No free memory for link descriptor\n");
542 #ifdef FSL_DMA_LD_DEBUG
543 dev_dbg(chan->dev, "new link desc alloc %p\n", new);
546 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
548 set_desc_cnt(chan, &new->hw, copy);
549 set_desc_src(chan, &new->hw, dma_src);
550 set_desc_dst(chan, &new->hw, dma_dst);
555 set_desc_next(chan, &prev->hw, new->async_tx.phys);
557 new->async_tx.cookie = 0;
558 async_tx_ack(&new->async_tx);
565 /* Insert the link descriptor to the LD ring */
566 list_add_tail(&new->node, &first->tx_list);
569 new->async_tx.flags = flags; /* client is in control of this ack */
570 new->async_tx.cookie = -EBUSY;
572 /* Set End-of-link to the last link descriptor of new list*/
573 set_ld_eol(chan, new);
575 return &first->async_tx;
581 fsldma_free_desc_list_reverse(chan, &first->tx_list);
586 * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
588 * @sgl: scatterlist to transfer to/from
589 * @sg_len: number of entries in @scatterlist
590 * @direction: DMA direction
591 * @flags: DMAEngine flags
593 * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the
594 * DMA_SLAVE API, this gets the device-specific information from the
595 * chan->private variable.
597 static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
598 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
599 enum dma_data_direction direction, unsigned long flags)
601 struct fsldma_chan *chan;
602 struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
603 struct fsl_dma_slave *slave;
607 struct scatterlist *sg;
610 struct fsl_dma_hw_addr *hw;
611 dma_addr_t dma_dst, dma_src;
619 chan = to_fsl_chan(dchan);
620 slave = dchan->private;
622 if (list_empty(&slave->addresses))
625 hw = list_first_entry(&slave->addresses, struct fsl_dma_hw_addr, entry);
629 * Build the hardware transaction to copy from the scatterlist to
630 * the hardware, or from the hardware to the scatterlist
632 * If you are copying from the hardware to the scatterlist and it
633 * takes two hardware entries to fill an entire page, then both
634 * hardware entries will be coalesced into the same page
636 * If you are copying from the scatterlist to the hardware and a
637 * single page can fill two hardware entries, then the data will
638 * be read out of the page into the first hardware entry, and so on
640 for_each_sg(sgl, sg, sg_len, i) {
643 /* Loop until the entire scatterlist entry is used */
644 while (sg_used < sg_dma_len(sg)) {
647 * If we've used up the current hardware address/length
648 * pair, we need to load a new one
650 * This is done in a while loop so that descriptors with
651 * length == 0 will be skipped
653 while (hw_used >= hw->length) {
656 * If the current hardware entry is the last
657 * entry in the list, we're finished
659 if (list_is_last(&hw->entry, &slave->addresses))
662 /* Get the next hardware address/length pair */
663 hw = list_entry(hw->entry.next,
664 struct fsl_dma_hw_addr, entry);
668 /* Allocate the link descriptor from DMA pool */
669 new = fsl_dma_alloc_descriptor(chan);
671 dev_err(chan->dev, "No free memory for "
672 "link descriptor\n");
675 #ifdef FSL_DMA_LD_DEBUG
676 dev_dbg(chan->dev, "new link desc alloc %p\n", new);
680 * Calculate the maximum number of bytes to transfer,
681 * making sure it is less than the DMA controller limit
683 copy = min_t(size_t, sg_dma_len(sg) - sg_used,
684 hw->length - hw_used);
685 copy = min_t(size_t, copy, FSL_DMA_BCR_MAX_CNT);
689 * from the hardware to the scatterlist
692 * from the scatterlist to the hardware
694 if (direction == DMA_FROM_DEVICE) {
695 dma_src = hw->address + hw_used;
696 dma_dst = sg_dma_address(sg) + sg_used;
698 dma_src = sg_dma_address(sg) + sg_used;
699 dma_dst = hw->address + hw_used;
702 /* Fill in the descriptor */
703 set_desc_cnt(chan, &new->hw, copy);
704 set_desc_src(chan, &new->hw, dma_src);
705 set_desc_dst(chan, &new->hw, dma_dst);
708 * If this is not the first descriptor, chain the
709 * current descriptor after the previous descriptor
714 set_desc_next(chan, &prev->hw,
718 new->async_tx.cookie = 0;
719 async_tx_ack(&new->async_tx);
725 /* Insert the link descriptor into the LD ring */
726 list_add_tail(&new->node, &first->tx_list);
732 /* All of the hardware address/length pairs had length == 0 */
736 new->async_tx.flags = flags;
737 new->async_tx.cookie = -EBUSY;
739 /* Set End-of-link to the last link descriptor of new list */
740 set_ld_eol(chan, new);
742 /* Enable extra controller features */
743 if (chan->set_src_loop_size)
744 chan->set_src_loop_size(chan, slave->src_loop_size);
746 if (chan->set_dst_loop_size)
747 chan->set_dst_loop_size(chan, slave->dst_loop_size);
749 if (chan->toggle_ext_start)
750 chan->toggle_ext_start(chan, slave->external_start);
752 if (chan->toggle_ext_pause)
753 chan->toggle_ext_pause(chan, slave->external_pause);
755 if (chan->set_request_count)
756 chan->set_request_count(chan, slave->request_count);
758 return &first->async_tx;
761 /* If first was not set, then we failed to allocate the very first
762 * descriptor, and we're done */
767 * First is set, so all of the descriptors we allocated have been added
768 * to first->tx_list, INCLUDING "first" itself. Therefore we
769 * must traverse the list backwards freeing each descriptor in turn
771 * We're re-using variables for the loop, oh well
773 fsldma_free_desc_list_reverse(chan, &first->tx_list);
777 static int fsl_dma_device_control(struct dma_chan *dchan,
778 enum dma_ctrl_cmd cmd)
780 struct fsldma_chan *chan;
783 /* Only supports DMA_TERMINATE_ALL */
784 if (cmd != DMA_TERMINATE_ALL)
790 chan = to_fsl_chan(dchan);
792 /* Halt the DMA engine */
795 spin_lock_irqsave(&chan->desc_lock, flags);
797 /* Remove and free all of the descriptors in the LD queue */
798 fsldma_free_desc_list(chan, &chan->ld_pending);
799 fsldma_free_desc_list(chan, &chan->ld_running);
801 spin_unlock_irqrestore(&chan->desc_lock, flags);
807 * fsl_dma_update_completed_cookie - Update the completed cookie.
808 * @chan : Freescale DMA channel
812 static void fsl_dma_update_completed_cookie(struct fsldma_chan *chan)
814 struct fsl_desc_sw *desc;
818 spin_lock_irqsave(&chan->desc_lock, flags);
820 if (list_empty(&chan->ld_running)) {
821 dev_dbg(chan->dev, "no running descriptors\n");
825 /* Get the last descriptor, update the cookie to that */
826 desc = to_fsl_desc(chan->ld_running.prev);
827 if (dma_is_idle(chan))
828 cookie = desc->async_tx.cookie;
830 cookie = desc->async_tx.cookie - 1;
831 if (unlikely(cookie < DMA_MIN_COOKIE))
832 cookie = DMA_MAX_COOKIE;
835 chan->completed_cookie = cookie;
838 spin_unlock_irqrestore(&chan->desc_lock, flags);
842 * fsldma_desc_status - Check the status of a descriptor
843 * @chan: Freescale DMA channel
844 * @desc: DMA SW descriptor
846 * This function will return the status of the given descriptor
848 static enum dma_status fsldma_desc_status(struct fsldma_chan *chan,
849 struct fsl_desc_sw *desc)
851 return dma_async_is_complete(desc->async_tx.cookie,
852 chan->completed_cookie,
853 chan->common.cookie);
857 * fsl_chan_ld_cleanup - Clean up link descriptors
858 * @chan : Freescale DMA channel
860 * This function clean up the ld_queue of DMA channel.
862 static void fsl_chan_ld_cleanup(struct fsldma_chan *chan)
864 struct fsl_desc_sw *desc, *_desc;
867 spin_lock_irqsave(&chan->desc_lock, flags);
869 dev_dbg(chan->dev, "chan completed_cookie = %d\n", chan->completed_cookie);
870 list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
871 dma_async_tx_callback callback;
872 void *callback_param;
874 if (fsldma_desc_status(chan, desc) == DMA_IN_PROGRESS)
877 /* Remove from the list of running transactions */
878 list_del(&desc->node);
880 /* Run the link descriptor callback function */
881 callback = desc->async_tx.callback;
882 callback_param = desc->async_tx.callback_param;
884 spin_unlock_irqrestore(&chan->desc_lock, flags);
885 dev_dbg(chan->dev, "LD %p callback\n", desc);
886 callback(callback_param);
887 spin_lock_irqsave(&chan->desc_lock, flags);
890 /* Run any dependencies, then free the descriptor */
891 dma_run_dependencies(&desc->async_tx);
892 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
895 spin_unlock_irqrestore(&chan->desc_lock, flags);
899 * fsl_chan_xfer_ld_queue - transfer any pending transactions
900 * @chan : Freescale DMA channel
902 * This will make sure that any pending transactions will be run.
903 * If the DMA controller is idle, it will be started. Otherwise,
904 * the DMA controller's interrupt handler will start any pending
905 * transactions when it becomes idle.
907 static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
909 struct fsl_desc_sw *desc;
912 spin_lock_irqsave(&chan->desc_lock, flags);
915 * If the list of pending descriptors is empty, then we
916 * don't need to do any work at all
918 if (list_empty(&chan->ld_pending)) {
919 dev_dbg(chan->dev, "no pending LDs\n");
924 * The DMA controller is not idle, which means the interrupt
925 * handler will start any queued transactions when it runs
926 * at the end of the current transaction
928 if (!dma_is_idle(chan)) {
929 dev_dbg(chan->dev, "DMA controller still busy\n");
935 * make sure the dma_halt() function really un-wedges the
936 * controller as much as possible
941 * If there are some link descriptors which have not been
942 * transferred, we need to start the controller
946 * Move all elements from the queue of pending transactions
947 * onto the list of running transactions
949 desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
950 list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
953 * Program the descriptor's address into the DMA controller,
954 * then start the DMA transaction
956 set_cdar(chan, desc->async_tx.phys);
960 spin_unlock_irqrestore(&chan->desc_lock, flags);
964 * fsl_dma_memcpy_issue_pending - Issue the DMA start command
965 * @chan : Freescale DMA channel
967 static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
969 struct fsldma_chan *chan = to_fsl_chan(dchan);
970 fsl_chan_xfer_ld_queue(chan);
974 * fsl_tx_status - Determine the DMA status
975 * @chan : Freescale DMA channel
977 static enum dma_status fsl_tx_status(struct dma_chan *dchan,
979 struct dma_tx_state *txstate)
981 struct fsldma_chan *chan = to_fsl_chan(dchan);
982 dma_cookie_t last_used;
983 dma_cookie_t last_complete;
985 fsl_chan_ld_cleanup(chan);
987 last_used = dchan->cookie;
988 last_complete = chan->completed_cookie;
991 txstate->last = last_complete;
992 txstate->used = last_used;
993 txstate->residue = 0;
996 return dma_async_is_complete(cookie, last_complete, last_used);
999 /*----------------------------------------------------------------------------*/
1000 /* Interrupt Handling */
1001 /*----------------------------------------------------------------------------*/
1003 static irqreturn_t fsldma_chan_irq(int irq, void *data)
1005 struct fsldma_chan *chan = data;
1006 int update_cookie = 0;
1010 /* save and clear the status register */
1011 stat = get_sr(chan);
1013 dev_dbg(chan->dev, "irq: channel %d, stat = 0x%x\n", chan->id, stat);
1015 stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
1019 if (stat & FSL_DMA_SR_TE)
1020 dev_err(chan->dev, "Transfer Error!\n");
1024 * The DMA_INTERRUPT async_tx is a NULL transfer, which will
1025 * triger a PE interrupt.
1027 if (stat & FSL_DMA_SR_PE) {
1028 dev_dbg(chan->dev, "irq: Programming Error INT\n");
1029 if (get_bcr(chan) == 0) {
1030 /* BCR register is 0, this is a DMA_INTERRUPT async_tx.
1031 * Now, update the completed cookie, and continue the
1032 * next uncompleted transfer.
1037 stat &= ~FSL_DMA_SR_PE;
1041 * If the link descriptor segment transfer finishes,
1042 * we will recycle the used descriptor.
1044 if (stat & FSL_DMA_SR_EOSI) {
1045 dev_dbg(chan->dev, "irq: End-of-segments INT\n");
1046 dev_dbg(chan->dev, "irq: clndar 0x%llx, nlndar 0x%llx\n",
1047 (unsigned long long)get_cdar(chan),
1048 (unsigned long long)get_ndar(chan));
1049 stat &= ~FSL_DMA_SR_EOSI;
1054 * For MPC8349, EOCDI event need to update cookie
1055 * and start the next transfer if it exist.
1057 if (stat & FSL_DMA_SR_EOCDI) {
1058 dev_dbg(chan->dev, "irq: End-of-Chain link INT\n");
1059 stat &= ~FSL_DMA_SR_EOCDI;
1065 * If it current transfer is the end-of-transfer,
1066 * we should clear the Channel Start bit for
1067 * prepare next transfer.
1069 if (stat & FSL_DMA_SR_EOLNI) {
1070 dev_dbg(chan->dev, "irq: End-of-link INT\n");
1071 stat &= ~FSL_DMA_SR_EOLNI;
1076 fsl_dma_update_completed_cookie(chan);
1078 fsl_chan_xfer_ld_queue(chan);
1080 dev_dbg(chan->dev, "irq: unhandled sr 0x%02x\n", stat);
1082 dev_dbg(chan->dev, "irq: Exit\n");
1083 tasklet_schedule(&chan->tasklet);
1087 static void dma_do_tasklet(unsigned long data)
1089 struct fsldma_chan *chan = (struct fsldma_chan *)data;
1090 fsl_chan_ld_cleanup(chan);
1093 static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
1095 struct fsldma_device *fdev = data;
1096 struct fsldma_chan *chan;
1097 unsigned int handled = 0;
1101 gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs)
1102 : in_le32(fdev->regs);
1104 dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr);
1106 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1107 chan = fdev->chan[i];
1112 dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
1113 fsldma_chan_irq(irq, chan);
1121 return IRQ_RETVAL(handled);
1124 static void fsldma_free_irqs(struct fsldma_device *fdev)
1126 struct fsldma_chan *chan;
1129 if (fdev->irq != NO_IRQ) {
1130 dev_dbg(fdev->dev, "free per-controller IRQ\n");
1131 free_irq(fdev->irq, fdev);
1135 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1136 chan = fdev->chan[i];
1137 if (chan && chan->irq != NO_IRQ) {
1138 dev_dbg(fdev->dev, "free channel %d IRQ\n", chan->id);
1139 free_irq(chan->irq, chan);
1144 static int fsldma_request_irqs(struct fsldma_device *fdev)
1146 struct fsldma_chan *chan;
1150 /* if we have a per-controller IRQ, use that */
1151 if (fdev->irq != NO_IRQ) {
1152 dev_dbg(fdev->dev, "request per-controller IRQ\n");
1153 ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED,
1154 "fsldma-controller", fdev);
1158 /* no per-controller IRQ, use the per-channel IRQs */
1159 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1160 chan = fdev->chan[i];
1164 if (chan->irq == NO_IRQ) {
1165 dev_err(fdev->dev, "no interrupts property defined for "
1166 "DMA channel %d. Please fix your "
1167 "device tree\n", chan->id);
1172 dev_dbg(fdev->dev, "request channel %d IRQ\n", chan->id);
1173 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
1174 "fsldma-chan", chan);
1176 dev_err(fdev->dev, "unable to request IRQ for DMA "
1177 "channel %d\n", chan->id);
1185 for (/* none */; i >= 0; i--) {
1186 chan = fdev->chan[i];
1190 if (chan->irq == NO_IRQ)
1193 free_irq(chan->irq, chan);
1199 /*----------------------------------------------------------------------------*/
1200 /* OpenFirmware Subsystem */
1201 /*----------------------------------------------------------------------------*/
1203 static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev,
1204 struct device_node *node, u32 feature, const char *compatible)
1206 struct fsldma_chan *chan;
1207 struct resource res;
1211 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1213 dev_err(fdev->dev, "no free memory for DMA channels!\n");
1218 /* ioremap registers for use */
1219 chan->regs = of_iomap(node, 0);
1221 dev_err(fdev->dev, "unable to ioremap registers\n");
1226 err = of_address_to_resource(node, 0, &res);
1228 dev_err(fdev->dev, "unable to find 'reg' property\n");
1229 goto out_iounmap_regs;
1232 chan->feature = feature;
1234 fdev->feature = chan->feature;
1237 * If the DMA device's feature is different than the feature
1238 * of its channels, report the bug
1240 WARN_ON(fdev->feature != chan->feature);
1242 chan->dev = fdev->dev;
1243 chan->id = ((res.start - 0x100) & 0xfff) >> 7;
1244 if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
1245 dev_err(fdev->dev, "too many channels for device\n");
1247 goto out_iounmap_regs;
1250 fdev->chan[chan->id] = chan;
1251 tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
1253 /* Initialize the channel */
1256 /* Clear cdar registers */
1259 switch (chan->feature & FSL_DMA_IP_MASK) {
1260 case FSL_DMA_IP_85XX:
1261 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
1262 case FSL_DMA_IP_83XX:
1263 chan->toggle_ext_start = fsl_chan_toggle_ext_start;
1264 chan->set_src_loop_size = fsl_chan_set_src_loop_size;
1265 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
1266 chan->set_request_count = fsl_chan_set_request_count;
1269 spin_lock_init(&chan->desc_lock);
1270 INIT_LIST_HEAD(&chan->ld_pending);
1271 INIT_LIST_HEAD(&chan->ld_running);
1273 chan->common.device = &fdev->common;
1275 /* find the IRQ line, if it exists in the device tree */
1276 chan->irq = irq_of_parse_and_map(node, 0);
1278 /* Add the channel to DMA device channel list */
1279 list_add_tail(&chan->common.device_node, &fdev->common.channels);
1280 fdev->common.chancnt++;
1282 dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
1283 chan->irq != NO_IRQ ? chan->irq : fdev->irq);
1288 iounmap(chan->regs);
1295 static void fsl_dma_chan_remove(struct fsldma_chan *chan)
1297 irq_dispose_mapping(chan->irq);
1298 list_del(&chan->common.device_node);
1299 iounmap(chan->regs);
1303 static int __devinit fsldma_of_probe(struct of_device *op,
1304 const struct of_device_id *match)
1306 struct fsldma_device *fdev;
1307 struct device_node *child;
1310 fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
1312 dev_err(&op->dev, "No enough memory for 'priv'\n");
1317 fdev->dev = &op->dev;
1318 INIT_LIST_HEAD(&fdev->common.channels);
1320 /* ioremap the registers for use */
1321 fdev->regs = of_iomap(op->node, 0);
1323 dev_err(&op->dev, "unable to ioremap registers\n");
1328 /* map the channel IRQ if it exists, but don't hookup the handler yet */
1329 fdev->irq = irq_of_parse_and_map(op->node, 0);
1331 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
1332 dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
1333 dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
1334 fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
1335 fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
1336 fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt;
1337 fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
1338 fdev->common.device_tx_status = fsl_tx_status;
1339 fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
1340 fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg;
1341 fdev->common.device_control = fsl_dma_device_control;
1342 fdev->common.dev = &op->dev;
1344 dev_set_drvdata(&op->dev, fdev);
1347 * We cannot use of_platform_bus_probe() because there is no
1348 * of_platform_bus_remove(). Instead, we manually instantiate every DMA
1351 for_each_child_of_node(op->node, child) {
1352 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
1353 fsl_dma_chan_probe(fdev, child,
1354 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
1355 "fsl,eloplus-dma-channel");
1358 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) {
1359 fsl_dma_chan_probe(fdev, child,
1360 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
1361 "fsl,elo-dma-channel");
1366 * Hookup the IRQ handler(s)
1368 * If we have a per-controller interrupt, we prefer that to the
1369 * per-channel interrupts to reduce the number of shared interrupt
1370 * handlers on the same IRQ line
1372 err = fsldma_request_irqs(fdev);
1374 dev_err(fdev->dev, "unable to request IRQs\n");
1378 dma_async_device_register(&fdev->common);
1382 irq_dispose_mapping(fdev->irq);
1388 static int fsldma_of_remove(struct of_device *op)
1390 struct fsldma_device *fdev;
1393 fdev = dev_get_drvdata(&op->dev);
1394 dma_async_device_unregister(&fdev->common);
1396 fsldma_free_irqs(fdev);
1398 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1400 fsl_dma_chan_remove(fdev->chan[i]);
1403 iounmap(fdev->regs);
1404 dev_set_drvdata(&op->dev, NULL);
1410 static const struct of_device_id fsldma_of_ids[] = {
1411 { .compatible = "fsl,eloplus-dma", },
1412 { .compatible = "fsl,elo-dma", },
1416 static struct of_platform_driver fsldma_of_driver = {
1417 .name = "fsl-elo-dma",
1418 .match_table = fsldma_of_ids,
1419 .probe = fsldma_of_probe,
1420 .remove = fsldma_of_remove,
1423 /*----------------------------------------------------------------------------*/
1424 /* Module Init / Exit */
1425 /*----------------------------------------------------------------------------*/
1427 static __init int fsldma_init(void)
1431 pr_info("Freescale Elo / Elo Plus DMA driver\n");
1433 ret = of_register_platform_driver(&fsldma_of_driver);
1435 pr_err("fsldma: failed to register platform driver\n");
1440 static void __exit fsldma_exit(void)
1442 of_unregister_platform_driver(&fsldma_of_driver);
1445 subsys_initcall(fsldma_init);
1446 module_exit(fsldma_exit);
1448 MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver");
1449 MODULE_LICENSE("GPL");