2 * Freescale MPC85xx, MPC83xx DMA Engine support
4 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
7 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
8 * Ebony Zhu <ebony.zhu@freescale.com>, May 2007
11 * DMA engine driver for Freescale MPC8540 DMA controller, which is
12 * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
13 * The support for MPC8349 DMA controller is also added.
15 * This driver instructs the DMA controller to issue the PCI Read Multiple
16 * command for PCI read operations, instead of using the default PCI Read Line
17 * command. Please be aware that this setting may result in read pre-fetching
20 * This is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/dmaengine.h>
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/dmapool.h>
36 #include <linux/of_address.h>
37 #include <linux/of_irq.h>
38 #include <linux/of_platform.h>
40 #include "dmaengine.h"
43 #define chan_dbg(chan, fmt, arg...) \
44 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
45 #define chan_err(chan, fmt, arg...) \
46 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
48 static const char msg_ld_oom[] = "No free memory for link descriptor";
54 static void set_sr(struct fsldma_chan *chan, u32 val)
56 DMA_OUT(chan, &chan->regs->sr, val, 32);
59 static u32 get_sr(struct fsldma_chan *chan)
61 return DMA_IN(chan, &chan->regs->sr, 32);
64 static void set_mr(struct fsldma_chan *chan, u32 val)
66 DMA_OUT(chan, &chan->regs->mr, val, 32);
69 static u32 get_mr(struct fsldma_chan *chan)
71 return DMA_IN(chan, &chan->regs->mr, 32);
74 static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
76 DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
79 static dma_addr_t get_cdar(struct fsldma_chan *chan)
81 return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
84 static void set_bcr(struct fsldma_chan *chan, u32 val)
86 DMA_OUT(chan, &chan->regs->bcr, val, 32);
89 static u32 get_bcr(struct fsldma_chan *chan)
91 return DMA_IN(chan, &chan->regs->bcr, 32);
98 static void set_desc_cnt(struct fsldma_chan *chan,
99 struct fsl_dma_ld_hw *hw, u32 count)
101 hw->count = CPU_TO_DMA(chan, count, 32);
104 static void set_desc_src(struct fsldma_chan *chan,
105 struct fsl_dma_ld_hw *hw, dma_addr_t src)
109 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
110 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
111 hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
114 static void set_desc_dst(struct fsldma_chan *chan,
115 struct fsl_dma_ld_hw *hw, dma_addr_t dst)
119 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
120 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
121 hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
124 static void set_desc_next(struct fsldma_chan *chan,
125 struct fsl_dma_ld_hw *hw, dma_addr_t next)
129 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
131 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
134 static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
138 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
141 desc->hw.next_ln_addr = CPU_TO_DMA(chan,
142 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
147 * DMA Engine Hardware Control Helpers
150 static void dma_init(struct fsldma_chan *chan)
152 /* Reset the channel */
155 switch (chan->feature & FSL_DMA_IP_MASK) {
156 case FSL_DMA_IP_85XX:
157 /* Set the channel to below modes:
158 * EIE - Error interrupt enable
159 * EOLNIE - End of links interrupt enable
160 * BWC - Bandwidth sharing among channels
162 set_mr(chan, FSL_DMA_MR_BWC | FSL_DMA_MR_EIE
163 | FSL_DMA_MR_EOLNIE);
165 case FSL_DMA_IP_83XX:
166 /* Set the channel to below modes:
167 * EOTIE - End-of-transfer interrupt enable
168 * PRC_RM - PCI read multiple
170 set_mr(chan, FSL_DMA_MR_EOTIE | FSL_DMA_MR_PRC_RM);
175 static int dma_is_idle(struct fsldma_chan *chan)
177 u32 sr = get_sr(chan);
178 return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
182 * Start the DMA controller
185 * - the CDAR register must point to the start descriptor
186 * - the MRn[CS] bit must be cleared
188 static void dma_start(struct fsldma_chan *chan)
194 if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
196 mode |= FSL_DMA_MR_EMP_EN;
198 mode &= ~FSL_DMA_MR_EMP_EN;
201 if (chan->feature & FSL_DMA_CHAN_START_EXT) {
202 mode |= FSL_DMA_MR_EMS_EN;
204 mode &= ~FSL_DMA_MR_EMS_EN;
205 mode |= FSL_DMA_MR_CS;
211 static void dma_halt(struct fsldma_chan *chan)
216 /* read the mode register */
220 * The 85xx controller supports channel abort, which will stop
221 * the current transfer. On 83xx, this bit is the transfer error
222 * mask bit, which should not be changed.
224 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
225 mode |= FSL_DMA_MR_CA;
228 mode &= ~FSL_DMA_MR_CA;
231 /* stop the DMA controller */
232 mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN);
235 /* wait for the DMA controller to become idle */
236 for (i = 0; i < 100; i++) {
237 if (dma_is_idle(chan))
243 if (!dma_is_idle(chan))
244 chan_err(chan, "DMA halt timeout!\n");
248 * fsl_chan_set_src_loop_size - Set source address hold transfer size
249 * @chan : Freescale DMA channel
250 * @size : Address loop size, 0 for disable loop
252 * The set source address hold transfer size. The source
253 * address hold or loop transfer size is when the DMA transfer
254 * data from source address (SA), if the loop size is 4, the DMA will
255 * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
256 * SA + 1 ... and so on.
258 static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
266 mode &= ~FSL_DMA_MR_SAHE;
272 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
280 * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
281 * @chan : Freescale DMA channel
282 * @size : Address loop size, 0 for disable loop
284 * The set destination address hold transfer size. The destination
285 * address hold or loop transfer size is when the DMA transfer
286 * data to destination address (TA), if the loop size is 4, the DMA will
287 * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
288 * TA + 1 ... and so on.
290 static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
298 mode &= ~FSL_DMA_MR_DAHE;
304 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
312 * fsl_chan_set_request_count - Set DMA Request Count for external control
313 * @chan : Freescale DMA channel
314 * @size : Number of bytes to transfer in a single request
316 * The Freescale DMA channel can be controlled by the external signal DREQ#.
317 * The DMA request count is how many bytes are allowed to transfer before
318 * pausing the channel, after which a new assertion of DREQ# resumes channel
321 * A size of 0 disables external pause control. The maximum size is 1024.
323 static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
330 mode |= (__ilog2(size) << 24) & 0x0f000000;
336 * fsl_chan_toggle_ext_pause - Toggle channel external pause status
337 * @chan : Freescale DMA channel
338 * @enable : 0 is disabled, 1 is enabled.
340 * The Freescale DMA channel can be controlled by the external signal DREQ#.
341 * The DMA Request Count feature should be used in addition to this feature
342 * to set the number of bytes to transfer before pausing the channel.
344 static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
347 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
349 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
353 * fsl_chan_toggle_ext_start - Toggle channel external start status
354 * @chan : Freescale DMA channel
355 * @enable : 0 is disabled, 1 is enabled.
357 * If enable the external start, the channel can be started by an
358 * external DMA start pin. So the dma_start() does not start the
359 * transfer immediately. The DMA channel will wait for the
360 * control pin asserted.
362 static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
365 chan->feature |= FSL_DMA_CHAN_START_EXT;
367 chan->feature &= ~FSL_DMA_CHAN_START_EXT;
370 static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
372 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
374 if (list_empty(&chan->ld_pending))
378 * Add the hardware descriptor to the chain of hardware descriptors
379 * that already exists in memory.
381 * This will un-set the EOL bit of the existing transaction, and the
382 * last link in this transaction will become the EOL descriptor.
384 set_desc_next(chan, &tail->hw, desc->async_tx.phys);
387 * Add the software descriptor and all children to the list
388 * of pending transactions
391 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
394 static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
396 struct fsldma_chan *chan = to_fsl_chan(tx->chan);
397 struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
398 struct fsl_desc_sw *child;
400 dma_cookie_t cookie = -EINVAL;
402 spin_lock_irqsave(&chan->desc_lock, flags);
405 * assign cookies to all of the software descriptors
406 * that make up this transaction
408 list_for_each_entry(child, &desc->tx_list, node) {
409 cookie = dma_cookie_assign(&child->async_tx);
412 /* put this transaction onto the tail of the pending queue */
413 append_ld_queue(chan, desc);
415 spin_unlock_irqrestore(&chan->desc_lock, flags);
421 * fsl_dma_free_descriptor - Free descriptor from channel's DMA pool.
422 * @chan : Freescale DMA channel
423 * @desc: descriptor to be freed
425 static void fsl_dma_free_descriptor(struct fsldma_chan *chan,
426 struct fsl_desc_sw *desc)
428 list_del(&desc->node);
429 chan_dbg(chan, "LD %p free\n", desc);
430 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
434 * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
435 * @chan : Freescale DMA channel
437 * Return - The descriptor allocated. NULL for failed.
439 static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
441 struct fsl_desc_sw *desc;
444 desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
446 chan_dbg(chan, "out of memory for link descriptor\n");
450 memset(desc, 0, sizeof(*desc));
451 INIT_LIST_HEAD(&desc->tx_list);
452 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
453 desc->async_tx.tx_submit = fsl_dma_tx_submit;
454 desc->async_tx.phys = pdesc;
456 chan_dbg(chan, "LD %p allocated\n", desc);
462 * fsl_chan_xfer_ld_queue - transfer any pending transactions
463 * @chan : Freescale DMA channel
465 * HARDWARE STATE: idle
466 * LOCKING: must hold chan->desc_lock
468 static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
470 struct fsl_desc_sw *desc;
473 * If the list of pending descriptors is empty, then we
474 * don't need to do any work at all
476 if (list_empty(&chan->ld_pending)) {
477 chan_dbg(chan, "no pending LDs\n");
482 * The DMA controller is not idle, which means that the interrupt
483 * handler will start any queued transactions when it runs after
484 * this transaction finishes
487 chan_dbg(chan, "DMA controller still busy\n");
492 * If there are some link descriptors which have not been
493 * transferred, we need to start the controller
497 * Move all elements from the queue of pending transactions
498 * onto the list of running transactions
500 chan_dbg(chan, "idle, starting controller\n");
501 desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
502 list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
505 * The 85xx DMA controller doesn't clear the channel start bit
506 * automatically at the end of a transfer. Therefore we must clear
507 * it in software before starting the transfer.
509 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
513 mode &= ~FSL_DMA_MR_CS;
518 * Program the descriptor's address into the DMA controller,
519 * then start the DMA transaction
521 set_cdar(chan, desc->async_tx.phys);
529 * fsldma_cleanup_descriptor - cleanup and free a single link descriptor
530 * @chan: Freescale DMA channel
531 * @desc: descriptor to cleanup and free
533 * This function is used on a descriptor which has been executed by the DMA
534 * controller. It will run any callbacks, submit any dependencies, and then
535 * free the descriptor.
537 static void fsldma_cleanup_descriptor(struct fsldma_chan *chan,
538 struct fsl_desc_sw *desc)
540 struct dma_async_tx_descriptor *txd = &desc->async_tx;
542 /* Run the link descriptor callback function */
544 chan_dbg(chan, "LD %p callback\n", desc);
545 txd->callback(txd->callback_param);
548 /* Run any dependencies */
549 dma_run_dependencies(txd);
551 dma_descriptor_unmap(txd);
552 chan_dbg(chan, "LD %p free\n", desc);
553 dma_pool_free(chan->desc_pool, desc, txd->phys);
557 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
558 * @chan : Freescale DMA channel
560 * This function will create a dma pool for descriptor allocation.
562 * Return - The number of descriptors allocated.
564 static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
566 struct fsldma_chan *chan = to_fsl_chan(dchan);
568 /* Has this channel already been allocated? */
573 * We need the descriptor to be aligned to 32bytes
574 * for meeting FSL DMA specification requirement.
576 chan->desc_pool = dma_pool_create(chan->name, chan->dev,
577 sizeof(struct fsl_desc_sw),
578 __alignof__(struct fsl_desc_sw), 0);
579 if (!chan->desc_pool) {
580 chan_err(chan, "unable to allocate descriptor pool\n");
584 /* there is at least one descriptor free to be allocated */
589 * fsldma_free_desc_list - Free all descriptors in a queue
590 * @chan: Freescae DMA channel
591 * @list: the list to free
593 * LOCKING: must hold chan->desc_lock
595 static void fsldma_free_desc_list(struct fsldma_chan *chan,
596 struct list_head *list)
598 struct fsl_desc_sw *desc, *_desc;
600 list_for_each_entry_safe(desc, _desc, list, node)
601 fsl_dma_free_descriptor(chan, desc);
604 static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
605 struct list_head *list)
607 struct fsl_desc_sw *desc, *_desc;
609 list_for_each_entry_safe_reverse(desc, _desc, list, node)
610 fsl_dma_free_descriptor(chan, desc);
614 * fsl_dma_free_chan_resources - Free all resources of the channel.
615 * @chan : Freescale DMA channel
617 static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
619 struct fsldma_chan *chan = to_fsl_chan(dchan);
622 chan_dbg(chan, "free all channel resources\n");
623 spin_lock_irqsave(&chan->desc_lock, flags);
624 fsldma_free_desc_list(chan, &chan->ld_pending);
625 fsldma_free_desc_list(chan, &chan->ld_running);
626 spin_unlock_irqrestore(&chan->desc_lock, flags);
628 dma_pool_destroy(chan->desc_pool);
629 chan->desc_pool = NULL;
632 static struct dma_async_tx_descriptor *
633 fsl_dma_prep_memcpy(struct dma_chan *dchan,
634 dma_addr_t dma_dst, dma_addr_t dma_src,
635 size_t len, unsigned long flags)
637 struct fsldma_chan *chan;
638 struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
647 chan = to_fsl_chan(dchan);
651 /* Allocate the link descriptor from DMA pool */
652 new = fsl_dma_alloc_descriptor(chan);
654 chan_err(chan, "%s\n", msg_ld_oom);
658 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
660 set_desc_cnt(chan, &new->hw, copy);
661 set_desc_src(chan, &new->hw, dma_src);
662 set_desc_dst(chan, &new->hw, dma_dst);
667 set_desc_next(chan, &prev->hw, new->async_tx.phys);
669 new->async_tx.cookie = 0;
670 async_tx_ack(&new->async_tx);
677 /* Insert the link descriptor to the LD ring */
678 list_add_tail(&new->node, &first->tx_list);
681 new->async_tx.flags = flags; /* client is in control of this ack */
682 new->async_tx.cookie = -EBUSY;
684 /* Set End-of-link to the last link descriptor of new list */
685 set_ld_eol(chan, new);
687 return &first->async_tx;
693 fsldma_free_desc_list_reverse(chan, &first->tx_list);
697 static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan,
698 struct scatterlist *dst_sg, unsigned int dst_nents,
699 struct scatterlist *src_sg, unsigned int src_nents,
702 struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
703 struct fsldma_chan *chan = to_fsl_chan(dchan);
704 size_t dst_avail, src_avail;
708 /* basic sanity checks */
709 if (dst_nents == 0 || src_nents == 0)
712 if (dst_sg == NULL || src_sg == NULL)
716 * TODO: should we check that both scatterlists have the same
717 * TODO: number of bytes in total? Is that really an error?
720 /* get prepared for the loop */
721 dst_avail = sg_dma_len(dst_sg);
722 src_avail = sg_dma_len(src_sg);
724 /* run until we are out of scatterlist entries */
727 /* create the largest transaction possible */
728 len = min_t(size_t, src_avail, dst_avail);
729 len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT);
733 dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail;
734 src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail;
736 /* allocate and populate the descriptor */
737 new = fsl_dma_alloc_descriptor(chan);
739 chan_err(chan, "%s\n", msg_ld_oom);
743 set_desc_cnt(chan, &new->hw, len);
744 set_desc_src(chan, &new->hw, src);
745 set_desc_dst(chan, &new->hw, dst);
750 set_desc_next(chan, &prev->hw, new->async_tx.phys);
752 new->async_tx.cookie = 0;
753 async_tx_ack(&new->async_tx);
756 /* Insert the link descriptor to the LD ring */
757 list_add_tail(&new->node, &first->tx_list);
759 /* update metadata */
764 /* fetch the next dst scatterlist entry */
765 if (dst_avail == 0) {
767 /* no more entries: we're done */
771 /* fetch the next entry: if there are no more: done */
772 dst_sg = sg_next(dst_sg);
777 dst_avail = sg_dma_len(dst_sg);
780 /* fetch the next src scatterlist entry */
781 if (src_avail == 0) {
783 /* no more entries: we're done */
787 /* fetch the next entry: if there are no more: done */
788 src_sg = sg_next(src_sg);
793 src_avail = sg_dma_len(src_sg);
797 new->async_tx.flags = flags; /* client is in control of this ack */
798 new->async_tx.cookie = -EBUSY;
800 /* Set End-of-link to the last link descriptor of new list */
801 set_ld_eol(chan, new);
803 return &first->async_tx;
809 fsldma_free_desc_list_reverse(chan, &first->tx_list);
814 * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
816 * @sgl: scatterlist to transfer to/from
817 * @sg_len: number of entries in @scatterlist
818 * @direction: DMA direction
819 * @flags: DMAEngine flags
820 * @context: transaction context (ignored)
822 * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the
823 * DMA_SLAVE API, this gets the device-specific information from the
824 * chan->private variable.
826 static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
827 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
828 enum dma_transfer_direction direction, unsigned long flags,
832 * This operation is not supported on the Freescale DMA controller
834 * However, we need to provide the function pointer to allow the
835 * device_control() method to work.
840 static int fsl_dma_device_control(struct dma_chan *dchan,
841 enum dma_ctrl_cmd cmd, unsigned long arg)
843 struct dma_slave_config *config;
844 struct fsldma_chan *chan;
851 chan = to_fsl_chan(dchan);
854 case DMA_TERMINATE_ALL:
855 spin_lock_irqsave(&chan->desc_lock, flags);
857 /* Halt the DMA engine */
860 /* Remove and free all of the descriptors in the LD queue */
861 fsldma_free_desc_list(chan, &chan->ld_pending);
862 fsldma_free_desc_list(chan, &chan->ld_running);
865 spin_unlock_irqrestore(&chan->desc_lock, flags);
868 case DMA_SLAVE_CONFIG:
869 config = (struct dma_slave_config *)arg;
871 /* make sure the channel supports setting burst size */
872 if (!chan->set_request_count)
875 /* we set the controller burst size depending on direction */
876 if (config->direction == DMA_MEM_TO_DEV)
877 size = config->dst_addr_width * config->dst_maxburst;
879 size = config->src_addr_width * config->src_maxburst;
881 chan->set_request_count(chan, size);
884 case FSLDMA_EXTERNAL_START:
886 /* make sure the channel supports external start */
887 if (!chan->toggle_ext_start)
890 chan->toggle_ext_start(chan, arg);
901 * fsl_dma_memcpy_issue_pending - Issue the DMA start command
902 * @chan : Freescale DMA channel
904 static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
906 struct fsldma_chan *chan = to_fsl_chan(dchan);
909 spin_lock_irqsave(&chan->desc_lock, flags);
910 fsl_chan_xfer_ld_queue(chan);
911 spin_unlock_irqrestore(&chan->desc_lock, flags);
915 * fsl_tx_status - Determine the DMA status
916 * @chan : Freescale DMA channel
918 static enum dma_status fsl_tx_status(struct dma_chan *dchan,
920 struct dma_tx_state *txstate)
922 return dma_cookie_status(dchan, cookie, txstate);
925 /*----------------------------------------------------------------------------*/
926 /* Interrupt Handling */
927 /*----------------------------------------------------------------------------*/
929 static irqreturn_t fsldma_chan_irq(int irq, void *data)
931 struct fsldma_chan *chan = data;
934 /* save and clear the status register */
937 chan_dbg(chan, "irq: stat = 0x%x\n", stat);
939 /* check that this was really our device */
940 stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
944 if (stat & FSL_DMA_SR_TE)
945 chan_err(chan, "Transfer Error!\n");
949 * The DMA_INTERRUPT async_tx is a NULL transfer, which will
950 * trigger a PE interrupt.
952 if (stat & FSL_DMA_SR_PE) {
953 chan_dbg(chan, "irq: Programming Error INT\n");
954 stat &= ~FSL_DMA_SR_PE;
955 if (get_bcr(chan) != 0)
956 chan_err(chan, "Programming Error!\n");
960 * For MPC8349, EOCDI event need to update cookie
961 * and start the next transfer if it exist.
963 if (stat & FSL_DMA_SR_EOCDI) {
964 chan_dbg(chan, "irq: End-of-Chain link INT\n");
965 stat &= ~FSL_DMA_SR_EOCDI;
969 * If it current transfer is the end-of-transfer,
970 * we should clear the Channel Start bit for
971 * prepare next transfer.
973 if (stat & FSL_DMA_SR_EOLNI) {
974 chan_dbg(chan, "irq: End-of-link INT\n");
975 stat &= ~FSL_DMA_SR_EOLNI;
978 /* check that the DMA controller is really idle */
979 if (!dma_is_idle(chan))
980 chan_err(chan, "irq: controller not idle!\n");
982 /* check that we handled all of the bits */
984 chan_err(chan, "irq: unhandled sr 0x%08x\n", stat);
987 * Schedule the tasklet to handle all cleanup of the current
988 * transaction. It will start a new transaction if there is
991 tasklet_schedule(&chan->tasklet);
992 chan_dbg(chan, "irq: Exit\n");
996 static void dma_do_tasklet(unsigned long data)
998 struct fsldma_chan *chan = (struct fsldma_chan *)data;
999 struct fsl_desc_sw *desc, *_desc;
1000 LIST_HEAD(ld_cleanup);
1001 unsigned long flags;
1003 chan_dbg(chan, "tasklet entry\n");
1005 spin_lock_irqsave(&chan->desc_lock, flags);
1007 /* update the cookie if we have some descriptors to cleanup */
1008 if (!list_empty(&chan->ld_running)) {
1009 dma_cookie_t cookie;
1011 desc = to_fsl_desc(chan->ld_running.prev);
1012 cookie = desc->async_tx.cookie;
1013 dma_cookie_complete(&desc->async_tx);
1015 chan_dbg(chan, "completed_cookie=%d\n", cookie);
1019 * move the descriptors to a temporary list so we can drop the lock
1020 * during the entire cleanup operation
1022 list_splice_tail_init(&chan->ld_running, &ld_cleanup);
1024 /* the hardware is now idle and ready for more */
1028 * Start any pending transactions automatically
1030 * In the ideal case, we keep the DMA controller busy while we go
1031 * ahead and free the descriptors below.
1033 fsl_chan_xfer_ld_queue(chan);
1034 spin_unlock_irqrestore(&chan->desc_lock, flags);
1036 /* Run the callback for each descriptor, in order */
1037 list_for_each_entry_safe(desc, _desc, &ld_cleanup, node) {
1039 /* Remove from the list of transactions */
1040 list_del(&desc->node);
1042 /* Run all cleanup for this descriptor */
1043 fsldma_cleanup_descriptor(chan, desc);
1046 chan_dbg(chan, "tasklet exit\n");
1049 static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
1051 struct fsldma_device *fdev = data;
1052 struct fsldma_chan *chan;
1053 unsigned int handled = 0;
1057 gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs)
1058 : in_le32(fdev->regs);
1060 dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr);
1062 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1063 chan = fdev->chan[i];
1068 dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
1069 fsldma_chan_irq(irq, chan);
1077 return IRQ_RETVAL(handled);
1080 static void fsldma_free_irqs(struct fsldma_device *fdev)
1082 struct fsldma_chan *chan;
1085 if (fdev->irq != NO_IRQ) {
1086 dev_dbg(fdev->dev, "free per-controller IRQ\n");
1087 free_irq(fdev->irq, fdev);
1091 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1092 chan = fdev->chan[i];
1093 if (chan && chan->irq != NO_IRQ) {
1094 chan_dbg(chan, "free per-channel IRQ\n");
1095 free_irq(chan->irq, chan);
1100 static int fsldma_request_irqs(struct fsldma_device *fdev)
1102 struct fsldma_chan *chan;
1106 /* if we have a per-controller IRQ, use that */
1107 if (fdev->irq != NO_IRQ) {
1108 dev_dbg(fdev->dev, "request per-controller IRQ\n");
1109 ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED,
1110 "fsldma-controller", fdev);
1114 /* no per-controller IRQ, use the per-channel IRQs */
1115 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1116 chan = fdev->chan[i];
1120 if (chan->irq == NO_IRQ) {
1121 chan_err(chan, "interrupts property missing in device tree\n");
1126 chan_dbg(chan, "request per-channel IRQ\n");
1127 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
1128 "fsldma-chan", chan);
1130 chan_err(chan, "unable to request per-channel IRQ\n");
1138 for (/* none */; i >= 0; i--) {
1139 chan = fdev->chan[i];
1143 if (chan->irq == NO_IRQ)
1146 free_irq(chan->irq, chan);
1152 /*----------------------------------------------------------------------------*/
1153 /* OpenFirmware Subsystem */
1154 /*----------------------------------------------------------------------------*/
1156 static int fsl_dma_chan_probe(struct fsldma_device *fdev,
1157 struct device_node *node, u32 feature, const char *compatible)
1159 struct fsldma_chan *chan;
1160 struct resource res;
1164 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1166 dev_err(fdev->dev, "no free memory for DMA channels!\n");
1171 /* ioremap registers for use */
1172 chan->regs = of_iomap(node, 0);
1174 dev_err(fdev->dev, "unable to ioremap registers\n");
1179 err = of_address_to_resource(node, 0, &res);
1181 dev_err(fdev->dev, "unable to find 'reg' property\n");
1182 goto out_iounmap_regs;
1185 chan->feature = feature;
1187 fdev->feature = chan->feature;
1190 * If the DMA device's feature is different than the feature
1191 * of its channels, report the bug
1193 WARN_ON(fdev->feature != chan->feature);
1195 chan->dev = fdev->dev;
1196 chan->id = (res.start & 0xfff) < 0x300 ?
1197 ((res.start - 0x100) & 0xfff) >> 7 :
1198 ((res.start - 0x200) & 0xfff) >> 7;
1199 if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
1200 dev_err(fdev->dev, "too many channels for device\n");
1202 goto out_iounmap_regs;
1205 fdev->chan[chan->id] = chan;
1206 tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
1207 snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id);
1209 /* Initialize the channel */
1212 /* Clear cdar registers */
1215 switch (chan->feature & FSL_DMA_IP_MASK) {
1216 case FSL_DMA_IP_85XX:
1217 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
1218 case FSL_DMA_IP_83XX:
1219 chan->toggle_ext_start = fsl_chan_toggle_ext_start;
1220 chan->set_src_loop_size = fsl_chan_set_src_loop_size;
1221 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
1222 chan->set_request_count = fsl_chan_set_request_count;
1225 spin_lock_init(&chan->desc_lock);
1226 INIT_LIST_HEAD(&chan->ld_pending);
1227 INIT_LIST_HEAD(&chan->ld_running);
1230 chan->common.device = &fdev->common;
1231 dma_cookie_init(&chan->common);
1233 /* find the IRQ line, if it exists in the device tree */
1234 chan->irq = irq_of_parse_and_map(node, 0);
1236 /* Add the channel to DMA device channel list */
1237 list_add_tail(&chan->common.device_node, &fdev->common.channels);
1238 fdev->common.chancnt++;
1240 dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
1241 chan->irq != NO_IRQ ? chan->irq : fdev->irq);
1246 iounmap(chan->regs);
1253 static void fsl_dma_chan_remove(struct fsldma_chan *chan)
1255 irq_dispose_mapping(chan->irq);
1256 list_del(&chan->common.device_node);
1257 iounmap(chan->regs);
1261 static int fsldma_of_probe(struct platform_device *op)
1263 struct fsldma_device *fdev;
1264 struct device_node *child;
1267 fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
1269 dev_err(&op->dev, "No enough memory for 'priv'\n");
1274 fdev->dev = &op->dev;
1275 INIT_LIST_HEAD(&fdev->common.channels);
1277 /* ioremap the registers for use */
1278 fdev->regs = of_iomap(op->dev.of_node, 0);
1280 dev_err(&op->dev, "unable to ioremap registers\n");
1285 /* map the channel IRQ if it exists, but don't hookup the handler yet */
1286 fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);
1288 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
1289 dma_cap_set(DMA_SG, fdev->common.cap_mask);
1290 dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
1291 fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
1292 fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
1293 fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
1294 fdev->common.device_prep_dma_sg = fsl_dma_prep_sg;
1295 fdev->common.device_tx_status = fsl_tx_status;
1296 fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
1297 fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg;
1298 fdev->common.device_control = fsl_dma_device_control;
1299 fdev->common.dev = &op->dev;
1301 dma_set_mask(&(op->dev), DMA_BIT_MASK(36));
1303 platform_set_drvdata(op, fdev);
1306 * We cannot use of_platform_bus_probe() because there is no
1307 * of_platform_bus_remove(). Instead, we manually instantiate every DMA
1310 for_each_child_of_node(op->dev.of_node, child) {
1311 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
1312 fsl_dma_chan_probe(fdev, child,
1313 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
1314 "fsl,eloplus-dma-channel");
1317 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) {
1318 fsl_dma_chan_probe(fdev, child,
1319 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
1320 "fsl,elo-dma-channel");
1325 * Hookup the IRQ handler(s)
1327 * If we have a per-controller interrupt, we prefer that to the
1328 * per-channel interrupts to reduce the number of shared interrupt
1329 * handlers on the same IRQ line
1331 err = fsldma_request_irqs(fdev);
1333 dev_err(fdev->dev, "unable to request IRQs\n");
1337 dma_async_device_register(&fdev->common);
1341 irq_dispose_mapping(fdev->irq);
1347 static int fsldma_of_remove(struct platform_device *op)
1349 struct fsldma_device *fdev;
1352 fdev = platform_get_drvdata(op);
1353 dma_async_device_unregister(&fdev->common);
1355 fsldma_free_irqs(fdev);
1357 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1359 fsl_dma_chan_remove(fdev->chan[i]);
1362 iounmap(fdev->regs);
1368 static const struct of_device_id fsldma_of_ids[] = {
1369 { .compatible = "fsl,elo3-dma", },
1370 { .compatible = "fsl,eloplus-dma", },
1371 { .compatible = "fsl,elo-dma", },
1375 static struct platform_driver fsldma_of_driver = {
1377 .name = "fsl-elo-dma",
1378 .owner = THIS_MODULE,
1379 .of_match_table = fsldma_of_ids,
1381 .probe = fsldma_of_probe,
1382 .remove = fsldma_of_remove,
1385 /*----------------------------------------------------------------------------*/
1386 /* Module Init / Exit */
1387 /*----------------------------------------------------------------------------*/
1389 static __init int fsldma_init(void)
1391 pr_info("Freescale Elo series DMA driver\n");
1392 return platform_driver_register(&fsldma_of_driver);
1395 static void __exit fsldma_exit(void)
1397 platform_driver_unregister(&fsldma_of_driver);
1400 subsys_initcall(fsldma_init);
1401 module_exit(fsldma_exit);
1403 MODULE_DESCRIPTION("Freescale Elo series DMA driver");
1404 MODULE_LICENSE("GPL");