2 * intel_mid_dma.c - Intel Langwell DMA Drivers
4 * Copyright (C) 2008-10 Intel Corp
5 * Author: Vinod Koul <vinod.koul@intel.com>
6 * The driver design is based on dw_dmac driver
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
22 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
26 #include <linux/pci.h>
27 #include <linux/interrupt.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/intel_mid_dma.h>
31 #define MAX_CHAN 4 /*max ch across controllers*/
32 #include "intel_mid_dma_regs.h"
34 #define INTEL_MID_DMAC1_ID 0x0814
35 #define INTEL_MID_DMAC2_ID 0x0813
36 #define INTEL_MID_GP_DMAC2_ID 0x0827
37 #define INTEL_MFLD_DMAC1_ID 0x0830
38 #define LNW_PERIPHRAL_MASK_BASE 0xFFAE8008
39 #define LNW_PERIPHRAL_MASK_SIZE 0x10
40 #define LNW_PERIPHRAL_STATUS 0x0
41 #define LNW_PERIPHRAL_MASK 0x8
43 struct intel_mid_dma_probe_info {
50 #define INFO(_max_chan, _ch_base, _block_size, _pimr_mask) \
51 ((kernel_ulong_t)&(struct intel_mid_dma_probe_info) { \
52 .max_chan = (_max_chan), \
53 .ch_base = (_ch_base), \
54 .block_size = (_block_size), \
55 .pimr_mask = (_pimr_mask), \
58 /*****************************************************************************
61 * get_ch_index - convert status to channel
62 * @status: status mask
63 * @base: dma ch base value
65 * Modify the status mask and return the channel index needing
66 * attention (or -1 if neither)
68 static int get_ch_index(int *status, unsigned int base)
71 for (i = 0; i < MAX_CHAN; i++) {
72 if (*status & (1 << (i + base))) {
73 *status = *status & ~(1 << (i + base));
74 pr_debug("MDMA: index %d New status %x\n", i, *status);
82 * get_block_ts - calculates dma transaction length
83 * @len: dma transfer length
84 * @tx_width: dma transfer src width
85 * @block_size: dma controller max block size
87 * Based on src width calculate the DMA trsaction length in data items
88 * return data items or FFFF if exceeds max length for block
90 static int get_block_ts(int len, int tx_width, int block_size)
92 int byte_width = 0, block_ts = 0;
95 case DMA_SLAVE_BUSWIDTH_1_BYTE:
98 case DMA_SLAVE_BUSWIDTH_2_BYTES:
101 case DMA_SLAVE_BUSWIDTH_4_BYTES:
107 block_ts = len/byte_width;
108 if (block_ts > block_size)
113 /*****************************************************************************
114 DMAC1 interrupt Functions*/
117 * dmac1_mask_periphral_intr - mask the periphral interrupt
118 * @mid: dma device for which masking is required
120 * Masks the DMA periphral interrupt
121 * this is valid for DMAC1 family controllers only
122 * This controller should have periphral mask registers already mapped
124 static void dmac1_mask_periphral_intr(struct middma_device *mid)
128 if (mid->pimr_mask) {
129 pimr = readl(mid->mask_reg + LNW_PERIPHRAL_MASK);
130 pimr |= mid->pimr_mask;
131 writel(pimr, mid->mask_reg + LNW_PERIPHRAL_MASK);
137 * dmac1_unmask_periphral_intr - unmask the periphral interrupt
138 * @midc: dma channel for which masking is required
140 * UnMasks the DMA periphral interrupt,
141 * this is valid for DMAC1 family controllers only
142 * This controller should have periphral mask registers already mapped
144 static void dmac1_unmask_periphral_intr(struct intel_mid_dma_chan *midc)
147 struct middma_device *mid = to_middma_device(midc->chan.device);
149 if (mid->pimr_mask) {
150 pimr = readl(mid->mask_reg + LNW_PERIPHRAL_MASK);
151 pimr &= ~mid->pimr_mask;
152 writel(pimr, mid->mask_reg + LNW_PERIPHRAL_MASK);
158 * enable_dma_interrupt - enable the periphral interrupt
159 * @midc: dma channel for which enable interrupt is required
161 * Enable the DMA periphral interrupt,
162 * this is valid for DMAC1 family controllers only
163 * This controller should have periphral mask registers already mapped
165 static void enable_dma_interrupt(struct intel_mid_dma_chan *midc)
167 dmac1_unmask_periphral_intr(midc);
170 iowrite32(UNMASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_TFR);
171 iowrite32(UNMASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_ERR);
176 * disable_dma_interrupt - disable the periphral interrupt
177 * @midc: dma channel for which disable interrupt is required
179 * Disable the DMA periphral interrupt,
180 * this is valid for DMAC1 family controllers only
181 * This controller should have periphral mask registers already mapped
183 static void disable_dma_interrupt(struct intel_mid_dma_chan *midc)
185 /*Check LPE PISR, make sure fwd is disabled*/
186 iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_BLOCK);
187 iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_TFR);
188 iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_ERR);
192 /*****************************************************************************
193 DMA channel helper Functions*/
195 * mid_desc_get - get a descriptor
196 * @midc: dma channel for which descriptor is required
198 * Obtain a descriptor for the channel. Returns NULL if none are free.
199 * Once the descriptor is returned it is private until put on another
202 static struct intel_mid_dma_desc *midc_desc_get(struct intel_mid_dma_chan *midc)
204 struct intel_mid_dma_desc *desc, *_desc;
205 struct intel_mid_dma_desc *ret = NULL;
207 spin_lock_bh(&midc->lock);
208 list_for_each_entry_safe(desc, _desc, &midc->free_list, desc_node) {
209 if (async_tx_test_ack(&desc->txd)) {
210 list_del(&desc->desc_node);
215 spin_unlock_bh(&midc->lock);
220 * mid_desc_put - put a descriptor
221 * @midc: dma channel for which descriptor is required
222 * @desc: descriptor to put
224 * Return a descriptor from lwn_desc_get back to the free pool
226 static void midc_desc_put(struct intel_mid_dma_chan *midc,
227 struct intel_mid_dma_desc *desc)
230 spin_lock_bh(&midc->lock);
231 list_add_tail(&desc->desc_node, &midc->free_list);
232 spin_unlock_bh(&midc->lock);
236 * midc_dostart - begin a DMA transaction
237 * @midc: channel for which txn is to be started
238 * @first: first descriptor of series
240 * Load a transaction into the engine. This must be called with midc->lock
241 * held and bh disabled.
243 static void midc_dostart(struct intel_mid_dma_chan *midc,
244 struct intel_mid_dma_desc *first)
246 struct middma_device *mid = to_middma_device(midc->chan.device);
248 /* channel is idle */
249 if (midc->busy && test_ch_en(midc->dma_base, midc->ch_id)) {
251 pr_err("ERR_MDMA: channel is busy in start\n");
252 /* The tasklet will hopefully advance the queue... */
256 /*write registers and en*/
257 iowrite32(first->sar, midc->ch_regs + SAR);
258 iowrite32(first->dar, midc->ch_regs + DAR);
259 iowrite32(first->lli_phys, midc->ch_regs + LLP);
260 iowrite32(first->cfg_hi, midc->ch_regs + CFG_HIGH);
261 iowrite32(first->cfg_lo, midc->ch_regs + CFG_LOW);
262 iowrite32(first->ctl_lo, midc->ch_regs + CTL_LOW);
263 iowrite32(first->ctl_hi, midc->ch_regs + CTL_HIGH);
264 pr_debug("MDMA:TX SAR %x,DAR %x,CFGL %x,CFGH %x,CTLH %x, CTLL %x\n",
265 (int)first->sar, (int)first->dar, first->cfg_hi,
266 first->cfg_lo, first->ctl_hi, first->ctl_lo);
267 first->status = DMA_IN_PROGRESS;
269 iowrite32(ENABLE_CHANNEL(midc->ch_id), mid->dma_base + DMA_CHAN_EN);
273 * midc_descriptor_complete - process completed descriptor
274 * @midc: channel owning the descriptor
275 * @desc: the descriptor itself
277 * Process a completed descriptor and perform any callbacks upon
278 * the completion. The completion handling drops the lock during the
279 * callbacks but must be called with the lock held.
281 static void midc_descriptor_complete(struct intel_mid_dma_chan *midc,
282 struct intel_mid_dma_desc *desc)
284 struct dma_async_tx_descriptor *txd = &desc->txd;
285 dma_async_tx_callback callback_txd = NULL;
286 struct intel_mid_dma_lli *llitem;
287 void *param_txd = NULL;
289 midc->completed = txd->cookie;
290 callback_txd = txd->callback;
291 param_txd = txd->callback_param;
293 if (desc->lli != NULL) {
294 /*clear the DONE bit of completed LLI in memory*/
295 llitem = desc->lli + desc->current_lli;
296 llitem->ctl_hi &= CLEAR_DONE;
297 if (desc->current_lli < desc->lli_length-1)
298 (desc->current_lli)++;
300 desc->current_lli = 0;
302 spin_unlock_bh(&midc->lock);
304 pr_debug("MDMA: TXD callback set ... calling\n");
305 callback_txd(param_txd);
308 desc->status = DMA_SUCCESS;
309 if (desc->lli != NULL) {
310 pci_pool_free(desc->lli_pool, desc->lli,
312 pci_pool_destroy(desc->lli_pool);
314 list_move(&desc->desc_node, &midc->free_list);
317 spin_lock_bh(&midc->lock);
321 * midc_scan_descriptors - check the descriptors in channel
322 * mark completed when tx is completete
324 * @midc: channel to scan
326 * Walk the descriptor chain for the device and process any entries
329 static void midc_scan_descriptors(struct middma_device *mid,
330 struct intel_mid_dma_chan *midc)
332 struct intel_mid_dma_desc *desc = NULL, *_desc = NULL;
335 list_for_each_entry_safe(desc, _desc, &midc->active_list, desc_node) {
336 if (desc->status == DMA_IN_PROGRESS)
337 midc_descriptor_complete(midc, desc);
342 * midc_lli_fill_sg - Helper function to convert
343 * SG list to Linked List Items.
345 *@desc: DMA descriptor
346 *@sglist: Pointer to SG list
347 *@sglen: SG list length
348 *@flags: DMA transaction flags
350 * Walk through the SG list and convert the SG list into Linked
353 static int midc_lli_fill_sg(struct intel_mid_dma_chan *midc,
354 struct intel_mid_dma_desc *desc,
355 struct scatterlist *sglist,
359 struct intel_mid_dma_slave *mids;
360 struct scatterlist *sg;
361 dma_addr_t lli_next, sg_phy_addr;
362 struct intel_mid_dma_lli *lli_bloc_desc;
363 union intel_mid_dma_ctl_lo ctl_lo;
364 union intel_mid_dma_ctl_hi ctl_hi;
367 pr_debug("MDMA: Entered midc_lli_fill_sg\n");
368 mids = midc->mid_slave;
370 lli_bloc_desc = desc->lli;
371 lli_next = desc->lli_phys;
373 ctl_lo.ctl_lo = desc->ctl_lo;
374 ctl_hi.ctl_hi = desc->ctl_hi;
375 for_each_sg(sglist, sg, sglen, i) {
376 /*Populate CTL_LOW and LLI values*/
377 if (i != sglen - 1) {
378 lli_next = lli_next +
379 sizeof(struct intel_mid_dma_lli);
381 /*Check for circular list, otherwise terminate LLI to ZERO*/
382 if (flags & DMA_PREP_CIRCULAR_LIST) {
383 pr_debug("MDMA: LLI is configured in circular mode\n");
384 lli_next = desc->lli_phys;
387 ctl_lo.ctlx.llp_dst_en = 0;
388 ctl_lo.ctlx.llp_src_en = 0;
391 /*Populate CTL_HI values*/
392 ctl_hi.ctlx.block_ts = get_block_ts(sg->length,
394 midc->dma->block_size);
395 /*Populate SAR and DAR values*/
396 sg_phy_addr = sg_phys(sg);
397 if (desc->dirn == DMA_TO_DEVICE) {
398 lli_bloc_desc->sar = sg_phy_addr;
399 lli_bloc_desc->dar = mids->dma_slave.dst_addr;
400 } else if (desc->dirn == DMA_FROM_DEVICE) {
401 lli_bloc_desc->sar = mids->dma_slave.src_addr;
402 lli_bloc_desc->dar = sg_phy_addr;
404 /*Copy values into block descriptor in system memroy*/
405 lli_bloc_desc->llp = lli_next;
406 lli_bloc_desc->ctl_lo = ctl_lo.ctl_lo;
407 lli_bloc_desc->ctl_hi = ctl_hi.ctl_hi;
411 /*Copy very first LLI values to descriptor*/
412 desc->ctl_lo = desc->lli->ctl_lo;
413 desc->ctl_hi = desc->lli->ctl_hi;
414 desc->sar = desc->lli->sar;
415 desc->dar = desc->lli->dar;
419 /*****************************************************************************
420 DMA engine callback Functions*/
422 * intel_mid_dma_tx_submit - callback to submit DMA transaction
423 * @tx: dma engine descriptor
425 * Submit the DMA trasaction for this descriptor, start if ch idle
427 static dma_cookie_t intel_mid_dma_tx_submit(struct dma_async_tx_descriptor *tx)
429 struct intel_mid_dma_desc *desc = to_intel_mid_dma_desc(tx);
430 struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(tx->chan);
433 spin_lock_bh(&midc->lock);
434 cookie = midc->chan.cookie;
439 midc->chan.cookie = cookie;
440 desc->txd.cookie = cookie;
443 if (list_empty(&midc->active_list))
444 list_add_tail(&desc->desc_node, &midc->active_list);
446 list_add_tail(&desc->desc_node, &midc->queue);
448 midc_dostart(midc, desc);
449 spin_unlock_bh(&midc->lock);
455 * intel_mid_dma_issue_pending - callback to issue pending txn
456 * @chan: chan where pending trascation needs to be checked and submitted
458 * Call for scan to issue pending descriptors
460 static void intel_mid_dma_issue_pending(struct dma_chan *chan)
462 struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan);
464 spin_lock_bh(&midc->lock);
465 if (!list_empty(&midc->queue))
466 midc_scan_descriptors(to_middma_device(chan->device), midc);
467 spin_unlock_bh(&midc->lock);
471 * intel_mid_dma_tx_status - Return status of txn
472 * @chan: chan for where status needs to be checked
473 * @cookie: cookie for txn
474 * @txstate: DMA txn state
476 * Return status of DMA txn
478 static enum dma_status intel_mid_dma_tx_status(struct dma_chan *chan,
480 struct dma_tx_state *txstate)
482 struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan);
483 dma_cookie_t last_used;
484 dma_cookie_t last_complete;
487 last_complete = midc->completed;
488 last_used = chan->cookie;
490 ret = dma_async_is_complete(cookie, last_complete, last_used);
491 if (ret != DMA_SUCCESS) {
492 midc_scan_descriptors(to_middma_device(chan->device), midc);
494 last_complete = midc->completed;
495 last_used = chan->cookie;
497 ret = dma_async_is_complete(cookie, last_complete, last_used);
501 txstate->last = last_complete;
502 txstate->used = last_used;
503 txstate->residue = 0;
508 static int dma_slave_control(struct dma_chan *chan, unsigned long arg)
510 struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan);
511 struct dma_slave_config *slave = (struct dma_slave_config *)arg;
512 struct intel_mid_dma_slave *mid_slave;
516 pr_debug("MDMA: slave control called\n");
518 mid_slave = to_intel_mid_dma_slave(slave);
522 midc->mid_slave = mid_slave;
526 * intel_mid_dma_device_control - DMA device control
527 * @chan: chan for DMA control
529 * @arg: cmd arg value
531 * Perform DMA control command
533 static int intel_mid_dma_device_control(struct dma_chan *chan,
534 enum dma_ctrl_cmd cmd, unsigned long arg)
536 struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan);
537 struct middma_device *mid = to_middma_device(chan->device);
538 struct intel_mid_dma_desc *desc, *_desc;
539 union intel_mid_dma_cfg_lo cfg_lo;
541 if (cmd == DMA_SLAVE_CONFIG)
542 return dma_slave_control(chan, arg);
544 if (cmd != DMA_TERMINATE_ALL)
547 spin_lock_bh(&midc->lock);
548 if (midc->busy == false) {
549 spin_unlock_bh(&midc->lock);
552 /*Suspend and disable the channel*/
553 cfg_lo.cfg_lo = ioread32(midc->ch_regs + CFG_LOW);
554 cfg_lo.cfgx.ch_susp = 1;
555 iowrite32(cfg_lo.cfg_lo, midc->ch_regs + CFG_LOW);
556 iowrite32(DISABLE_CHANNEL(midc->ch_id), mid->dma_base + DMA_CHAN_EN);
558 /* Disable interrupts */
559 disable_dma_interrupt(midc);
560 midc->descs_allocated = 0;
562 spin_unlock_bh(&midc->lock);
563 list_for_each_entry_safe(desc, _desc, &midc->active_list, desc_node) {
564 if (desc->lli != NULL) {
565 pci_pool_free(desc->lli_pool, desc->lli,
567 pci_pool_destroy(desc->lli_pool);
569 list_move(&desc->desc_node, &midc->free_list);
576 * intel_mid_dma_prep_memcpy - Prep memcpy txn
577 * @chan: chan for DMA transfer
578 * @dest: destn address
580 * @len: DMA transfer len
583 * Perform a DMA memcpy. Note we support slave periphral DMA transfers only
584 * The periphral txn details should be filled in slave structure properly
585 * Returns the descriptor for this txn
587 static struct dma_async_tx_descriptor *intel_mid_dma_prep_memcpy(
588 struct dma_chan *chan, dma_addr_t dest,
589 dma_addr_t src, size_t len, unsigned long flags)
591 struct intel_mid_dma_chan *midc;
592 struct intel_mid_dma_desc *desc = NULL;
593 struct intel_mid_dma_slave *mids;
594 union intel_mid_dma_ctl_lo ctl_lo;
595 union intel_mid_dma_ctl_hi ctl_hi;
596 union intel_mid_dma_cfg_lo cfg_lo;
597 union intel_mid_dma_cfg_hi cfg_hi;
598 enum dma_slave_buswidth width;
600 pr_debug("MDMA: Prep for memcpy\n");
605 midc = to_intel_mid_dma_chan(chan);
608 mids = midc->mid_slave;
611 pr_debug("MDMA:called for DMA %x CH %d Length %zu\n",
612 midc->dma->pci_id, midc->ch_id, len);
613 pr_debug("MDMA:Cfg passed Mode %x, Dirn %x, HS %x, Width %x\n",
614 mids->cfg_mode, mids->dma_slave.direction,
615 mids->hs_mode, mids->dma_slave.src_addr_width);
618 if (mids->hs_mode == LNW_DMA_SW_HS) {
620 cfg_lo.cfgx.hs_sel_dst = 1;
621 cfg_lo.cfgx.hs_sel_src = 1;
622 } else if (mids->hs_mode == LNW_DMA_HW_HS)
623 cfg_lo.cfg_lo = 0x00000;
626 if (mids->cfg_mode == LNW_DMA_MEM_TO_MEM) {
631 if (midc->dma->pimr_mask) {
632 cfg_hi.cfgx.protctl = 0x0; /*default value*/
633 cfg_hi.cfgx.fifo_mode = 1;
634 if (mids->dma_slave.direction == DMA_TO_DEVICE) {
635 cfg_hi.cfgx.src_per = 0;
636 if (mids->device_instance == 0)
637 cfg_hi.cfgx.dst_per = 3;
638 if (mids->device_instance == 1)
639 cfg_hi.cfgx.dst_per = 1;
640 } else if (mids->dma_slave.direction == DMA_FROM_DEVICE) {
641 if (mids->device_instance == 0)
642 cfg_hi.cfgx.src_per = 2;
643 if (mids->device_instance == 1)
644 cfg_hi.cfgx.src_per = 0;
645 cfg_hi.cfgx.dst_per = 0;
648 cfg_hi.cfgx.protctl = 0x1; /*default value*/
649 cfg_hi.cfgx.src_per = cfg_hi.cfgx.dst_per =
650 midc->ch_id - midc->dma->chan_base;
655 ctl_hi.ctlx.reser = 0;
656 ctl_hi.ctlx.done = 0;
657 width = mids->dma_slave.src_addr_width;
659 ctl_hi.ctlx.block_ts = get_block_ts(len, width, midc->dma->block_size);
660 pr_debug("MDMA:calc len %d for block size %d\n",
661 ctl_hi.ctlx.block_ts, midc->dma->block_size);
664 ctl_lo.ctlx.int_en = 1;
665 ctl_lo.ctlx.dst_msize = mids->dma_slave.src_maxburst;
666 ctl_lo.ctlx.src_msize = mids->dma_slave.dst_maxburst;
669 * Here we need some translation from "enum dma_slave_buswidth"
670 * to the format for our dma controller
671 * standard intel_mid_dmac's format
676 ctl_lo.ctlx.dst_tr_width = mids->dma_slave.dst_addr_width / 2;
677 ctl_lo.ctlx.src_tr_width = mids->dma_slave.src_addr_width / 2;
679 if (mids->cfg_mode == LNW_DMA_MEM_TO_MEM) {
680 ctl_lo.ctlx.tt_fc = 0;
681 ctl_lo.ctlx.sinc = 0;
682 ctl_lo.ctlx.dinc = 0;
684 if (mids->dma_slave.direction == DMA_TO_DEVICE) {
685 ctl_lo.ctlx.sinc = 0;
686 ctl_lo.ctlx.dinc = 2;
687 ctl_lo.ctlx.tt_fc = 1;
688 } else if (mids->dma_slave.direction == DMA_FROM_DEVICE) {
689 ctl_lo.ctlx.sinc = 2;
690 ctl_lo.ctlx.dinc = 0;
691 ctl_lo.ctlx.tt_fc = 2;
695 pr_debug("MDMA:Calc CTL LO %x, CTL HI %x, CFG LO %x, CFG HI %x\n",
696 ctl_lo.ctl_lo, ctl_hi.ctl_hi, cfg_lo.cfg_lo, cfg_hi.cfg_hi);
698 enable_dma_interrupt(midc);
700 desc = midc_desc_get(midc);
706 desc->cfg_hi = cfg_hi.cfg_hi;
707 desc->cfg_lo = cfg_lo.cfg_lo;
708 desc->ctl_lo = ctl_lo.ctl_lo;
709 desc->ctl_hi = ctl_hi.ctl_hi;
711 desc->dirn = mids->dma_slave.direction;
714 desc->lli_pool = NULL;
718 pr_err("ERR_MDMA: Failed to get desc\n");
719 midc_desc_put(midc, desc);
723 * intel_mid_dma_prep_slave_sg - Prep slave sg txn
724 * @chan: chan for DMA transfer
725 * @sgl: scatter gather list
726 * @sg_len: length of sg txn
727 * @direction: DMA transfer dirtn
730 * Prepares LLI based periphral transfer
732 static struct dma_async_tx_descriptor *intel_mid_dma_prep_slave_sg(
733 struct dma_chan *chan, struct scatterlist *sgl,
734 unsigned int sg_len, enum dma_data_direction direction,
737 struct intel_mid_dma_chan *midc = NULL;
738 struct intel_mid_dma_slave *mids = NULL;
739 struct intel_mid_dma_desc *desc = NULL;
740 struct dma_async_tx_descriptor *txd = NULL;
741 union intel_mid_dma_ctl_lo ctl_lo;
743 pr_debug("MDMA: Prep for slave SG\n");
746 pr_err("MDMA: Invalid SG length\n");
749 midc = to_intel_mid_dma_chan(chan);
752 mids = midc->mid_slave;
755 if (!midc->dma->pimr_mask) {
756 /* We can still handle sg list with only one item */
758 txd = intel_mid_dma_prep_memcpy(chan,
759 mids->dma_slave.dst_addr,
760 mids->dma_slave.src_addr,
765 pr_warn("MDMA: SG list is not supported by this controller\n");
770 pr_debug("MDMA: SG Length = %d, direction = %d, Flags = %#lx\n",
771 sg_len, direction, flags);
773 txd = intel_mid_dma_prep_memcpy(chan, 0, 0, sgl->length, flags);
775 pr_err("MDMA: Prep memcpy failed\n");
779 desc = to_intel_mid_dma_desc(txd);
780 desc->dirn = direction;
781 ctl_lo.ctl_lo = desc->ctl_lo;
782 ctl_lo.ctlx.llp_dst_en = 1;
783 ctl_lo.ctlx.llp_src_en = 1;
784 desc->ctl_lo = ctl_lo.ctl_lo;
785 desc->lli_length = sg_len;
786 desc->current_lli = 0;
787 /* DMA coherent memory pool for LLI descriptors*/
788 desc->lli_pool = pci_pool_create("intel_mid_dma_lli_pool",
790 (sizeof(struct intel_mid_dma_lli)*sg_len),
792 if (NULL == desc->lli_pool) {
793 pr_err("MID_DMA:LLI pool create failed\n");
797 desc->lli = pci_pool_alloc(desc->lli_pool, GFP_KERNEL, &desc->lli_phys);
799 pr_err("MID_DMA: LLI alloc failed\n");
800 pci_pool_destroy(desc->lli_pool);
804 midc_lli_fill_sg(midc, desc, sgl, sg_len, flags);
805 if (flags & DMA_PREP_INTERRUPT) {
806 iowrite32(UNMASK_INTR_REG(midc->ch_id),
807 midc->dma_base + MASK_BLOCK);
808 pr_debug("MDMA:Enabled Block interrupt\n");
814 * intel_mid_dma_free_chan_resources - Frees dma resources
815 * @chan: chan requiring attention
817 * Frees the allocated resources on this DMA chan
819 static void intel_mid_dma_free_chan_resources(struct dma_chan *chan)
821 struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan);
822 struct middma_device *mid = to_middma_device(chan->device);
823 struct intel_mid_dma_desc *desc, *_desc;
825 if (true == midc->busy) {
826 /*trying to free ch in use!!!!!*/
827 pr_err("ERR_MDMA: trying to free ch in use\n");
829 pm_runtime_put(&mid->pdev->dev);
830 spin_lock_bh(&midc->lock);
831 midc->descs_allocated = 0;
832 list_for_each_entry_safe(desc, _desc, &midc->active_list, desc_node) {
833 list_del(&desc->desc_node);
834 pci_pool_free(mid->dma_pool, desc, desc->txd.phys);
836 list_for_each_entry_safe(desc, _desc, &midc->free_list, desc_node) {
837 list_del(&desc->desc_node);
838 pci_pool_free(mid->dma_pool, desc, desc->txd.phys);
840 list_for_each_entry_safe(desc, _desc, &midc->queue, desc_node) {
841 list_del(&desc->desc_node);
842 pci_pool_free(mid->dma_pool, desc, desc->txd.phys);
844 spin_unlock_bh(&midc->lock);
845 midc->in_use = false;
847 /* Disable CH interrupts */
848 iowrite32(MASK_INTR_REG(midc->ch_id), mid->dma_base + MASK_BLOCK);
849 iowrite32(MASK_INTR_REG(midc->ch_id), mid->dma_base + MASK_ERR);
853 * intel_mid_dma_alloc_chan_resources - Allocate dma resources
854 * @chan: chan requiring attention
856 * Allocates DMA resources on this chan
857 * Return the descriptors allocated
859 static int intel_mid_dma_alloc_chan_resources(struct dma_chan *chan)
861 struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan);
862 struct middma_device *mid = to_middma_device(chan->device);
863 struct intel_mid_dma_desc *desc;
867 pm_runtime_get_sync(&mid->pdev->dev);
869 if (mid->state == SUSPENDED) {
870 if (dma_resume(mid->pdev)) {
871 pr_err("ERR_MDMA: resume failed");
876 /* ASSERT: channel is idle */
877 if (test_ch_en(mid->dma_base, midc->ch_id)) {
879 pr_err("ERR_MDMA: ch not idle\n");
880 pm_runtime_put(&mid->pdev->dev);
883 midc->completed = chan->cookie = 1;
885 spin_lock_bh(&midc->lock);
886 while (midc->descs_allocated < DESCS_PER_CHANNEL) {
887 spin_unlock_bh(&midc->lock);
888 desc = pci_pool_alloc(mid->dma_pool, GFP_KERNEL, &phys);
890 pr_err("ERR_MDMA: desc failed\n");
891 pm_runtime_put(&mid->pdev->dev);
895 dma_async_tx_descriptor_init(&desc->txd, chan);
896 desc->txd.tx_submit = intel_mid_dma_tx_submit;
897 desc->txd.flags = DMA_CTRL_ACK;
898 desc->txd.phys = phys;
899 spin_lock_bh(&midc->lock);
900 i = ++midc->descs_allocated;
901 list_add_tail(&desc->desc_node, &midc->free_list);
903 spin_unlock_bh(&midc->lock);
906 pr_debug("MID_DMA: Desc alloc done ret: %d desc\n", i);
911 * midc_handle_error - Handle DMA txn error
912 * @mid: controller where error occurred
913 * @midc: chan where error occurred
915 * Scan the descriptor for error
917 static void midc_handle_error(struct middma_device *mid,
918 struct intel_mid_dma_chan *midc)
920 midc_scan_descriptors(mid, midc);
924 * dma_tasklet - DMA interrupt tasklet
925 * @data: tasklet arg (the controller structure)
927 * Scan the controller for interrupts for completion/error
928 * Clear the interrupt and call for handling completion/error
930 static void dma_tasklet(unsigned long data)
932 struct middma_device *mid = NULL;
933 struct intel_mid_dma_chan *midc = NULL;
934 u32 status, raw_tfr, raw_block;
937 mid = (struct middma_device *)data;
939 pr_err("ERR_MDMA: tasklet Null param\n");
942 pr_debug("MDMA: in tasklet for device %x\n", mid->pci_id);
943 raw_tfr = ioread32(mid->dma_base + RAW_TFR);
944 raw_block = ioread32(mid->dma_base + RAW_BLOCK);
945 status = raw_tfr | raw_block;
946 status &= mid->intr_mask;
949 i = get_ch_index(&status, mid->chan_base);
951 pr_err("ERR_MDMA:Invalid ch index %x\n", i);
956 pr_err("ERR_MDMA:Null param midc\n");
959 pr_debug("MDMA:Tx complete interrupt %x, Ch No %d Index %d\n",
960 status, midc->ch_id, i);
961 midc->raw_tfr = raw_tfr;
962 midc->raw_block = raw_block;
963 spin_lock_bh(&midc->lock);
964 /*clearing this interrupts first*/
965 iowrite32((1 << midc->ch_id), mid->dma_base + CLEAR_TFR);
967 iowrite32((1 << midc->ch_id),
968 mid->dma_base + CLEAR_BLOCK);
970 midc_scan_descriptors(mid, midc);
971 pr_debug("MDMA:Scan of desc... complete, unmasking\n");
972 iowrite32(UNMASK_INTR_REG(midc->ch_id),
973 mid->dma_base + MASK_TFR);
975 iowrite32(UNMASK_INTR_REG(midc->ch_id),
976 mid->dma_base + MASK_BLOCK);
978 spin_unlock_bh(&midc->lock);
981 status = ioread32(mid->dma_base + RAW_ERR);
982 status &= mid->intr_mask;
985 i = get_ch_index(&status, mid->chan_base);
987 pr_err("ERR_MDMA:Invalid ch index %x\n", i);
992 pr_err("ERR_MDMA:Null param midc\n");
995 pr_debug("MDMA:Tx complete interrupt %x, Ch No %d Index %d\n",
996 status, midc->ch_id, i);
998 iowrite32((1 << midc->ch_id), mid->dma_base + CLEAR_ERR);
999 spin_lock_bh(&midc->lock);
1000 midc_handle_error(mid, midc);
1001 iowrite32(UNMASK_INTR_REG(midc->ch_id),
1002 mid->dma_base + MASK_ERR);
1003 spin_unlock_bh(&midc->lock);
1005 pr_debug("MDMA:Exiting takslet...\n");
1009 static void dma_tasklet1(unsigned long data)
1011 pr_debug("MDMA:in takslet1...\n");
1012 return dma_tasklet(data);
1015 static void dma_tasklet2(unsigned long data)
1017 pr_debug("MDMA:in takslet2...\n");
1018 return dma_tasklet(data);
1022 * intel_mid_dma_interrupt - DMA ISR
1023 * @irq: IRQ where interrupt occurred
1024 * @data: ISR cllback data (the controller structure)
1026 * See if this is our interrupt if so then schedule the tasklet
1029 static irqreturn_t intel_mid_dma_interrupt(int irq, void *data)
1031 struct middma_device *mid = data;
1032 u32 tfr_status, err_status;
1033 int call_tasklet = 0;
1035 tfr_status = ioread32(mid->dma_base + RAW_TFR);
1036 err_status = ioread32(mid->dma_base + RAW_ERR);
1037 if (!tfr_status && !err_status)
1041 pr_debug("MDMA:Got an interrupt on irq %d\n", irq);
1042 pr_debug("MDMA: Status %x, Mask %x\n", tfr_status, mid->intr_mask);
1043 tfr_status &= mid->intr_mask;
1045 /*need to disable intr*/
1046 iowrite32((tfr_status << INT_MASK_WE), mid->dma_base + MASK_TFR);
1047 iowrite32((tfr_status << INT_MASK_WE), mid->dma_base + MASK_BLOCK);
1048 pr_debug("MDMA: Calling tasklet %x\n", tfr_status);
1051 err_status &= mid->intr_mask;
1053 iowrite32(MASK_INTR_REG(err_status), mid->dma_base + MASK_ERR);
1057 tasklet_schedule(&mid->tasklet);
1062 static irqreturn_t intel_mid_dma_interrupt1(int irq, void *data)
1064 return intel_mid_dma_interrupt(irq, data);
1067 static irqreturn_t intel_mid_dma_interrupt2(int irq, void *data)
1069 return intel_mid_dma_interrupt(irq, data);
1073 * mid_setup_dma - Setup the DMA controller
1074 * @pdev: Controller PCI device structure
1076 * Initialize the DMA controller, channels, registers with DMA engine,
1077 * ISR. Initialize DMA controller channels.
1079 static int mid_setup_dma(struct pci_dev *pdev)
1081 struct middma_device *dma = pci_get_drvdata(pdev);
1084 /* DMA coherent memory pool for DMA descriptor allocations */
1085 dma->dma_pool = pci_pool_create("intel_mid_dma_desc_pool", pdev,
1086 sizeof(struct intel_mid_dma_desc),
1088 if (NULL == dma->dma_pool) {
1089 pr_err("ERR_MDMA:pci_pool_create failed\n");
1094 INIT_LIST_HEAD(&dma->common.channels);
1095 dma->pci_id = pdev->device;
1096 if (dma->pimr_mask) {
1097 dma->mask_reg = ioremap(LNW_PERIPHRAL_MASK_BASE,
1098 LNW_PERIPHRAL_MASK_SIZE);
1099 if (dma->mask_reg == NULL) {
1100 pr_err("ERR_MDMA:Can't map periphral intr space !!\n");
1104 dma->mask_reg = NULL;
1106 pr_debug("MDMA:Adding %d channel for this controller\n", dma->max_chan);
1107 /*init CH structures*/
1109 dma->state = RUNNING;
1110 for (i = 0; i < dma->max_chan; i++) {
1111 struct intel_mid_dma_chan *midch = &dma->ch[i];
1113 midch->chan.device = &dma->common;
1114 midch->chan.cookie = 1;
1115 midch->ch_id = dma->chan_base + i;
1116 pr_debug("MDMA:Init CH %d, ID %d\n", i, midch->ch_id);
1118 midch->dma_base = dma->dma_base;
1119 midch->ch_regs = dma->dma_base + DMA_CH_SIZE * midch->ch_id;
1121 dma->intr_mask |= 1 << (dma->chan_base + i);
1122 spin_lock_init(&midch->lock);
1124 INIT_LIST_HEAD(&midch->active_list);
1125 INIT_LIST_HEAD(&midch->queue);
1126 INIT_LIST_HEAD(&midch->free_list);
1128 iowrite32(MASK_INTR_REG(midch->ch_id),
1129 dma->dma_base + MASK_BLOCK);
1130 iowrite32(MASK_INTR_REG(midch->ch_id),
1131 dma->dma_base + MASK_SRC_TRAN);
1132 iowrite32(MASK_INTR_REG(midch->ch_id),
1133 dma->dma_base + MASK_DST_TRAN);
1134 iowrite32(MASK_INTR_REG(midch->ch_id),
1135 dma->dma_base + MASK_ERR);
1136 iowrite32(MASK_INTR_REG(midch->ch_id),
1137 dma->dma_base + MASK_TFR);
1139 disable_dma_interrupt(midch);
1140 list_add_tail(&midch->chan.device_node, &dma->common.channels);
1142 pr_debug("MDMA: Calc Mask as %x for this controller\n", dma->intr_mask);
1144 /*init dma structure*/
1145 dma_cap_zero(dma->common.cap_mask);
1146 dma_cap_set(DMA_MEMCPY, dma->common.cap_mask);
1147 dma_cap_set(DMA_SLAVE, dma->common.cap_mask);
1148 dma_cap_set(DMA_PRIVATE, dma->common.cap_mask);
1149 dma->common.dev = &pdev->dev;
1151 dma->common.device_alloc_chan_resources =
1152 intel_mid_dma_alloc_chan_resources;
1153 dma->common.device_free_chan_resources =
1154 intel_mid_dma_free_chan_resources;
1156 dma->common.device_tx_status = intel_mid_dma_tx_status;
1157 dma->common.device_prep_dma_memcpy = intel_mid_dma_prep_memcpy;
1158 dma->common.device_issue_pending = intel_mid_dma_issue_pending;
1159 dma->common.device_prep_slave_sg = intel_mid_dma_prep_slave_sg;
1160 dma->common.device_control = intel_mid_dma_device_control;
1162 /*enable dma cntrl*/
1163 iowrite32(REG_BIT0, dma->dma_base + DMA_CFG);
1166 if (dma->pimr_mask) {
1167 pr_debug("MDMA:Requesting irq shared for DMAC1\n");
1168 err = request_irq(pdev->irq, intel_mid_dma_interrupt1,
1169 IRQF_SHARED, "INTEL_MID_DMAC1", dma);
1173 dma->intr_mask = 0x03;
1174 pr_debug("MDMA:Requesting irq for DMAC2\n");
1175 err = request_irq(pdev->irq, intel_mid_dma_interrupt2,
1176 IRQF_SHARED, "INTEL_MID_DMAC2", dma);
1180 /*register device w/ engine*/
1181 err = dma_async_device_register(&dma->common);
1183 pr_err("ERR_MDMA:device_register failed: %d\n", err);
1186 if (dma->pimr_mask) {
1187 pr_debug("setting up tasklet1 for DMAC1\n");
1188 tasklet_init(&dma->tasklet, dma_tasklet1, (unsigned long)dma);
1190 pr_debug("setting up tasklet2 for DMAC2\n");
1191 tasklet_init(&dma->tasklet, dma_tasklet2, (unsigned long)dma);
1196 free_irq(pdev->irq, dma);
1198 pci_pool_destroy(dma->dma_pool);
1200 pr_err("ERR_MDMA:setup_dma failed: %d\n", err);
1206 * middma_shutdown - Shutdown the DMA controller
1207 * @pdev: Controller PCI device structure
1210 * Unregister DMa controller, clear all structures and free interrupt
1212 static void middma_shutdown(struct pci_dev *pdev)
1214 struct middma_device *device = pci_get_drvdata(pdev);
1216 dma_async_device_unregister(&device->common);
1217 pci_pool_destroy(device->dma_pool);
1218 if (device->mask_reg)
1219 iounmap(device->mask_reg);
1220 if (device->dma_base)
1221 iounmap(device->dma_base);
1222 free_irq(pdev->irq, device);
1227 * intel_mid_dma_probe - PCI Probe
1228 * @pdev: Controller PCI device structure
1229 * @id: pci device id structure
1231 * Initialize the PCI device, map BARs, query driver data.
1232 * Call setup_dma to complete contoller and chan initilzation
1234 static int __devinit intel_mid_dma_probe(struct pci_dev *pdev,
1235 const struct pci_device_id *id)
1237 struct middma_device *device;
1238 u32 base_addr, bar_size;
1239 struct intel_mid_dma_probe_info *info;
1242 pr_debug("MDMA: probe for %x\n", pdev->device);
1243 info = (void *)id->driver_data;
1244 pr_debug("MDMA: CH %d, base %d, block len %d, Periphral mask %x\n",
1245 info->max_chan, info->ch_base,
1246 info->block_size, info->pimr_mask);
1248 err = pci_enable_device(pdev);
1250 goto err_enable_device;
1252 err = pci_request_regions(pdev, "intel_mid_dmac");
1254 goto err_request_regions;
1256 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1258 goto err_set_dma_mask;
1260 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1262 goto err_set_dma_mask;
1264 device = kzalloc(sizeof(*device), GFP_KERNEL);
1266 pr_err("ERR_MDMA:kzalloc failed probe\n");
1270 device->pdev = pci_dev_get(pdev);
1272 base_addr = pci_resource_start(pdev, 0);
1273 bar_size = pci_resource_len(pdev, 0);
1274 device->dma_base = ioremap_nocache(base_addr, DMA_REG_SIZE);
1275 if (!device->dma_base) {
1276 pr_err("ERR_MDMA:ioremap failed\n");
1280 pci_set_drvdata(pdev, device);
1281 pci_set_master(pdev);
1282 device->max_chan = info->max_chan;
1283 device->chan_base = info->ch_base;
1284 device->block_size = info->block_size;
1285 device->pimr_mask = info->pimr_mask;
1287 err = mid_setup_dma(pdev);
1291 pm_runtime_put_noidle(&pdev->dev);
1292 pm_runtime_allow(&pdev->dev);
1296 iounmap(device->dma_base);
1302 pci_release_regions(pdev);
1303 pci_disable_device(pdev);
1304 err_request_regions:
1306 pr_err("ERR_MDMA:Probe failed %d\n", err);
1311 * intel_mid_dma_remove - PCI remove
1312 * @pdev: Controller PCI device structure
1314 * Free up all resources and data
1315 * Call shutdown_dma to complete contoller and chan cleanup
1317 static void __devexit intel_mid_dma_remove(struct pci_dev *pdev)
1319 struct middma_device *device = pci_get_drvdata(pdev);
1321 pm_runtime_get_noresume(&pdev->dev);
1322 pm_runtime_forbid(&pdev->dev);
1323 middma_shutdown(pdev);
1326 pci_release_regions(pdev);
1327 pci_disable_device(pdev);
1330 /* Power Management */
1332 * dma_suspend - PCI suspend function
1334 * @pci: PCI device structure
1335 * @state: PM message
1337 * This function is called by OS when a power event occurs
1339 int dma_suspend(struct pci_dev *pci, pm_message_t state)
1342 struct middma_device *device = pci_get_drvdata(pci);
1343 pr_debug("MDMA: dma_suspend called\n");
1345 for (i = 0; i < device->max_chan; i++) {
1346 if (device->ch[i].in_use)
1349 dmac1_mask_periphral_intr(device);
1350 device->state = SUSPENDED;
1351 pci_save_state(pci);
1352 pci_disable_device(pci);
1353 pci_set_power_state(pci, PCI_D3hot);
1358 * dma_resume - PCI resume function
1360 * @pci: PCI device structure
1362 * This function is called by OS when a power event occurs
1364 int dma_resume(struct pci_dev *pci)
1367 struct middma_device *device = pci_get_drvdata(pci);
1369 pr_debug("MDMA: dma_resume called\n");
1370 pci_set_power_state(pci, PCI_D0);
1371 pci_restore_state(pci);
1372 ret = pci_enable_device(pci);
1374 pr_err("MDMA: device can't be enabled for %x\n", pci->device);
1377 device->state = RUNNING;
1378 iowrite32(REG_BIT0, device->dma_base + DMA_CFG);
1382 static int dma_runtime_suspend(struct device *dev)
1384 struct pci_dev *pci_dev = to_pci_dev(dev);
1385 struct middma_device *device = pci_get_drvdata(pci_dev);
1387 device->state = SUSPENDED;
1391 static int dma_runtime_resume(struct device *dev)
1393 struct pci_dev *pci_dev = to_pci_dev(dev);
1394 struct middma_device *device = pci_get_drvdata(pci_dev);
1396 device->state = RUNNING;
1397 iowrite32(REG_BIT0, device->dma_base + DMA_CFG);
1401 static int dma_runtime_idle(struct device *dev)
1403 struct pci_dev *pdev = to_pci_dev(dev);
1404 struct middma_device *device = pci_get_drvdata(pdev);
1407 for (i = 0; i < device->max_chan; i++) {
1408 if (device->ch[i].in_use)
1412 return pm_schedule_suspend(dev, 0);
1415 /******************************************************************************
1418 static struct pci_device_id intel_mid_dma_ids[] = {
1419 { PCI_VDEVICE(INTEL, INTEL_MID_DMAC1_ID), INFO(2, 6, 4095, 0x200020)},
1420 { PCI_VDEVICE(INTEL, INTEL_MID_DMAC2_ID), INFO(2, 0, 2047, 0)},
1421 { PCI_VDEVICE(INTEL, INTEL_MID_GP_DMAC2_ID), INFO(2, 0, 2047, 0)},
1422 { PCI_VDEVICE(INTEL, INTEL_MFLD_DMAC1_ID), INFO(4, 0, 4095, 0x400040)},
1425 MODULE_DEVICE_TABLE(pci, intel_mid_dma_ids);
1427 static const struct dev_pm_ops intel_mid_dma_pm = {
1428 .runtime_suspend = dma_runtime_suspend,
1429 .runtime_resume = dma_runtime_resume,
1430 .runtime_idle = dma_runtime_idle,
1433 static struct pci_driver intel_mid_dma_pci_driver = {
1434 .name = "Intel MID DMA",
1435 .id_table = intel_mid_dma_ids,
1436 .probe = intel_mid_dma_probe,
1437 .remove = __devexit_p(intel_mid_dma_remove),
1439 .suspend = dma_suspend,
1440 .resume = dma_resume,
1442 .pm = &intel_mid_dma_pm,
1447 static int __init intel_mid_dma_init(void)
1449 pr_debug("INFO_MDMA: LNW DMA Driver Version %s\n",
1450 INTEL_MID_DMA_DRIVER_VERSION);
1451 return pci_register_driver(&intel_mid_dma_pci_driver);
1453 fs_initcall(intel_mid_dma_init);
1455 static void __exit intel_mid_dma_exit(void)
1457 pci_unregister_driver(&intel_mid_dma_pci_driver);
1459 module_exit(intel_mid_dma_exit);
1461 MODULE_AUTHOR("Vinod Koul <vinod.koul@intel.com>");
1462 MODULE_DESCRIPTION("Intel (R) MID DMAC Driver");
1463 MODULE_LICENSE("GPL v2");
1464 MODULE_VERSION(INTEL_MID_DMA_DRIVER_VERSION);