2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
7 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 * The full GNU General Public License is included in this distribution in
23 * the file called "COPYING".
27 * Copyright(c) 2004-2009 Intel Corporation. All rights reserved.
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions are met:
32 * * Redistributions of source code must retain the above copyright
33 * notice, this list of conditions and the following disclaimer.
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35 * notice, this list of conditions and the following disclaimer in
36 * the documentation and/or other materials provided with the
38 * * Neither the name of Intel Corporation nor the names of its
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40 * from this software without specific prior written permission.
42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
43 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
45 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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47 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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49 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
50 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
51 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
52 * POSSIBILITY OF SUCH DAMAGE.
56 * Support routines for v3+ hardware
59 #include <linux/pci.h>
60 #include <linux/dmaengine.h>
61 #include <linux/dma-mapping.h>
62 #include "registers.h"
67 /* ioat hardware assumes at least two sources for raid operations */
68 #define src_cnt_to_sw(x) ((x) + 2)
69 #define src_cnt_to_hw(x) ((x) - 2)
71 /* provide a lookup table for setting the source address in the base or
72 * extended descriptor of an xor or pq descriptor
74 static const u8 xor_idx_to_desc __read_mostly = 0xd0;
75 static const u8 xor_idx_to_field[] __read_mostly = { 1, 4, 5, 6, 7, 0, 1, 2 };
76 static const u8 pq_idx_to_desc __read_mostly = 0xf8;
77 static const u8 pq_idx_to_field[] __read_mostly = { 1, 4, 5, 0, 1, 2, 4, 5 };
79 static dma_addr_t xor_get_src(struct ioat_raw_descriptor *descs[2], int idx)
81 struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1];
83 return raw->field[xor_idx_to_field[idx]];
86 static void xor_set_src(struct ioat_raw_descriptor *descs[2],
87 dma_addr_t addr, u32 offset, int idx)
89 struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1];
91 raw->field[xor_idx_to_field[idx]] = addr + offset;
94 static dma_addr_t pq_get_src(struct ioat_raw_descriptor *descs[2], int idx)
96 struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1];
98 return raw->field[pq_idx_to_field[idx]];
101 static void pq_set_src(struct ioat_raw_descriptor *descs[2],
102 dma_addr_t addr, u32 offset, u8 coef, int idx)
104 struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *) descs[0];
105 struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1];
107 raw->field[pq_idx_to_field[idx]] = addr + offset;
108 pq->coef[idx] = coef;
111 static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat,
112 struct ioat_ring_ent *desc, int idx)
114 struct ioat_chan_common *chan = &ioat->base;
115 struct pci_dev *pdev = chan->device->pdev;
116 size_t len = desc->len;
117 size_t offset = len - desc->hw->size;
118 struct dma_async_tx_descriptor *tx = &desc->txd;
119 enum dma_ctrl_flags flags = tx->flags;
121 switch (desc->hw->ctl_f.op) {
123 if (!desc->hw->ctl_f.null) /* skip 'interrupt' ops */
124 ioat_dma_unmap(chan, flags, len, desc->hw);
127 struct ioat_fill_descriptor *hw = desc->fill;
129 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP))
130 ioat_unmap(pdev, hw->dst_addr - offset, len,
131 PCI_DMA_FROMDEVICE, flags, 1);
134 case IOAT_OP_XOR_VAL:
136 struct ioat_xor_descriptor *xor = desc->xor;
137 struct ioat_ring_ent *ext;
138 struct ioat_xor_ext_descriptor *xor_ex = NULL;
139 int src_cnt = src_cnt_to_sw(xor->ctl_f.src_cnt);
140 struct ioat_raw_descriptor *descs[2];
144 ext = ioat2_get_ring_ent(ioat, idx + 1);
145 xor_ex = ext->xor_ex;
148 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
149 descs[0] = (struct ioat_raw_descriptor *) xor;
150 descs[1] = (struct ioat_raw_descriptor *) xor_ex;
151 for (i = 0; i < src_cnt; i++) {
152 dma_addr_t src = xor_get_src(descs, i);
154 ioat_unmap(pdev, src - offset, len,
155 PCI_DMA_TODEVICE, flags, 0);
158 /* dest is a source in xor validate operations */
159 if (xor->ctl_f.op == IOAT_OP_XOR_VAL) {
160 ioat_unmap(pdev, xor->dst_addr - offset, len,
161 PCI_DMA_TODEVICE, flags, 1);
166 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP))
167 ioat_unmap(pdev, xor->dst_addr - offset, len,
168 PCI_DMA_FROMDEVICE, flags, 1);
173 struct ioat_pq_descriptor *pq = desc->pq;
174 struct ioat_ring_ent *ext;
175 struct ioat_pq_ext_descriptor *pq_ex = NULL;
176 int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt);
177 struct ioat_raw_descriptor *descs[2];
181 ext = ioat2_get_ring_ent(ioat, idx + 1);
185 /* in the 'continue' case don't unmap the dests as sources */
186 if (dmaf_p_disabled_continue(flags))
188 else if (dmaf_continue(flags))
191 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
192 descs[0] = (struct ioat_raw_descriptor *) pq;
193 descs[1] = (struct ioat_raw_descriptor *) pq_ex;
194 for (i = 0; i < src_cnt; i++) {
195 dma_addr_t src = pq_get_src(descs, i);
197 ioat_unmap(pdev, src - offset, len,
198 PCI_DMA_TODEVICE, flags, 0);
201 /* the dests are sources in pq validate operations */
202 if (pq->ctl_f.op == IOAT_OP_XOR_VAL) {
203 if (!(flags & DMA_PREP_PQ_DISABLE_P))
204 ioat_unmap(pdev, pq->p_addr - offset,
205 len, PCI_DMA_TODEVICE, flags, 0);
206 if (!(flags & DMA_PREP_PQ_DISABLE_Q))
207 ioat_unmap(pdev, pq->q_addr - offset,
208 len, PCI_DMA_TODEVICE, flags, 0);
213 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
214 if (!(flags & DMA_PREP_PQ_DISABLE_P))
215 ioat_unmap(pdev, pq->p_addr - offset, len,
216 PCI_DMA_BIDIRECTIONAL, flags, 1);
217 if (!(flags & DMA_PREP_PQ_DISABLE_Q))
218 ioat_unmap(pdev, pq->q_addr - offset, len,
219 PCI_DMA_BIDIRECTIONAL, flags, 1);
224 dev_err(&pdev->dev, "%s: unknown op type: %#x\n",
225 __func__, desc->hw->ctl_f.op);
229 static bool desc_has_ext(struct ioat_ring_ent *desc)
231 struct ioat_dma_descriptor *hw = desc->hw;
233 if (hw->ctl_f.op == IOAT_OP_XOR ||
234 hw->ctl_f.op == IOAT_OP_XOR_VAL) {
235 struct ioat_xor_descriptor *xor = desc->xor;
237 if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5)
239 } else if (hw->ctl_f.op == IOAT_OP_PQ ||
240 hw->ctl_f.op == IOAT_OP_PQ_VAL) {
241 struct ioat_pq_descriptor *pq = desc->pq;
243 if (src_cnt_to_sw(pq->ctl_f.src_cnt) > 3)
251 * __cleanup - reclaim used descriptors
252 * @ioat: channel (ring) to clean
254 * The difference from the dma_v2.c __cleanup() is that this routine
255 * handles extended descriptors and dma-unmapping raid operations.
257 static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
259 struct ioat_chan_common *chan = &ioat->base;
260 struct ioat_ring_ent *desc;
261 bool seen_current = false;
265 dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n",
266 __func__, ioat->head, ioat->tail, ioat->issued);
268 active = ioat2_ring_active(ioat);
269 for (i = 0; i < active && !seen_current; i++) {
270 struct dma_async_tx_descriptor *tx;
272 prefetch(ioat2_get_ring_ent(ioat, ioat->tail + i + 1));
273 desc = ioat2_get_ring_ent(ioat, ioat->tail + i);
274 dump_desc_dbg(ioat, desc);
277 chan->completed_cookie = tx->cookie;
278 ioat3_dma_unmap(ioat, desc, ioat->tail + i);
281 tx->callback(tx->callback_param);
286 if (tx->phys == phys_complete)
289 /* skip extended descriptors */
290 if (desc_has_ext(desc)) {
291 BUG_ON(i + 1 >= active);
296 BUG_ON(!seen_current); /* no active descs have written a completion? */
297 chan->last_completion = phys_complete;
298 if (ioat->head == ioat->tail) {
299 dev_dbg(to_dev(chan), "%s: cancel completion timeout\n",
301 clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
302 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
306 static void ioat3_cleanup(struct ioat2_dma_chan *ioat)
308 struct ioat_chan_common *chan = &ioat->base;
309 unsigned long phys_complete;
311 prefetch(chan->completion);
313 if (!spin_trylock_bh(&chan->cleanup_lock))
316 if (!ioat_cleanup_preamble(chan, &phys_complete)) {
317 spin_unlock_bh(&chan->cleanup_lock);
321 if (!spin_trylock_bh(&ioat->ring_lock)) {
322 spin_unlock_bh(&chan->cleanup_lock);
326 __cleanup(ioat, phys_complete);
328 spin_unlock_bh(&ioat->ring_lock);
329 spin_unlock_bh(&chan->cleanup_lock);
332 static void ioat3_cleanup_tasklet(unsigned long data)
334 struct ioat2_dma_chan *ioat = (void *) data;
337 writew(IOAT_CHANCTRL_RUN | IOAT3_CHANCTRL_COMPL_DCA_EN,
338 ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
341 static void ioat3_restart_channel(struct ioat2_dma_chan *ioat)
343 struct ioat_chan_common *chan = &ioat->base;
344 unsigned long phys_complete;
347 status = ioat_chansts(chan);
348 if (is_ioat_active(status) || is_ioat_idle(status))
350 while (is_ioat_active(status) || is_ioat_idle(status)) {
351 status = ioat_chansts(chan);
355 if (ioat_cleanup_preamble(chan, &phys_complete))
356 __cleanup(ioat, phys_complete);
358 __ioat2_restart_chan(ioat);
361 static void ioat3_timer_event(unsigned long data)
363 struct ioat2_dma_chan *ioat = (void *) data;
364 struct ioat_chan_common *chan = &ioat->base;
366 spin_lock_bh(&chan->cleanup_lock);
367 if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
368 unsigned long phys_complete;
371 spin_lock_bh(&ioat->ring_lock);
372 status = ioat_chansts(chan);
374 /* when halted due to errors check for channel
375 * programming errors before advancing the completion state
377 if (is_ioat_halted(status)) {
380 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
381 dev_err(to_dev(chan), "%s: Channel halted (%x)\n",
383 BUG_ON(is_ioat_bug(chanerr));
386 /* if we haven't made progress and we have already
387 * acknowledged a pending completion once, then be more
388 * forceful with a restart
390 if (ioat_cleanup_preamble(chan, &phys_complete))
391 __cleanup(ioat, phys_complete);
392 else if (test_bit(IOAT_COMPLETION_ACK, &chan->state))
393 ioat3_restart_channel(ioat);
395 set_bit(IOAT_COMPLETION_ACK, &chan->state);
396 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
398 spin_unlock_bh(&ioat->ring_lock);
402 /* if the ring is idle, empty, and oversized try to step
405 spin_lock_bh(&ioat->ring_lock);
406 active = ioat2_ring_active(ioat);
407 if (active == 0 && ioat->alloc_order > ioat_get_alloc_order())
408 reshape_ring(ioat, ioat->alloc_order-1);
409 spin_unlock_bh(&ioat->ring_lock);
411 /* keep shrinking until we get back to our minimum
414 if (ioat->alloc_order > ioat_get_alloc_order())
415 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
417 spin_unlock_bh(&chan->cleanup_lock);
420 static enum dma_status
421 ioat3_is_complete(struct dma_chan *c, dma_cookie_t cookie,
422 dma_cookie_t *done, dma_cookie_t *used)
424 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
426 if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS)
431 return ioat_is_complete(c, cookie, done, used);
434 static struct dma_async_tx_descriptor *
435 ioat3_prep_memset_lock(struct dma_chan *c, dma_addr_t dest, int value,
436 size_t len, unsigned long flags)
438 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
439 struct ioat_ring_ent *desc;
440 size_t total_len = len;
441 struct ioat_fill_descriptor *fill;
443 u64 src_data = (0x0101010101010101ULL) * (value & 0xff);
447 num_descs = ioat2_xferlen_to_descs(ioat, len);
448 if (likely(num_descs) &&
449 ioat2_alloc_and_lock(&idx, ioat, num_descs) == 0)
455 size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log);
457 desc = ioat2_get_ring_ent(ioat, idx + i);
460 fill->size = xfer_size;
461 fill->src_data = src_data;
462 fill->dst_addr = dest;
464 fill->ctl_f.op = IOAT_OP_FILL;
468 dump_desc_dbg(ioat, desc);
469 } while (++i < num_descs);
471 desc->txd.flags = flags;
472 desc->len = total_len;
473 fill->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
474 fill->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
475 fill->ctl_f.compl_write = 1;
476 dump_desc_dbg(ioat, desc);
478 /* we leave the channel locked to ensure in order submission */
482 static struct dma_async_tx_descriptor *
483 __ioat3_prep_xor_lock(struct dma_chan *c, enum sum_check_flags *result,
484 dma_addr_t dest, dma_addr_t *src, unsigned int src_cnt,
485 size_t len, unsigned long flags)
487 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
488 struct ioat_ring_ent *compl_desc;
489 struct ioat_ring_ent *desc;
490 struct ioat_ring_ent *ext;
491 size_t total_len = len;
492 struct ioat_xor_descriptor *xor;
493 struct ioat_xor_ext_descriptor *xor_ex = NULL;
494 struct ioat_dma_descriptor *hw;
500 u8 op = result ? IOAT_OP_XOR_VAL : IOAT_OP_XOR;
504 num_descs = ioat2_xferlen_to_descs(ioat, len);
505 /* we need 2x the number of descriptors to cover greater than 5
514 /* completion writes from the raid engine may pass completion
515 * writes from the legacy engine, so we need one extra null
516 * (legacy) descriptor to ensure all completion writes arrive in
519 if (likely(num_descs) &&
520 ioat2_alloc_and_lock(&idx, ioat, num_descs+1) == 0)
526 struct ioat_raw_descriptor *descs[2];
527 size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log);
530 desc = ioat2_get_ring_ent(ioat, idx + i);
533 /* save a branch by unconditionally retrieving the
534 * extended descriptor xor_set_src() knows to not write
535 * to it in the single descriptor case
537 ext = ioat2_get_ring_ent(ioat, idx + i + 1);
538 xor_ex = ext->xor_ex;
540 descs[0] = (struct ioat_raw_descriptor *) xor;
541 descs[1] = (struct ioat_raw_descriptor *) xor_ex;
542 for (s = 0; s < src_cnt; s++)
543 xor_set_src(descs, src[s], offset, s);
544 xor->size = xfer_size;
545 xor->dst_addr = dest + offset;
548 xor->ctl_f.src_cnt = src_cnt_to_hw(src_cnt);
552 dump_desc_dbg(ioat, desc);
553 } while ((i += 1 + with_ext) < num_descs);
555 /* last xor descriptor carries the unmap parameters and fence bit */
556 desc->txd.flags = flags;
557 desc->len = total_len;
559 desc->result = result;
560 xor->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
562 /* completion descriptor carries interrupt bit */
563 compl_desc = ioat2_get_ring_ent(ioat, idx + i);
564 compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT;
568 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
569 hw->ctl_f.compl_write = 1;
570 hw->size = NULL_DESC_BUFFER_SIZE;
571 dump_desc_dbg(ioat, compl_desc);
573 /* we leave the channel locked to ensure in order submission */
574 return &compl_desc->txd;
577 static struct dma_async_tx_descriptor *
578 ioat3_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
579 unsigned int src_cnt, size_t len, unsigned long flags)
581 return __ioat3_prep_xor_lock(chan, NULL, dest, src, src_cnt, len, flags);
584 struct dma_async_tx_descriptor *
585 ioat3_prep_xor_val(struct dma_chan *chan, dma_addr_t *src,
586 unsigned int src_cnt, size_t len,
587 enum sum_check_flags *result, unsigned long flags)
589 /* the cleanup routine only sets bits on validate failure, it
590 * does not clear bits on validate success... so clear it here
594 return __ioat3_prep_xor_lock(chan, result, src[0], &src[1],
595 src_cnt - 1, len, flags);
599 dump_pq_desc_dbg(struct ioat2_dma_chan *ioat, struct ioat_ring_ent *desc, struct ioat_ring_ent *ext)
601 struct device *dev = to_dev(&ioat->base);
602 struct ioat_pq_descriptor *pq = desc->pq;
603 struct ioat_pq_ext_descriptor *pq_ex = ext ? ext->pq_ex : NULL;
604 struct ioat_raw_descriptor *descs[] = { (void *) pq, (void *) pq_ex };
605 int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt);
608 dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x"
609 " sz: %#x ctl: %#x (op: %d int: %d compl: %d pq: '%s%s' src_cnt: %d)\n",
610 desc_id(desc), (unsigned long long) desc->txd.phys,
611 (unsigned long long) (pq_ex ? pq_ex->next : pq->next),
612 desc->txd.flags, pq->size, pq->ctl, pq->ctl_f.op, pq->ctl_f.int_en,
613 pq->ctl_f.compl_write,
614 pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q",
616 for (i = 0; i < src_cnt; i++)
617 dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i,
618 (unsigned long long) pq_get_src(descs, i), pq->coef[i]);
619 dev_dbg(dev, "\tP: %#llx\n", pq->p_addr);
620 dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr);
623 static struct dma_async_tx_descriptor *
624 __ioat3_prep_pq_lock(struct dma_chan *c, enum sum_check_flags *result,
625 const dma_addr_t *dst, const dma_addr_t *src,
626 unsigned int src_cnt, const unsigned char *scf,
627 size_t len, unsigned long flags)
629 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
630 struct ioat_chan_common *chan = &ioat->base;
631 struct ioat_ring_ent *compl_desc;
632 struct ioat_ring_ent *desc;
633 struct ioat_ring_ent *ext;
634 size_t total_len = len;
635 struct ioat_pq_descriptor *pq;
636 struct ioat_pq_ext_descriptor *pq_ex = NULL;
637 struct ioat_dma_descriptor *hw;
643 u8 op = result ? IOAT_OP_PQ_VAL : IOAT_OP_PQ;
645 dev_dbg(to_dev(chan), "%s\n", __func__);
646 /* the engine requires at least two sources (we provide
647 * at least 1 implied source in the DMA_PREP_CONTINUE case)
649 BUG_ON(src_cnt + dmaf_continue(flags) < 2);
651 num_descs = ioat2_xferlen_to_descs(ioat, len);
652 /* we need 2x the number of descriptors to cover greater than 3
653 * sources (we need 1 extra source in the q-only continuation
654 * case and 3 extra sources in the p+q continuation case.
656 if (src_cnt + dmaf_p_disabled_continue(flags) > 3 ||
657 (dmaf_continue(flags) && !dmaf_p_disabled_continue(flags))) {
663 /* completion writes from the raid engine may pass completion
664 * writes from the legacy engine, so we need one extra null
665 * (legacy) descriptor to ensure all completion writes arrive in
668 if (likely(num_descs) &&
669 ioat2_alloc_and_lock(&idx, ioat, num_descs+1) == 0)
675 struct ioat_raw_descriptor *descs[2];
676 size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log);
678 desc = ioat2_get_ring_ent(ioat, idx + i);
681 /* save a branch by unconditionally retrieving the
682 * extended descriptor pq_set_src() knows to not write
683 * to it in the single descriptor case
685 ext = ioat2_get_ring_ent(ioat, idx + i + with_ext);
688 descs[0] = (struct ioat_raw_descriptor *) pq;
689 descs[1] = (struct ioat_raw_descriptor *) pq_ex;
691 for (s = 0; s < src_cnt; s++)
692 pq_set_src(descs, src[s], offset, scf[s], s);
694 /* see the comment for dma_maxpq in include/linux/dmaengine.h */
695 if (dmaf_p_disabled_continue(flags))
696 pq_set_src(descs, dst[1], offset, 1, s++);
697 else if (dmaf_continue(flags)) {
698 pq_set_src(descs, dst[0], offset, 0, s++);
699 pq_set_src(descs, dst[1], offset, 1, s++);
700 pq_set_src(descs, dst[1], offset, 0, s++);
702 pq->size = xfer_size;
703 pq->p_addr = dst[0] + offset;
704 pq->q_addr = dst[1] + offset;
707 pq->ctl_f.src_cnt = src_cnt_to_hw(s);
708 pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P);
709 pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q);
713 } while ((i += 1 + with_ext) < num_descs);
715 /* last pq descriptor carries the unmap parameters and fence bit */
716 desc->txd.flags = flags;
717 desc->len = total_len;
719 desc->result = result;
720 pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
721 dump_pq_desc_dbg(ioat, desc, ext);
723 /* completion descriptor carries interrupt bit */
724 compl_desc = ioat2_get_ring_ent(ioat, idx + i);
725 compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT;
729 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
730 hw->ctl_f.compl_write = 1;
731 hw->size = NULL_DESC_BUFFER_SIZE;
732 dump_desc_dbg(ioat, compl_desc);
734 /* we leave the channel locked to ensure in order submission */
735 return &compl_desc->txd;
738 static struct dma_async_tx_descriptor *
739 ioat3_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
740 unsigned int src_cnt, const unsigned char *scf, size_t len,
743 /* specify valid address for disabled result */
744 if (flags & DMA_PREP_PQ_DISABLE_P)
746 if (flags & DMA_PREP_PQ_DISABLE_Q)
749 /* handle the single source multiply case from the raid6
752 if ((flags & DMA_PREP_PQ_DISABLE_P) && src_cnt == 1) {
753 dma_addr_t single_source[2];
754 unsigned char single_source_coef[2];
756 BUG_ON(flags & DMA_PREP_PQ_DISABLE_Q);
757 single_source[0] = src[0];
758 single_source[1] = src[0];
759 single_source_coef[0] = scf[0];
760 single_source_coef[1] = 0;
762 return __ioat3_prep_pq_lock(chan, NULL, dst, single_source, 2,
763 single_source_coef, len, flags);
765 return __ioat3_prep_pq_lock(chan, NULL, dst, src, src_cnt, scf,
769 struct dma_async_tx_descriptor *
770 ioat3_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
771 unsigned int src_cnt, const unsigned char *scf, size_t len,
772 enum sum_check_flags *pqres, unsigned long flags)
774 /* specify valid address for disabled result */
775 if (flags & DMA_PREP_PQ_DISABLE_P)
777 if (flags & DMA_PREP_PQ_DISABLE_Q)
780 /* the cleanup routine only sets bits on validate failure, it
781 * does not clear bits on validate success... so clear it here
785 return __ioat3_prep_pq_lock(chan, pqres, pq, src, src_cnt, scf, len,
789 static struct dma_async_tx_descriptor *
790 ioat3_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
791 unsigned int src_cnt, size_t len, unsigned long flags)
793 unsigned char scf[src_cnt];
796 memset(scf, 0, src_cnt);
798 flags |= DMA_PREP_PQ_DISABLE_Q;
799 pq[1] = dst; /* specify valid address for disabled result */
801 return __ioat3_prep_pq_lock(chan, NULL, pq, src, src_cnt, scf, len,
805 struct dma_async_tx_descriptor *
806 ioat3_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src,
807 unsigned int src_cnt, size_t len,
808 enum sum_check_flags *result, unsigned long flags)
810 unsigned char scf[src_cnt];
813 /* the cleanup routine only sets bits on validate failure, it
814 * does not clear bits on validate success... so clear it here
818 memset(scf, 0, src_cnt);
820 flags |= DMA_PREP_PQ_DISABLE_Q;
821 pq[1] = pq[0]; /* specify valid address for disabled result */
823 return __ioat3_prep_pq_lock(chan, result, pq, &src[1], src_cnt - 1, scf,
827 static struct dma_async_tx_descriptor *
828 ioat3_prep_interrupt_lock(struct dma_chan *c, unsigned long flags)
830 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
831 struct ioat_ring_ent *desc;
832 struct ioat_dma_descriptor *hw;
835 if (ioat2_alloc_and_lock(&idx, ioat, 1) == 0)
836 desc = ioat2_get_ring_ent(ioat, idx);
843 hw->ctl_f.int_en = 1;
844 hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
845 hw->ctl_f.compl_write = 1;
846 hw->size = NULL_DESC_BUFFER_SIZE;
850 desc->txd.flags = flags;
853 dump_desc_dbg(ioat, desc);
855 /* we leave the channel locked to ensure in order submission */
859 static void __devinit ioat3_dma_test_callback(void *dma_async_param)
861 struct completion *cmp = dma_async_param;
866 #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */
867 static int __devinit ioat_xor_val_self_test(struct ioatdma_device *device)
871 struct page *xor_srcs[IOAT_NUM_SRC_TEST];
872 struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1];
873 dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1];
874 dma_addr_t dma_addr, dest_dma;
875 struct dma_async_tx_descriptor *tx;
876 struct dma_chan *dma_chan;
882 struct completion cmp;
884 struct device *dev = &device->pdev->dev;
885 struct dma_device *dma = &device->common;
887 dev_dbg(dev, "%s\n", __func__);
889 if (!dma_has_cap(DMA_XOR, dma->cap_mask))
892 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
893 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
894 if (!xor_srcs[src_idx]) {
896 __free_page(xor_srcs[src_idx]);
901 dest = alloc_page(GFP_KERNEL);
904 __free_page(xor_srcs[src_idx]);
908 /* Fill in src buffers */
909 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
910 u8 *ptr = page_address(xor_srcs[src_idx]);
911 for (i = 0; i < PAGE_SIZE; i++)
912 ptr[i] = (1 << src_idx);
915 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++)
916 cmp_byte ^= (u8) (1 << src_idx);
918 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
919 (cmp_byte << 8) | cmp_byte;
921 memset(page_address(dest), 0, PAGE_SIZE);
923 dma_chan = container_of(dma->channels.next, struct dma_chan,
925 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
931 dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE);
932 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
933 dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE,
935 tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
936 IOAT_NUM_SRC_TEST, PAGE_SIZE,
940 dev_err(dev, "Self-test xor prep failed\n");
946 init_completion(&cmp);
947 tx->callback = ioat3_dma_test_callback;
948 tx->callback_param = &cmp;
949 cookie = tx->tx_submit(tx);
951 dev_err(dev, "Self-test xor setup failed\n");
955 dma->device_issue_pending(dma_chan);
957 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
959 if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
960 dev_err(dev, "Self-test xor timed out\n");
965 dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
966 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
967 u32 *ptr = page_address(dest);
968 if (ptr[i] != cmp_word) {
969 dev_err(dev, "Self-test xor failed compare\n");
974 dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_TO_DEVICE);
976 /* skip validate if the capability is not present */
977 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask))
980 /* validate the sources with the destintation page */
981 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
982 xor_val_srcs[i] = xor_srcs[i];
983 xor_val_srcs[i] = dest;
987 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
988 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
990 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
991 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
992 &xor_val_result, DMA_PREP_INTERRUPT);
994 dev_err(dev, "Self-test zero prep failed\n");
1000 init_completion(&cmp);
1001 tx->callback = ioat3_dma_test_callback;
1002 tx->callback_param = &cmp;
1003 cookie = tx->tx_submit(tx);
1005 dev_err(dev, "Self-test zero setup failed\n");
1007 goto free_resources;
1009 dma->device_issue_pending(dma_chan);
1011 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
1013 if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1014 dev_err(dev, "Self-test validate timed out\n");
1016 goto free_resources;
1019 if (xor_val_result != 0) {
1020 dev_err(dev, "Self-test validate failed compare\n");
1022 goto free_resources;
1025 /* skip memset if the capability is not present */
1026 if (!dma_has_cap(DMA_MEMSET, dma_chan->device->cap_mask))
1027 goto free_resources;
1030 dma_addr = dma_map_page(dev, dest, 0,
1031 PAGE_SIZE, DMA_FROM_DEVICE);
1032 tx = dma->device_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE,
1033 DMA_PREP_INTERRUPT);
1035 dev_err(dev, "Self-test memset prep failed\n");
1037 goto free_resources;
1041 init_completion(&cmp);
1042 tx->callback = ioat3_dma_test_callback;
1043 tx->callback_param = &cmp;
1044 cookie = tx->tx_submit(tx);
1046 dev_err(dev, "Self-test memset setup failed\n");
1048 goto free_resources;
1050 dma->device_issue_pending(dma_chan);
1052 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
1054 if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1055 dev_err(dev, "Self-test memset timed out\n");
1057 goto free_resources;
1060 for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) {
1061 u32 *ptr = page_address(dest);
1063 dev_err(dev, "Self-test memset failed compare\n");
1065 goto free_resources;
1069 /* test for non-zero parity sum */
1071 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1072 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
1074 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
1075 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
1076 &xor_val_result, DMA_PREP_INTERRUPT);
1078 dev_err(dev, "Self-test 2nd zero prep failed\n");
1080 goto free_resources;
1084 init_completion(&cmp);
1085 tx->callback = ioat3_dma_test_callback;
1086 tx->callback_param = &cmp;
1087 cookie = tx->tx_submit(tx);
1089 dev_err(dev, "Self-test 2nd zero setup failed\n");
1091 goto free_resources;
1093 dma->device_issue_pending(dma_chan);
1095 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
1097 if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1098 dev_err(dev, "Self-test 2nd validate timed out\n");
1100 goto free_resources;
1103 if (xor_val_result != SUM_CHECK_P_RESULT) {
1104 dev_err(dev, "Self-test validate failed compare\n");
1106 goto free_resources;
1110 dma->device_free_chan_resources(dma_chan);
1112 src_idx = IOAT_NUM_SRC_TEST;
1114 __free_page(xor_srcs[src_idx]);
1119 static int __devinit ioat3_dma_self_test(struct ioatdma_device *device)
1121 int rc = ioat_dma_self_test(device);
1126 rc = ioat_xor_val_self_test(device);
1133 static int ioat3_reset_hw(struct ioat_chan_common *chan)
1135 /* throw away whatever the channel was doing and get it
1136 * initialized, with ioat3 specific workarounds
1138 struct ioatdma_device *device = chan->device;
1139 struct pci_dev *pdev = device->pdev;
1144 ioat2_quiesce(chan, msecs_to_jiffies(100));
1146 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
1147 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
1149 /* -= IOAT ver.3 workarounds =- */
1150 /* Write CHANERRMSK_INT with 3E07h to mask out the errors
1151 * that can cause stability issues for IOAT ver.3, and clear any
1154 pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0x3e07);
1155 err = pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr);
1157 dev_err(&pdev->dev, "channel error register unreachable\n");
1160 pci_write_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, chanerr);
1162 /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit
1163 * (workaround for spurious config parity error after restart)
1165 pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id);
1166 if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0)
1167 pci_write_config_dword(pdev, IOAT_PCI_DMAUNCERRSTS_OFFSET, 0x10);
1169 return ioat2_reset_sync(chan, msecs_to_jiffies(200));
1172 int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca)
1174 struct pci_dev *pdev = device->pdev;
1175 int dca_en = system_has_dca_enabled(pdev);
1176 struct dma_device *dma;
1178 struct ioat_chan_common *chan;
1179 bool is_raid_device = false;
1183 device->enumerate_channels = ioat2_enumerate_channels;
1184 device->reset_hw = ioat3_reset_hw;
1185 device->self_test = ioat3_dma_self_test;
1186 dma = &device->common;
1187 dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock;
1188 dma->device_issue_pending = ioat2_issue_pending;
1189 dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;
1190 dma->device_free_chan_resources = ioat2_free_chan_resources;
1192 dma_cap_set(DMA_INTERRUPT, dma->cap_mask);
1193 dma->device_prep_dma_interrupt = ioat3_prep_interrupt_lock;
1195 cap = readl(device->reg_base + IOAT_DMA_CAP_OFFSET);
1197 /* dca is incompatible with raid operations */
1198 if (dca_en && (cap & (IOAT_CAP_XOR|IOAT_CAP_PQ)))
1199 cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ);
1201 if (cap & IOAT_CAP_XOR) {
1202 is_raid_device = true;
1206 dma_cap_set(DMA_XOR, dma->cap_mask);
1207 dma->device_prep_dma_xor = ioat3_prep_xor;
1209 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1210 dma->device_prep_dma_xor_val = ioat3_prep_xor_val;
1212 if (cap & IOAT_CAP_PQ) {
1213 is_raid_device = true;
1214 dma_set_maxpq(dma, 8, 0);
1217 dma_cap_set(DMA_PQ, dma->cap_mask);
1218 dma->device_prep_dma_pq = ioat3_prep_pq;
1220 dma_cap_set(DMA_PQ_VAL, dma->cap_mask);
1221 dma->device_prep_dma_pq_val = ioat3_prep_pq_val;
1223 if (!(cap & IOAT_CAP_XOR)) {
1227 dma_cap_set(DMA_XOR, dma->cap_mask);
1228 dma->device_prep_dma_xor = ioat3_prep_pqxor;
1230 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1231 dma->device_prep_dma_xor_val = ioat3_prep_pqxor_val;
1234 if (is_raid_device && (cap & IOAT_CAP_FILL_BLOCK)) {
1235 dma_cap_set(DMA_MEMSET, dma->cap_mask);
1236 dma->device_prep_dma_memset = ioat3_prep_memset_lock;
1240 if (is_raid_device) {
1241 dma->device_is_tx_complete = ioat3_is_complete;
1242 device->cleanup_tasklet = ioat3_cleanup_tasklet;
1243 device->timer_fn = ioat3_timer_event;
1245 dma->device_is_tx_complete = ioat2_is_complete;
1246 device->cleanup_tasklet = ioat2_cleanup_tasklet;
1247 device->timer_fn = ioat2_timer_event;
1250 #ifdef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
1251 dma_cap_clear(DMA_PQ_VAL, dma->cap_mask);
1252 dma->device_prep_dma_pq_val = NULL;
1255 #ifdef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
1256 dma_cap_clear(DMA_XOR_VAL, dma->cap_mask);
1257 dma->device_prep_dma_xor_val = NULL;
1260 err = ioat_probe(device);
1263 ioat_set_tcp_copy_break(262144);
1265 list_for_each_entry(c, &dma->channels, device_node) {
1266 chan = to_chan_common(c);
1267 writel(IOAT_DMA_DCA_ANY_CPU,
1268 chan->reg_base + IOAT_DCACTRL_OFFSET);
1271 err = ioat_register(device);
1275 ioat_kobject_add(device, &ioat2_ktype);
1278 device->dca = ioat3_dca_init(pdev, device->reg_base);