drivers/dma/ioat/hw.h

   1 /*
   2  * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc., 59
  16  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called COPYING.
  20  */
  21 #ifndef _IOAT_HW_H_
  22 #define _IOAT_HW_H_
  23
  24 /* PCI Configuration Space Values */
  25 #define IOAT_MMIO_BAR           0
  26
  27 /* CB device ID's */
  28 #define IOAT_PCI_DID_5000       0x1A38
  29 #define IOAT_PCI_DID_CNB        0x360B
  30 #define IOAT_PCI_DID_SCNB       0x65FF
  31 #define IOAT_PCI_DID_SNB        0x402F
  32
  33 #define PCI_DEVICE_ID_INTEL_IOAT_IVB0   0x0e20
  34 #define PCI_DEVICE_ID_INTEL_IOAT_IVB1   0x0e21
  35 #define PCI_DEVICE_ID_INTEL_IOAT_IVB2   0x0e22
  36 #define PCI_DEVICE_ID_INTEL_IOAT_IVB3   0x0e23
  37 #define PCI_DEVICE_ID_INTEL_IOAT_IVB4   0x0e24
  38 #define PCI_DEVICE_ID_INTEL_IOAT_IVB5   0x0e25
  39 #define PCI_DEVICE_ID_INTEL_IOAT_IVB6   0x0e26
  40 #define PCI_DEVICE_ID_INTEL_IOAT_IVB7   0x0e27
  41 #define PCI_DEVICE_ID_INTEL_IOAT_IVB8   0x0e2e
  42 #define PCI_DEVICE_ID_INTEL_IOAT_IVB9   0x0e2f
  43
  44 #define PCI_DEVICE_ID_INTEL_IOAT_HSW0   0x2f20
  45 #define PCI_DEVICE_ID_INTEL_IOAT_HSW1   0x2f21
  46 #define PCI_DEVICE_ID_INTEL_IOAT_HSW2   0x2f22
  47 #define PCI_DEVICE_ID_INTEL_IOAT_HSW3   0x2f23
  48 #define PCI_DEVICE_ID_INTEL_IOAT_HSW4   0x2f24
  49 #define PCI_DEVICE_ID_INTEL_IOAT_HSW5   0x2f25
  50 #define PCI_DEVICE_ID_INTEL_IOAT_HSW6   0x2f26
  51 #define PCI_DEVICE_ID_INTEL_IOAT_HSW7   0x2f27
  52 #define PCI_DEVICE_ID_INTEL_IOAT_HSW8   0x2f2e
  53 #define PCI_DEVICE_ID_INTEL_IOAT_HSW9   0x2f2f
  54
  55 #define PCI_DEVICE_ID_INTEL_IOAT_BWD0   0x0C50
  56 #define PCI_DEVICE_ID_INTEL_IOAT_BWD1   0x0C51
  57 #define PCI_DEVICE_ID_INTEL_IOAT_BWD2   0x0C52
  58 #define PCI_DEVICE_ID_INTEL_IOAT_BWD3   0x0C53
  59
  60 #define IOAT_VER_1_2            0x12    /* Version 1.2 */
  61 #define IOAT_VER_2_0            0x20    /* Version 2.0 */
  62 #define IOAT_VER_3_0            0x30    /* Version 3.0 */
  63 #define IOAT_VER_3_2            0x32    /* Version 3.2 */
  64 #define IOAT_VER_3_3            0x33    /* Version 3.3 */
  65
  66
  67 int system_has_dca_enabled(struct pci_dev *pdev);
  68
  69 struct ioat_dma_descriptor {
  70         uint32_t        size;
  71         union {
  72                 uint32_t ctl;
  73                 struct {
  74                         unsigned int int_en:1;
  75                         unsigned int src_snoop_dis:1;
  76                         unsigned int dest_snoop_dis:1;
  77                         unsigned int compl_write:1;
  78                         unsigned int fence:1;
  79                         unsigned int null:1;
  80                         unsigned int src_brk:1;
  81                         unsigned int dest_brk:1;
  82                         unsigned int bundle:1;
  83                         unsigned int dest_dca:1;
  84                         unsigned int hint:1;
  85                         unsigned int rsvd2:13;
  86                         #define IOAT_OP_COPY 0x00
  87                         unsigned int op:8;
  88                 } ctl_f;
  89         };
  90         uint64_t        src_addr;
  91         uint64_t        dst_addr;
  92         uint64_t        next;
  93         uint64_t        rsv1;
  94         uint64_t        rsv2;
  95         /* store some driver data in an unused portion of the descriptor */
  96         union {
  97                 uint64_t        user1;
  98                 uint64_t        tx_cnt;
  99         };
 100         uint64_t        user2;
 101 };
 102
 103 struct ioat_fill_descriptor {
 104         uint32_t        size;
 105         union {
 106                 uint32_t ctl;
 107                 struct {
 108                         unsigned int int_en:1;
 109                         unsigned int rsvd:1;
 110                         unsigned int dest_snoop_dis:1;
 111                         unsigned int compl_write:1;
 112                         unsigned int fence:1;
 113                         unsigned int rsvd2:2;
 114                         unsigned int dest_brk:1;
 115                         unsigned int bundle:1;
 116                         unsigned int rsvd4:15;
 117                         #define IOAT_OP_FILL 0x01
 118                         unsigned int op:8;
 119                 } ctl_f;
 120         };
 121         uint64_t        src_data;
 122         uint64_t        dst_addr;
 123         uint64_t        next;
 124         uint64_t        rsv1;
 125         uint64_t        next_dst_addr;
 126         uint64_t        user1;
 127         uint64_t        user2;
 128 };
 129
 130 struct ioat_xor_descriptor {
 131         uint32_t        size;
 132         union {
 133                 uint32_t ctl;
 134                 struct {
 135                         unsigned int int_en:1;
 136                         unsigned int src_snoop_dis:1;
 137                         unsigned int dest_snoop_dis:1;
 138                         unsigned int compl_write:1;
 139                         unsigned int fence:1;
 140                         unsigned int src_cnt:3;
 141                         unsigned int bundle:1;
 142                         unsigned int dest_dca:1;
 143                         unsigned int hint:1;
 144                         unsigned int rsvd:13;
 145                         #define IOAT_OP_XOR 0x87
 146                         #define IOAT_OP_XOR_VAL 0x88
 147                         unsigned int op:8;
 148                 } ctl_f;
 149         };
 150         uint64_t        src_addr;
 151         uint64_t        dst_addr;
 152         uint64_t        next;
 153         uint64_t        src_addr2;
 154         uint64_t        src_addr3;
 155         uint64_t        src_addr4;
 156         uint64_t        src_addr5;
 157 };
 158
 159 struct ioat_xor_ext_descriptor {
 160         uint64_t        src_addr6;
 161         uint64_t        src_addr7;
 162         uint64_t        src_addr8;
 163         uint64_t        next;
 164         uint64_t        rsvd[4];
 165 };
 166
 167 struct ioat_pq_descriptor {
 168         union {
 169                 uint32_t        size;
 170                 uint32_t        dwbes;
 171                 struct {
 172                         unsigned int rsvd:25;
 173                         unsigned int p_val_err:1;
 174                         unsigned int q_val_err:1;
 175                         unsigned int rsvd1:4;
 176                         unsigned int wbes:1;
 177                 } dwbes_f;
 178         };
 179         union {
 180                 uint32_t ctl;
 181                 struct {
 182                         unsigned int int_en:1;
 183                         unsigned int src_snoop_dis:1;
 184                         unsigned int dest_snoop_dis:1;
 185                         unsigned int compl_write:1;
 186                         unsigned int fence:1;
 187                         unsigned int src_cnt:3;
 188                         unsigned int bundle:1;
 189                         unsigned int dest_dca:1;
 190                         unsigned int hint:1;
 191                         unsigned int p_disable:1;
 192                         unsigned int q_disable:1;
 193                         unsigned int rsvd2:2;
 194                         unsigned int wb_en:1;
 195                         unsigned int prl_en:1;
 196                         unsigned int rsvd3:7;
 197                         #define IOAT_OP_PQ 0x89
 198                         #define IOAT_OP_PQ_VAL 0x8a
 199                         #define IOAT_OP_PQ_16S 0xa0
 200                         #define IOAT_OP_PQ_VAL_16S 0xa1
 201                         unsigned int op:8;
 202                 } ctl_f;
 203         };
 204         uint64_t        src_addr;
 205         uint64_t        p_addr;
 206         uint64_t        next;
 207         uint64_t        src_addr2;
 208         union {
 209                 uint64_t        src_addr3;
 210                 uint64_t        sed_addr;
 211         };
 212         uint8_t         coef[8];
 213         uint64_t        q_addr;
 214 };
 215
 216 struct ioat_pq_ext_descriptor {
 217         uint64_t        src_addr4;
 218         uint64_t        src_addr5;
 219         uint64_t        src_addr6;
 220         uint64_t        next;
 221         uint64_t        src_addr7;
 222         uint64_t        src_addr8;
 223         uint64_t        rsvd[2];
 224 };
 225
 226 struct ioat_pq_update_descriptor {
 227         uint32_t        size;
 228         union {
 229                 uint32_t ctl;
 230                 struct {
 231                         unsigned int int_en:1;
 232                         unsigned int src_snoop_dis:1;
 233                         unsigned int dest_snoop_dis:1;
 234                         unsigned int compl_write:1;
 235                         unsigned int fence:1;
 236                         unsigned int src_cnt:3;
 237                         unsigned int bundle:1;
 238                         unsigned int dest_dca:1;
 239                         unsigned int hint:1;
 240                         unsigned int p_disable:1;
 241                         unsigned int q_disable:1;
 242                         unsigned int rsvd:3;
 243                         unsigned int coef:8;
 244                         #define IOAT_OP_PQ_UP 0x8b
 245                         unsigned int op:8;
 246                 } ctl_f;
 247         };
 248         uint64_t        src_addr;
 249         uint64_t        p_addr;
 250         uint64_t        next;
 251         uint64_t        src_addr2;
 252         uint64_t        p_src;
 253         uint64_t        q_src;
 254         uint64_t        q_addr;
 255 };
 256
 257 struct ioat_raw_descriptor {
 258         uint64_t        field[8];
 259 };
 260
 261 struct ioat_pq16a_descriptor {
 262         uint8_t coef[8];
 263         uint64_t src_addr3;
 264         uint64_t src_addr4;
 265         uint64_t src_addr5;
 266         uint64_t src_addr6;
 267         uint64_t src_addr7;
 268         uint64_t src_addr8;
 269         uint64_t src_addr9;
 270 };
 271
 272 struct ioat_pq16b_descriptor {
 273         uint64_t src_addr10;
 274         uint64_t src_addr11;
 275         uint64_t src_addr12;
 276         uint64_t src_addr13;
 277         uint64_t src_addr14;
 278         uint64_t src_addr15;
 279         uint64_t src_addr16;
 280         uint64_t rsvd;
 281 };
 282
 283 union ioat_sed_pq_descriptor {
 284         struct ioat_pq16a_descriptor a;
 285         struct ioat_pq16b_descriptor b;
 286 };
 287
 288 #define SED_SIZE        64
 289
 290 struct ioat_sed_raw_descriptor {
 291         uint64_t        a[8];
 292         uint64_t        b[8];
 293         uint64_t        c[8];
 294 };
 295
 296 #endif