2 * Intel I/OAT DMA Linux driver
3 * Copyright(c) 2004 - 2015 Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in
15 * the file called "COPYING".
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/gfp.h>
21 #include <linux/dmaengine.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/prefetch.h>
24 #include "../dmaengine.h"
25 #include "registers.h"
29 /* provide a lookup table for setting the source address in the base or
30 * extended descriptor of an xor or pq descriptor
32 static const u8 xor_idx_to_desc = 0xe0;
33 static const u8 xor_idx_to_field[] = { 1, 4, 5, 6, 7, 0, 1, 2 };
34 static const u8 pq_idx_to_desc = 0xf8;
35 static const u8 pq16_idx_to_desc[] = { 0, 0, 1, 1, 1, 1, 1, 1, 1,
36 2, 2, 2, 2, 2, 2, 2 };
37 static const u8 pq_idx_to_field[] = { 1, 4, 5, 0, 1, 2, 4, 5 };
38 static const u8 pq16_idx_to_field[] = { 1, 4, 1, 2, 3, 4, 5, 6, 7,
39 0, 1, 2, 3, 4, 5, 6 };
41 static void xor_set_src(struct ioat_raw_descriptor *descs[2],
42 dma_addr_t addr, u32 offset, int idx)
44 struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1];
46 raw->field[xor_idx_to_field[idx]] = addr + offset;
49 static dma_addr_t pq_get_src(struct ioat_raw_descriptor *descs[2], int idx)
51 struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1];
53 return raw->field[pq_idx_to_field[idx]];
56 static dma_addr_t pq16_get_src(struct ioat_raw_descriptor *desc[3], int idx)
58 struct ioat_raw_descriptor *raw = desc[pq16_idx_to_desc[idx]];
60 return raw->field[pq16_idx_to_field[idx]];
63 static void pq_set_src(struct ioat_raw_descriptor *descs[2],
64 dma_addr_t addr, u32 offset, u8 coef, int idx)
66 struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *) descs[0];
67 struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1];
69 raw->field[pq_idx_to_field[idx]] = addr + offset;
73 static void pq16_set_src(struct ioat_raw_descriptor *desc[3],
74 dma_addr_t addr, u32 offset, u8 coef, unsigned idx)
76 struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *)desc[0];
77 struct ioat_pq16a_descriptor *pq16 =
78 (struct ioat_pq16a_descriptor *)desc[1];
79 struct ioat_raw_descriptor *raw = desc[pq16_idx_to_desc[idx]];
81 raw->field[pq16_idx_to_field[idx]] = addr + offset;
86 pq16->coef[idx - 8] = coef;
89 static struct ioat_sed_ent *
90 ioat3_alloc_sed(struct ioatdma_device *ioat_dma, unsigned int hw_pool)
92 struct ioat_sed_ent *sed;
93 gfp_t flags = __GFP_ZERO | GFP_ATOMIC;
95 sed = kmem_cache_alloc(ioat_sed_cache, flags);
99 sed->hw_pool = hw_pool;
100 sed->hw = dma_pool_alloc(ioat_dma->sed_hw_pool[hw_pool],
103 kmem_cache_free(ioat_sed_cache, sed);
110 struct dma_async_tx_descriptor *
111 ioat_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
112 dma_addr_t dma_src, size_t len, unsigned long flags)
114 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
115 struct ioat_dma_descriptor *hw;
116 struct ioat_ring_ent *desc;
117 dma_addr_t dst = dma_dest;
118 dma_addr_t src = dma_src;
119 size_t total_len = len;
120 int num_descs, idx, i;
122 num_descs = ioat_xferlen_to_descs(ioat_chan, len);
123 if (likely(num_descs) &&
124 ioat_check_space_lock(ioat_chan, num_descs) == 0)
125 idx = ioat_chan->head;
130 size_t copy = min_t(size_t, len, 1 << ioat_chan->xfercap_log);
132 desc = ioat_get_ring_ent(ioat_chan, idx + i);
143 dump_desc_dbg(ioat_chan, desc);
144 } while (++i < num_descs);
146 desc->txd.flags = flags;
147 desc->len = total_len;
148 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
149 hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
150 hw->ctl_f.compl_write = 1;
151 dump_desc_dbg(ioat_chan, desc);
152 /* we leave the channel locked to ensure in order submission */
158 static struct dma_async_tx_descriptor *
159 __ioat_prep_xor_lock(struct dma_chan *c, enum sum_check_flags *result,
160 dma_addr_t dest, dma_addr_t *src, unsigned int src_cnt,
161 size_t len, unsigned long flags)
163 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
164 struct ioat_ring_ent *compl_desc;
165 struct ioat_ring_ent *desc;
166 struct ioat_ring_ent *ext;
167 size_t total_len = len;
168 struct ioat_xor_descriptor *xor;
169 struct ioat_xor_ext_descriptor *xor_ex = NULL;
170 struct ioat_dma_descriptor *hw;
171 int num_descs, with_ext, idx, i;
173 u8 op = result ? IOAT_OP_XOR_VAL : IOAT_OP_XOR;
177 num_descs = ioat_xferlen_to_descs(ioat_chan, len);
178 /* we need 2x the number of descriptors to cover greater than 5
187 /* completion writes from the raid engine may pass completion
188 * writes from the legacy engine, so we need one extra null
189 * (legacy) descriptor to ensure all completion writes arrive in
192 if (likely(num_descs) &&
193 ioat_check_space_lock(ioat_chan, num_descs+1) == 0)
194 idx = ioat_chan->head;
199 struct ioat_raw_descriptor *descs[2];
200 size_t xfer_size = min_t(size_t,
201 len, 1 << ioat_chan->xfercap_log);
204 desc = ioat_get_ring_ent(ioat_chan, idx + i);
207 /* save a branch by unconditionally retrieving the
208 * extended descriptor xor_set_src() knows to not write
209 * to it in the single descriptor case
211 ext = ioat_get_ring_ent(ioat_chan, idx + i + 1);
212 xor_ex = ext->xor_ex;
214 descs[0] = (struct ioat_raw_descriptor *) xor;
215 descs[1] = (struct ioat_raw_descriptor *) xor_ex;
216 for (s = 0; s < src_cnt; s++)
217 xor_set_src(descs, src[s], offset, s);
218 xor->size = xfer_size;
219 xor->dst_addr = dest + offset;
222 xor->ctl_f.src_cnt = src_cnt_to_hw(src_cnt);
226 dump_desc_dbg(ioat_chan, desc);
227 } while ((i += 1 + with_ext) < num_descs);
229 /* last xor descriptor carries the unmap parameters and fence bit */
230 desc->txd.flags = flags;
231 desc->len = total_len;
233 desc->result = result;
234 xor->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
236 /* completion descriptor carries interrupt bit */
237 compl_desc = ioat_get_ring_ent(ioat_chan, idx + i);
238 compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT;
242 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
243 hw->ctl_f.compl_write = 1;
244 hw->size = NULL_DESC_BUFFER_SIZE;
245 dump_desc_dbg(ioat_chan, compl_desc);
247 /* we leave the channel locked to ensure in order submission */
248 return &compl_desc->txd;
251 struct dma_async_tx_descriptor *
252 ioat_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
253 unsigned int src_cnt, size_t len, unsigned long flags)
255 return __ioat_prep_xor_lock(chan, NULL, dest, src, src_cnt, len, flags);
258 struct dma_async_tx_descriptor *
259 ioat_prep_xor_val(struct dma_chan *chan, dma_addr_t *src,
260 unsigned int src_cnt, size_t len,
261 enum sum_check_flags *result, unsigned long flags)
263 /* the cleanup routine only sets bits on validate failure, it
264 * does not clear bits on validate success... so clear it here
268 return __ioat_prep_xor_lock(chan, result, src[0], &src[1],
269 src_cnt - 1, len, flags);
273 dump_pq_desc_dbg(struct ioatdma_chan *ioat_chan, struct ioat_ring_ent *desc,
274 struct ioat_ring_ent *ext)
276 struct device *dev = to_dev(ioat_chan);
277 struct ioat_pq_descriptor *pq = desc->pq;
278 struct ioat_pq_ext_descriptor *pq_ex = ext ? ext->pq_ex : NULL;
279 struct ioat_raw_descriptor *descs[] = { (void *) pq, (void *) pq_ex };
280 int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt);
283 dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x"
284 " sz: %#10.8x ctl: %#x (op: %#x int: %d compl: %d pq: '%s%s'"
286 desc_id(desc), (unsigned long long) desc->txd.phys,
287 (unsigned long long) (pq_ex ? pq_ex->next : pq->next),
288 desc->txd.flags, pq->size, pq->ctl, pq->ctl_f.op,
289 pq->ctl_f.int_en, pq->ctl_f.compl_write,
290 pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q",
292 for (i = 0; i < src_cnt; i++)
293 dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i,
294 (unsigned long long) pq_get_src(descs, i), pq->coef[i]);
295 dev_dbg(dev, "\tP: %#llx\n", pq->p_addr);
296 dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr);
297 dev_dbg(dev, "\tNEXT: %#llx\n", pq->next);
300 static void dump_pq16_desc_dbg(struct ioatdma_chan *ioat_chan,
301 struct ioat_ring_ent *desc)
303 struct device *dev = to_dev(ioat_chan);
304 struct ioat_pq_descriptor *pq = desc->pq;
305 struct ioat_raw_descriptor *descs[] = { (void *)pq,
308 int src_cnt = src16_cnt_to_sw(pq->ctl_f.src_cnt);
312 descs[1] = (void *)desc->sed->hw;
313 descs[2] = (void *)desc->sed->hw + 64;
316 dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x"
317 " sz: %#x ctl: %#x (op: %#x int: %d compl: %d pq: '%s%s'"
319 desc_id(desc), (unsigned long long) desc->txd.phys,
320 (unsigned long long) pq->next,
321 desc->txd.flags, pq->size, pq->ctl,
322 pq->ctl_f.op, pq->ctl_f.int_en,
323 pq->ctl_f.compl_write,
324 pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q",
326 for (i = 0; i < src_cnt; i++) {
327 dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i,
328 (unsigned long long) pq16_get_src(descs, i),
331 dev_dbg(dev, "\tP: %#llx\n", pq->p_addr);
332 dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr);
335 static struct dma_async_tx_descriptor *
336 __ioat_prep_pq_lock(struct dma_chan *c, enum sum_check_flags *result,
337 const dma_addr_t *dst, const dma_addr_t *src,
338 unsigned int src_cnt, const unsigned char *scf,
339 size_t len, unsigned long flags)
341 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
342 struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma;
343 struct ioat_ring_ent *compl_desc;
344 struct ioat_ring_ent *desc;
345 struct ioat_ring_ent *ext;
346 size_t total_len = len;
347 struct ioat_pq_descriptor *pq;
348 struct ioat_pq_ext_descriptor *pq_ex = NULL;
349 struct ioat_dma_descriptor *hw;
351 u8 op = result ? IOAT_OP_PQ_VAL : IOAT_OP_PQ;
352 int i, s, idx, with_ext, num_descs;
353 int cb32 = (ioat_dma->version < IOAT_VER_3_3) ? 1 : 0;
355 dev_dbg(to_dev(ioat_chan), "%s\n", __func__);
356 /* the engine requires at least two sources (we provide
357 * at least 1 implied source in the DMA_PREP_CONTINUE case)
359 BUG_ON(src_cnt + dmaf_continue(flags) < 2);
361 num_descs = ioat_xferlen_to_descs(ioat_chan, len);
362 /* we need 2x the number of descriptors to cover greater than 3
363 * sources (we need 1 extra source in the q-only continuation
364 * case and 3 extra sources in the p+q continuation case.
366 if (src_cnt + dmaf_p_disabled_continue(flags) > 3 ||
367 (dmaf_continue(flags) && !dmaf_p_disabled_continue(flags))) {
373 /* completion writes from the raid engine may pass completion
374 * writes from the legacy engine, so we need one extra null
375 * (legacy) descriptor to ensure all completion writes arrive in
378 if (likely(num_descs) &&
379 ioat_check_space_lock(ioat_chan, num_descs + cb32) == 0)
380 idx = ioat_chan->head;
385 struct ioat_raw_descriptor *descs[2];
386 size_t xfer_size = min_t(size_t, len,
387 1 << ioat_chan->xfercap_log);
389 desc = ioat_get_ring_ent(ioat_chan, idx + i);
392 /* save a branch by unconditionally retrieving the
393 * extended descriptor pq_set_src() knows to not write
394 * to it in the single descriptor case
396 ext = ioat_get_ring_ent(ioat_chan, idx + i + with_ext);
399 descs[0] = (struct ioat_raw_descriptor *) pq;
400 descs[1] = (struct ioat_raw_descriptor *) pq_ex;
402 for (s = 0; s < src_cnt; s++)
403 pq_set_src(descs, src[s], offset, scf[s], s);
405 /* see the comment for dma_maxpq in include/linux/dmaengine.h */
406 if (dmaf_p_disabled_continue(flags))
407 pq_set_src(descs, dst[1], offset, 1, s++);
408 else if (dmaf_continue(flags)) {
409 pq_set_src(descs, dst[0], offset, 0, s++);
410 pq_set_src(descs, dst[1], offset, 1, s++);
411 pq_set_src(descs, dst[1], offset, 0, s++);
413 pq->size = xfer_size;
414 pq->p_addr = dst[0] + offset;
415 pq->q_addr = dst[1] + offset;
418 /* we turn on descriptor write back error status */
419 if (ioat_dma->cap & IOAT_CAP_DWBES)
420 pq->ctl_f.wb_en = result ? 1 : 0;
421 pq->ctl_f.src_cnt = src_cnt_to_hw(s);
422 pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P);
423 pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q);
427 } while ((i += 1 + with_ext) < num_descs);
429 /* last pq descriptor carries the unmap parameters and fence bit */
430 desc->txd.flags = flags;
431 desc->len = total_len;
433 desc->result = result;
434 pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
435 dump_pq_desc_dbg(ioat_chan, desc, ext);
438 pq->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
439 pq->ctl_f.compl_write = 1;
442 /* completion descriptor carries interrupt bit */
443 compl_desc = ioat_get_ring_ent(ioat_chan, idx + i);
444 compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT;
448 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
449 hw->ctl_f.compl_write = 1;
450 hw->size = NULL_DESC_BUFFER_SIZE;
451 dump_desc_dbg(ioat_chan, compl_desc);
455 /* we leave the channel locked to ensure in order submission */
456 return &compl_desc->txd;
459 static struct dma_async_tx_descriptor *
460 __ioat_prep_pq16_lock(struct dma_chan *c, enum sum_check_flags *result,
461 const dma_addr_t *dst, const dma_addr_t *src,
462 unsigned int src_cnt, const unsigned char *scf,
463 size_t len, unsigned long flags)
465 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
466 struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma;
467 struct ioat_ring_ent *desc;
468 size_t total_len = len;
469 struct ioat_pq_descriptor *pq;
472 int i, s, idx, num_descs;
474 /* this function is only called with 9-16 sources */
475 op = result ? IOAT_OP_PQ_VAL_16S : IOAT_OP_PQ_16S;
477 dev_dbg(to_dev(ioat_chan), "%s\n", __func__);
479 num_descs = ioat_xferlen_to_descs(ioat_chan, len);
482 * 16 source pq is only available on cb3.3 and has no completion
485 if (num_descs && ioat_check_space_lock(ioat_chan, num_descs) == 0)
486 idx = ioat_chan->head;
493 struct ioat_raw_descriptor *descs[4];
494 size_t xfer_size = min_t(size_t, len,
495 1 << ioat_chan->xfercap_log);
497 desc = ioat_get_ring_ent(ioat_chan, idx + i);
500 descs[0] = (struct ioat_raw_descriptor *) pq;
502 desc->sed = ioat3_alloc_sed(ioat_dma, (src_cnt-2) >> 3);
504 dev_err(to_dev(ioat_chan),
505 "%s: no free sed entries\n", __func__);
509 pq->sed_addr = desc->sed->dma;
510 desc->sed->parent = desc;
512 descs[1] = (struct ioat_raw_descriptor *)desc->sed->hw;
513 descs[2] = (void *)descs[1] + 64;
515 for (s = 0; s < src_cnt; s++)
516 pq16_set_src(descs, src[s], offset, scf[s], s);
518 /* see the comment for dma_maxpq in include/linux/dmaengine.h */
519 if (dmaf_p_disabled_continue(flags))
520 pq16_set_src(descs, dst[1], offset, 1, s++);
521 else if (dmaf_continue(flags)) {
522 pq16_set_src(descs, dst[0], offset, 0, s++);
523 pq16_set_src(descs, dst[1], offset, 1, s++);
524 pq16_set_src(descs, dst[1], offset, 0, s++);
527 pq->size = xfer_size;
528 pq->p_addr = dst[0] + offset;
529 pq->q_addr = dst[1] + offset;
532 pq->ctl_f.src_cnt = src16_cnt_to_hw(s);
533 /* we turn on descriptor write back error status */
534 if (ioat_dma->cap & IOAT_CAP_DWBES)
535 pq->ctl_f.wb_en = result ? 1 : 0;
536 pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P);
537 pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q);
541 } while (++i < num_descs);
543 /* last pq descriptor carries the unmap parameters and fence bit */
544 desc->txd.flags = flags;
545 desc->len = total_len;
547 desc->result = result;
548 pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
550 /* with cb3.3 we should be able to do completion w/o a null desc */
551 pq->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
552 pq->ctl_f.compl_write = 1;
554 dump_pq16_desc_dbg(ioat_chan, desc);
556 /* we leave the channel locked to ensure in order submission */
560 static int src_cnt_flags(unsigned int src_cnt, unsigned long flags)
562 if (dmaf_p_disabled_continue(flags))
564 else if (dmaf_continue(flags))
570 struct dma_async_tx_descriptor *
571 ioat_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
572 unsigned int src_cnt, const unsigned char *scf, size_t len,
575 /* specify valid address for disabled result */
576 if (flags & DMA_PREP_PQ_DISABLE_P)
578 if (flags & DMA_PREP_PQ_DISABLE_Q)
581 /* handle the single source multiply case from the raid6
584 if ((flags & DMA_PREP_PQ_DISABLE_P) && src_cnt == 1) {
585 dma_addr_t single_source[2];
586 unsigned char single_source_coef[2];
588 BUG_ON(flags & DMA_PREP_PQ_DISABLE_Q);
589 single_source[0] = src[0];
590 single_source[1] = src[0];
591 single_source_coef[0] = scf[0];
592 single_source_coef[1] = 0;
594 return src_cnt_flags(src_cnt, flags) > 8 ?
595 __ioat_prep_pq16_lock(chan, NULL, dst, single_source,
596 2, single_source_coef, len,
598 __ioat_prep_pq_lock(chan, NULL, dst, single_source, 2,
599 single_source_coef, len, flags);
602 return src_cnt_flags(src_cnt, flags) > 8 ?
603 __ioat_prep_pq16_lock(chan, NULL, dst, src, src_cnt,
605 __ioat_prep_pq_lock(chan, NULL, dst, src, src_cnt,
610 struct dma_async_tx_descriptor *
611 ioat_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
612 unsigned int src_cnt, const unsigned char *scf, size_t len,
613 enum sum_check_flags *pqres, unsigned long flags)
615 /* specify valid address for disabled result */
616 if (flags & DMA_PREP_PQ_DISABLE_P)
618 if (flags & DMA_PREP_PQ_DISABLE_Q)
621 /* the cleanup routine only sets bits on validate failure, it
622 * does not clear bits on validate success... so clear it here
626 return src_cnt_flags(src_cnt, flags) > 8 ?
627 __ioat_prep_pq16_lock(chan, pqres, pq, src, src_cnt, scf, len,
629 __ioat_prep_pq_lock(chan, pqres, pq, src, src_cnt, scf, len,
633 struct dma_async_tx_descriptor *
634 ioat_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
635 unsigned int src_cnt, size_t len, unsigned long flags)
637 unsigned char scf[src_cnt];
640 memset(scf, 0, src_cnt);
642 flags |= DMA_PREP_PQ_DISABLE_Q;
643 pq[1] = dst; /* specify valid address for disabled result */
645 return src_cnt_flags(src_cnt, flags) > 8 ?
646 __ioat_prep_pq16_lock(chan, NULL, pq, src, src_cnt, scf, len,
648 __ioat_prep_pq_lock(chan, NULL, pq, src, src_cnt, scf, len,
652 struct dma_async_tx_descriptor *
653 ioat_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src,
654 unsigned int src_cnt, size_t len,
655 enum sum_check_flags *result, unsigned long flags)
657 unsigned char scf[src_cnt];
660 /* the cleanup routine only sets bits on validate failure, it
661 * does not clear bits on validate success... so clear it here
665 memset(scf, 0, src_cnt);
667 flags |= DMA_PREP_PQ_DISABLE_Q;
668 pq[1] = pq[0]; /* specify valid address for disabled result */
670 return src_cnt_flags(src_cnt, flags) > 8 ?
671 __ioat_prep_pq16_lock(chan, result, pq, &src[1], src_cnt - 1,
673 __ioat_prep_pq_lock(chan, result, pq, &src[1], src_cnt - 1,
677 struct dma_async_tx_descriptor *
678 ioat_prep_interrupt_lock(struct dma_chan *c, unsigned long flags)
680 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
681 struct ioat_ring_ent *desc;
682 struct ioat_dma_descriptor *hw;
684 if (ioat_check_space_lock(ioat_chan, 1) == 0)
685 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head);
692 hw->ctl_f.int_en = 1;
693 hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
694 hw->ctl_f.compl_write = 1;
695 hw->size = NULL_DESC_BUFFER_SIZE;
699 desc->txd.flags = flags;
702 dump_desc_dbg(ioat_chan, desc);
704 /* we leave the channel locked to ensure in order submission */