2 * offload engine driver for the Intel Xscale series of i/o processors
3 * Copyright © 2006, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21 * This driver supports the asynchrounous DMA copy and RAID engines available
22 * on the Intel Xscale(R) family of I/O Processors (IOP 32x, 33x, 134x)
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/delay.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/spinlock.h>
30 #include <linux/interrupt.h>
31 #include <linux/platform_device.h>
32 #include <linux/memory.h>
33 #include <linux/ioport.h>
35 #include <mach/adma.h>
37 #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common)
38 #define to_iop_adma_device(dev) \
39 container_of(dev, struct iop_adma_device, common)
40 #define tx_to_iop_adma_slot(tx) \
41 container_of(tx, struct iop_adma_desc_slot, async_tx)
44 * iop_adma_free_slots - flags descriptor slots for reuse
46 * Caller must hold &iop_chan->lock while calling this function
48 static void iop_adma_free_slots(struct iop_adma_desc_slot *slot)
50 int stride = slot->slots_per_op;
53 slot->slots_per_op = 0;
54 slot = list_entry(slot->slot_node.next,
55 struct iop_adma_desc_slot,
61 iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc,
62 struct iop_adma_chan *iop_chan, dma_cookie_t cookie)
64 struct dma_async_tx_descriptor *tx = &desc->async_tx;
66 BUG_ON(tx->cookie < 0);
71 /* call the callback (must not sleep or submit new
72 * operations to this channel)
75 tx->callback(tx->callback_param);
77 /* unmap dma addresses
78 * (unmap_single vs unmap_page?)
80 if (desc->group_head && desc->unmap_len) {
81 struct iop_adma_desc_slot *unmap = desc->group_head;
83 &iop_chan->device->pdev->dev;
84 u32 len = unmap->unmap_len;
85 enum dma_ctrl_flags flags = tx->flags;
90 src_cnt = unmap->unmap_src_cnt;
91 dest = iop_desc_get_dest_addr(unmap, iop_chan);
92 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
93 enum dma_data_direction dir;
95 if (src_cnt > 1) /* is xor? */
96 dir = DMA_BIDIRECTIONAL;
98 dir = DMA_FROM_DEVICE;
100 dma_unmap_page(dev, dest, len, dir);
103 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
105 addr = iop_desc_get_src_addr(unmap,
110 dma_unmap_page(dev, addr, len,
114 desc->group_head = NULL;
118 /* run dependent operations */
119 dma_run_dependencies(tx);
125 iop_adma_clean_slot(struct iop_adma_desc_slot *desc,
126 struct iop_adma_chan *iop_chan)
128 /* the client is allowed to attach dependent operations
131 if (!async_tx_test_ack(&desc->async_tx))
134 /* leave the last descriptor in the chain
135 * so we can append to it
137 if (desc->chain_node.next == &iop_chan->chain)
140 dev_dbg(iop_chan->device->common.dev,
141 "\tfree slot: %d slots_per_op: %d\n",
142 desc->idx, desc->slots_per_op);
144 list_del(&desc->chain_node);
145 iop_adma_free_slots(desc);
150 static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
152 struct iop_adma_desc_slot *iter, *_iter, *grp_start = NULL;
153 dma_cookie_t cookie = 0;
154 u32 current_desc = iop_chan_get_current_descriptor(iop_chan);
155 int busy = iop_chan_is_busy(iop_chan);
156 int seen_current = 0, slot_cnt = 0, slots_per_op = 0;
158 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
159 /* free completed slots from the chain starting with
160 * the oldest descriptor
162 list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
164 pr_debug("\tcookie: %d slot: %d busy: %d "
165 "this_desc: %#x next_desc: %#x ack: %d\n",
166 iter->async_tx.cookie, iter->idx, busy,
167 iter->async_tx.phys, iop_desc_get_next_desc(iter),
168 async_tx_test_ack(&iter->async_tx));
170 prefetch(&_iter->async_tx);
172 /* do not advance past the current descriptor loaded into the
173 * hardware channel, subsequent descriptors are either in
174 * process or have not been submitted
179 /* stop the search if we reach the current descriptor and the
180 * channel is busy, or if it appears that the current descriptor
181 * needs to be re-read (i.e. has been appended to)
183 if (iter->async_tx.phys == current_desc) {
184 BUG_ON(seen_current++);
185 if (busy || iop_desc_get_next_desc(iter))
189 /* detect the start of a group transaction */
190 if (!slot_cnt && !slots_per_op) {
191 slot_cnt = iter->slot_cnt;
192 slots_per_op = iter->slots_per_op;
193 if (slot_cnt <= slots_per_op) {
200 pr_debug("\tgroup++\n");
203 slot_cnt -= slots_per_op;
206 /* all the members of a group are complete */
207 if (slots_per_op != 0 && slot_cnt == 0) {
208 struct iop_adma_desc_slot *grp_iter, *_grp_iter;
209 int end_of_chain = 0;
210 pr_debug("\tgroup end\n");
212 /* collect the total results */
213 if (grp_start->xor_check_result) {
214 u32 zero_sum_result = 0;
215 slot_cnt = grp_start->slot_cnt;
216 grp_iter = grp_start;
218 list_for_each_entry_from(grp_iter,
219 &iop_chan->chain, chain_node) {
221 iop_desc_get_zero_result(grp_iter);
222 pr_debug("\titer%d result: %d\n",
223 grp_iter->idx, zero_sum_result);
224 slot_cnt -= slots_per_op;
228 pr_debug("\tgrp_start->xor_check_result: %p\n",
229 grp_start->xor_check_result);
230 *grp_start->xor_check_result = zero_sum_result;
233 /* clean up the group */
234 slot_cnt = grp_start->slot_cnt;
235 grp_iter = grp_start;
236 list_for_each_entry_safe_from(grp_iter, _grp_iter,
237 &iop_chan->chain, chain_node) {
238 cookie = iop_adma_run_tx_complete_actions(
239 grp_iter, iop_chan, cookie);
241 slot_cnt -= slots_per_op;
242 end_of_chain = iop_adma_clean_slot(grp_iter,
245 if (slot_cnt == 0 || end_of_chain)
249 /* the group should be complete at this point */
258 } else if (slots_per_op) /* wait for group completion */
261 /* write back zero sum results (single descriptor case) */
262 if (iter->xor_check_result && iter->async_tx.cookie)
263 *iter->xor_check_result =
264 iop_desc_get_zero_result(iter);
266 cookie = iop_adma_run_tx_complete_actions(
267 iter, iop_chan, cookie);
269 if (iop_adma_clean_slot(iter, iop_chan))
274 iop_chan->completed_cookie = cookie;
275 pr_debug("\tcompleted cookie %d\n", cookie);
280 iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
282 spin_lock_bh(&iop_chan->lock);
283 __iop_adma_slot_cleanup(iop_chan);
284 spin_unlock_bh(&iop_chan->lock);
287 static void iop_adma_tasklet(unsigned long data)
289 struct iop_adma_chan *iop_chan = (struct iop_adma_chan *) data;
291 /* lockdep will flag depedency submissions as potentially
292 * recursive locking, this is not the case as a dependency
293 * submission will never recurse a channels submit routine.
294 * There are checks in async_tx.c to prevent this.
296 spin_lock_nested(&iop_chan->lock, SINGLE_DEPTH_NESTING);
297 __iop_adma_slot_cleanup(iop_chan);
298 spin_unlock(&iop_chan->lock);
301 static struct iop_adma_desc_slot *
302 iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots,
305 struct iop_adma_desc_slot *iter, *_iter, *alloc_start = NULL;
307 int slots_found, retry = 0;
309 /* start search from the last allocated descrtiptor
310 * if a contiguous allocation can not be found start searching
311 * from the beginning of the list
316 iter = iop_chan->last_used;
318 iter = list_entry(&iop_chan->all_slots,
319 struct iop_adma_desc_slot,
322 list_for_each_entry_safe_continue(
323 iter, _iter, &iop_chan->all_slots, slot_node) {
325 prefetch(&_iter->async_tx);
326 if (iter->slots_per_op) {
327 /* give up after finding the first busy slot
328 * on the second pass through the list
337 /* start the allocation if the slot is correctly aligned */
338 if (!slots_found++) {
339 if (iop_desc_is_aligned(iter, slots_per_op))
347 if (slots_found == num_slots) {
348 struct iop_adma_desc_slot *alloc_tail = NULL;
349 struct iop_adma_desc_slot *last_used = NULL;
353 dev_dbg(iop_chan->device->common.dev,
354 "allocated slot: %d "
355 "(desc %p phys: %#x) slots_per_op %d\n",
356 iter->idx, iter->hw_desc,
357 iter->async_tx.phys, slots_per_op);
359 /* pre-ack all but the last descriptor */
360 if (num_slots != slots_per_op)
361 async_tx_ack(&iter->async_tx);
363 list_add_tail(&iter->chain_node, &chain);
365 iter->async_tx.cookie = 0;
366 iter->slot_cnt = num_slots;
367 iter->xor_check_result = NULL;
368 for (i = 0; i < slots_per_op; i++) {
369 iter->slots_per_op = slots_per_op - i;
371 iter = list_entry(iter->slot_node.next,
372 struct iop_adma_desc_slot,
375 num_slots -= slots_per_op;
377 alloc_tail->group_head = alloc_start;
378 alloc_tail->async_tx.cookie = -EBUSY;
379 list_splice(&chain, &alloc_tail->async_tx.tx_list);
380 iop_chan->last_used = last_used;
381 iop_desc_clear_next_desc(alloc_start);
382 iop_desc_clear_next_desc(alloc_tail);
389 /* perform direct reclaim if the allocation fails */
390 __iop_adma_slot_cleanup(iop_chan);
396 iop_desc_assign_cookie(struct iop_adma_chan *iop_chan,
397 struct iop_adma_desc_slot *desc)
399 dma_cookie_t cookie = iop_chan->common.cookie;
403 iop_chan->common.cookie = desc->async_tx.cookie = cookie;
407 static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan)
409 dev_dbg(iop_chan->device->common.dev, "pending: %d\n",
412 if (iop_chan->pending >= IOP_ADMA_THRESHOLD) {
413 iop_chan->pending = 0;
414 iop_chan_append(iop_chan);
419 iop_adma_tx_submit(struct dma_async_tx_descriptor *tx)
421 struct iop_adma_desc_slot *sw_desc = tx_to_iop_adma_slot(tx);
422 struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan);
423 struct iop_adma_desc_slot *grp_start, *old_chain_tail;
429 grp_start = sw_desc->group_head;
430 slot_cnt = grp_start->slot_cnt;
431 slots_per_op = grp_start->slots_per_op;
433 spin_lock_bh(&iop_chan->lock);
434 cookie = iop_desc_assign_cookie(iop_chan, sw_desc);
436 old_chain_tail = list_entry(iop_chan->chain.prev,
437 struct iop_adma_desc_slot, chain_node);
438 list_splice_init(&sw_desc->async_tx.tx_list,
439 &old_chain_tail->chain_node);
441 /* fix up the hardware chain */
442 next_dma = grp_start->async_tx.phys;
443 iop_desc_set_next_desc(old_chain_tail, next_dma);
444 BUG_ON(iop_desc_get_next_desc(old_chain_tail) != next_dma); /* flush */
446 /* check for pre-chained descriptors */
447 iop_paranoia(iop_desc_get_next_desc(sw_desc));
449 /* increment the pending count by the number of slots
450 * memcpy operations have a 1:1 (slot:operation) relation
451 * other operations are heavier and will pop the threshold
454 iop_chan->pending += slot_cnt;
455 iop_adma_check_threshold(iop_chan);
456 spin_unlock_bh(&iop_chan->lock);
458 dev_dbg(iop_chan->device->common.dev, "%s cookie: %d slot: %d\n",
459 __func__, sw_desc->async_tx.cookie, sw_desc->idx);
464 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan);
465 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan);
468 * iop_adma_alloc_chan_resources - returns the number of allocated descriptors
469 * @chan - allocate descriptor resources for this channel
470 * @client - current client requesting the channel be ready for requests
472 * Note: We keep the slots for 1 operation on iop_chan->chain at all times. To
473 * avoid deadlock, via async_xor, num_descs_in_pool must at a minimum be
474 * greater than 2x the number slots needed to satisfy a device->max_xor
477 static int iop_adma_alloc_chan_resources(struct dma_chan *chan)
481 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
482 struct iop_adma_desc_slot *slot = NULL;
483 int init = iop_chan->slots_allocated ? 0 : 1;
484 struct iop_adma_platform_data *plat_data =
485 iop_chan->device->pdev->dev.platform_data;
486 int num_descs_in_pool = plat_data->pool_size/IOP_ADMA_SLOT_SIZE;
488 /* Allocate descriptor slots */
490 idx = iop_chan->slots_allocated;
491 if (idx == num_descs_in_pool)
494 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
496 printk(KERN_INFO "IOP ADMA Channel only initialized"
497 " %d descriptor slots", idx);
500 hw_desc = (char *) iop_chan->device->dma_desc_pool_virt;
501 slot->hw_desc = (void *) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
503 dma_async_tx_descriptor_init(&slot->async_tx, chan);
504 slot->async_tx.tx_submit = iop_adma_tx_submit;
505 INIT_LIST_HEAD(&slot->chain_node);
506 INIT_LIST_HEAD(&slot->slot_node);
507 hw_desc = (char *) iop_chan->device->dma_desc_pool;
508 slot->async_tx.phys =
509 (dma_addr_t) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
512 spin_lock_bh(&iop_chan->lock);
513 iop_chan->slots_allocated++;
514 list_add_tail(&slot->slot_node, &iop_chan->all_slots);
515 spin_unlock_bh(&iop_chan->lock);
516 } while (iop_chan->slots_allocated < num_descs_in_pool);
518 if (idx && !iop_chan->last_used)
519 iop_chan->last_used = list_entry(iop_chan->all_slots.next,
520 struct iop_adma_desc_slot,
523 dev_dbg(iop_chan->device->common.dev,
524 "allocated %d descriptor slots last_used: %p\n",
525 iop_chan->slots_allocated, iop_chan->last_used);
527 /* initialize the channel and the chain with a null operation */
529 if (dma_has_cap(DMA_MEMCPY,
530 iop_chan->device->common.cap_mask))
531 iop_chan_start_null_memcpy(iop_chan);
532 else if (dma_has_cap(DMA_XOR,
533 iop_chan->device->common.cap_mask))
534 iop_chan_start_null_xor(iop_chan);
539 return (idx > 0) ? idx : -ENOMEM;
542 static struct dma_async_tx_descriptor *
543 iop_adma_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
545 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
546 struct iop_adma_desc_slot *sw_desc, *grp_start;
547 int slot_cnt, slots_per_op;
549 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
551 spin_lock_bh(&iop_chan->lock);
552 slot_cnt = iop_chan_interrupt_slot_count(&slots_per_op, iop_chan);
553 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
555 grp_start = sw_desc->group_head;
556 iop_desc_init_interrupt(grp_start, iop_chan);
557 grp_start->unmap_len = 0;
558 sw_desc->async_tx.flags = flags;
560 spin_unlock_bh(&iop_chan->lock);
562 return sw_desc ? &sw_desc->async_tx : NULL;
565 static struct dma_async_tx_descriptor *
566 iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest,
567 dma_addr_t dma_src, size_t len, unsigned long flags)
569 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
570 struct iop_adma_desc_slot *sw_desc, *grp_start;
571 int slot_cnt, slots_per_op;
575 BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
577 dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
580 spin_lock_bh(&iop_chan->lock);
581 slot_cnt = iop_chan_memcpy_slot_count(len, &slots_per_op);
582 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
584 grp_start = sw_desc->group_head;
585 iop_desc_init_memcpy(grp_start, flags);
586 iop_desc_set_byte_count(grp_start, iop_chan, len);
587 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
588 iop_desc_set_memcpy_src_addr(grp_start, dma_src);
589 sw_desc->unmap_src_cnt = 1;
590 sw_desc->unmap_len = len;
591 sw_desc->async_tx.flags = flags;
593 spin_unlock_bh(&iop_chan->lock);
595 return sw_desc ? &sw_desc->async_tx : NULL;
598 static struct dma_async_tx_descriptor *
599 iop_adma_prep_dma_memset(struct dma_chan *chan, dma_addr_t dma_dest,
600 int value, size_t len, unsigned long flags)
602 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
603 struct iop_adma_desc_slot *sw_desc, *grp_start;
604 int slot_cnt, slots_per_op;
608 BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
610 dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
613 spin_lock_bh(&iop_chan->lock);
614 slot_cnt = iop_chan_memset_slot_count(len, &slots_per_op);
615 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
617 grp_start = sw_desc->group_head;
618 iop_desc_init_memset(grp_start, flags);
619 iop_desc_set_byte_count(grp_start, iop_chan, len);
620 iop_desc_set_block_fill_val(grp_start, value);
621 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
622 sw_desc->unmap_src_cnt = 1;
623 sw_desc->unmap_len = len;
624 sw_desc->async_tx.flags = flags;
626 spin_unlock_bh(&iop_chan->lock);
628 return sw_desc ? &sw_desc->async_tx : NULL;
631 static struct dma_async_tx_descriptor *
632 iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest,
633 dma_addr_t *dma_src, unsigned int src_cnt, size_t len,
636 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
637 struct iop_adma_desc_slot *sw_desc, *grp_start;
638 int slot_cnt, slots_per_op;
642 BUG_ON(unlikely(len > IOP_ADMA_XOR_MAX_BYTE_COUNT));
644 dev_dbg(iop_chan->device->common.dev,
645 "%s src_cnt: %d len: %u flags: %lx\n",
646 __func__, src_cnt, len, flags);
648 spin_lock_bh(&iop_chan->lock);
649 slot_cnt = iop_chan_xor_slot_count(len, src_cnt, &slots_per_op);
650 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
652 grp_start = sw_desc->group_head;
653 iop_desc_init_xor(grp_start, src_cnt, flags);
654 iop_desc_set_byte_count(grp_start, iop_chan, len);
655 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
656 sw_desc->unmap_src_cnt = src_cnt;
657 sw_desc->unmap_len = len;
658 sw_desc->async_tx.flags = flags;
660 iop_desc_set_xor_src_addr(grp_start, src_cnt,
663 spin_unlock_bh(&iop_chan->lock);
665 return sw_desc ? &sw_desc->async_tx : NULL;
668 static struct dma_async_tx_descriptor *
669 iop_adma_prep_dma_xor_val(struct dma_chan *chan, dma_addr_t *dma_src,
670 unsigned int src_cnt, size_t len, u32 *result,
673 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
674 struct iop_adma_desc_slot *sw_desc, *grp_start;
675 int slot_cnt, slots_per_op;
680 dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n",
681 __func__, src_cnt, len);
683 spin_lock_bh(&iop_chan->lock);
684 slot_cnt = iop_chan_zero_sum_slot_count(len, src_cnt, &slots_per_op);
685 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
687 grp_start = sw_desc->group_head;
688 iop_desc_init_zero_sum(grp_start, src_cnt, flags);
689 iop_desc_set_zero_sum_byte_count(grp_start, len);
690 grp_start->xor_check_result = result;
691 pr_debug("\t%s: grp_start->xor_check_result: %p\n",
692 __func__, grp_start->xor_check_result);
693 sw_desc->unmap_src_cnt = src_cnt;
694 sw_desc->unmap_len = len;
695 sw_desc->async_tx.flags = flags;
697 iop_desc_set_zero_sum_src_addr(grp_start, src_cnt,
700 spin_unlock_bh(&iop_chan->lock);
702 return sw_desc ? &sw_desc->async_tx : NULL;
705 static void iop_adma_free_chan_resources(struct dma_chan *chan)
707 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
708 struct iop_adma_desc_slot *iter, *_iter;
709 int in_use_descs = 0;
711 iop_adma_slot_cleanup(iop_chan);
713 spin_lock_bh(&iop_chan->lock);
714 list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
717 list_del(&iter->chain_node);
719 list_for_each_entry_safe_reverse(
720 iter, _iter, &iop_chan->all_slots, slot_node) {
721 list_del(&iter->slot_node);
723 iop_chan->slots_allocated--;
725 iop_chan->last_used = NULL;
727 dev_dbg(iop_chan->device->common.dev, "%s slots_allocated %d\n",
728 __func__, iop_chan->slots_allocated);
729 spin_unlock_bh(&iop_chan->lock);
731 /* one is ok since we left it on there on purpose */
732 if (in_use_descs > 1)
733 printk(KERN_ERR "IOP: Freeing %d in use descriptors!\n",
738 * iop_adma_is_complete - poll the status of an ADMA transaction
739 * @chan: ADMA channel handle
740 * @cookie: ADMA transaction identifier
742 static enum dma_status iop_adma_is_complete(struct dma_chan *chan,
747 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
748 dma_cookie_t last_used;
749 dma_cookie_t last_complete;
752 last_used = chan->cookie;
753 last_complete = iop_chan->completed_cookie;
756 *done = last_complete;
760 ret = dma_async_is_complete(cookie, last_complete, last_used);
761 if (ret == DMA_SUCCESS)
764 iop_adma_slot_cleanup(iop_chan);
766 last_used = chan->cookie;
767 last_complete = iop_chan->completed_cookie;
770 *done = last_complete;
774 return dma_async_is_complete(cookie, last_complete, last_used);
777 static irqreturn_t iop_adma_eot_handler(int irq, void *data)
779 struct iop_adma_chan *chan = data;
781 dev_dbg(chan->device->common.dev, "%s\n", __func__);
783 tasklet_schedule(&chan->irq_tasklet);
785 iop_adma_device_clear_eot_status(chan);
790 static irqreturn_t iop_adma_eoc_handler(int irq, void *data)
792 struct iop_adma_chan *chan = data;
794 dev_dbg(chan->device->common.dev, "%s\n", __func__);
796 tasklet_schedule(&chan->irq_tasklet);
798 iop_adma_device_clear_eoc_status(chan);
803 static irqreturn_t iop_adma_err_handler(int irq, void *data)
805 struct iop_adma_chan *chan = data;
806 unsigned long status = iop_chan_get_status(chan);
808 dev_printk(KERN_ERR, chan->device->common.dev,
809 "error ( %s%s%s%s%s%s%s)\n",
810 iop_is_err_int_parity(status, chan) ? "int_parity " : "",
811 iop_is_err_mcu_abort(status, chan) ? "mcu_abort " : "",
812 iop_is_err_int_tabort(status, chan) ? "int_tabort " : "",
813 iop_is_err_int_mabort(status, chan) ? "int_mabort " : "",
814 iop_is_err_pci_tabort(status, chan) ? "pci_tabort " : "",
815 iop_is_err_pci_mabort(status, chan) ? "pci_mabort " : "",
816 iop_is_err_split_tx(status, chan) ? "split_tx " : "");
818 iop_adma_device_clear_err_status(chan);
825 static void iop_adma_issue_pending(struct dma_chan *chan)
827 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
829 if (iop_chan->pending) {
830 iop_chan->pending = 0;
831 iop_chan_append(iop_chan);
836 * Perform a transaction to verify the HW works.
838 #define IOP_ADMA_TEST_SIZE 2000
840 static int __devinit iop_adma_memcpy_self_test(struct iop_adma_device *device)
844 dma_addr_t src_dma, dest_dma;
845 struct dma_chan *dma_chan;
847 struct dma_async_tx_descriptor *tx;
849 struct iop_adma_chan *iop_chan;
851 dev_dbg(device->common.dev, "%s\n", __func__);
853 src = kmalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
856 dest = kzalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
862 /* Fill in src buffer */
863 for (i = 0; i < IOP_ADMA_TEST_SIZE; i++)
864 ((u8 *) src)[i] = (u8)i;
866 /* Start copy, using first DMA channel */
867 dma_chan = container_of(device->common.channels.next,
870 if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
875 dest_dma = dma_map_single(dma_chan->device->dev, dest,
876 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
877 src_dma = dma_map_single(dma_chan->device->dev, src,
878 IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE);
879 tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
881 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
883 cookie = iop_adma_tx_submit(tx);
884 iop_adma_issue_pending(dma_chan);
887 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
889 dev_printk(KERN_ERR, dma_chan->device->dev,
890 "Self-test copy timed out, disabling\n");
895 iop_chan = to_iop_adma_chan(dma_chan);
896 dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
897 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
898 if (memcmp(src, dest, IOP_ADMA_TEST_SIZE)) {
899 dev_printk(KERN_ERR, dma_chan->device->dev,
900 "Self-test copy failed compare, disabling\n");
906 iop_adma_free_chan_resources(dma_chan);
913 #define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */
915 iop_adma_xor_val_self_test(struct iop_adma_device *device)
919 struct page *xor_srcs[IOP_ADMA_NUM_SRC_TEST];
920 struct page *zero_sum_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
921 dma_addr_t dma_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
922 dma_addr_t dma_addr, dest_dma;
923 struct dma_async_tx_descriptor *tx;
924 struct dma_chan *dma_chan;
930 struct iop_adma_chan *iop_chan;
932 dev_dbg(device->common.dev, "%s\n", __func__);
934 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
935 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
936 if (!xor_srcs[src_idx]) {
938 __free_page(xor_srcs[src_idx]);
943 dest = alloc_page(GFP_KERNEL);
946 __free_page(xor_srcs[src_idx]);
950 /* Fill in src buffers */
951 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
952 u8 *ptr = page_address(xor_srcs[src_idx]);
953 for (i = 0; i < PAGE_SIZE; i++)
954 ptr[i] = (1 << src_idx);
957 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++)
958 cmp_byte ^= (u8) (1 << src_idx);
960 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
961 (cmp_byte << 8) | cmp_byte;
963 memset(page_address(dest), 0, PAGE_SIZE);
965 dma_chan = container_of(device->common.channels.next,
968 if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
974 dest_dma = dma_map_page(dma_chan->device->dev, dest, 0,
975 PAGE_SIZE, DMA_FROM_DEVICE);
976 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
977 dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
978 0, PAGE_SIZE, DMA_TO_DEVICE);
979 tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
980 IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE,
981 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
983 cookie = iop_adma_tx_submit(tx);
984 iop_adma_issue_pending(dma_chan);
987 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
989 dev_printk(KERN_ERR, dma_chan->device->dev,
990 "Self-test xor timed out, disabling\n");
995 iop_chan = to_iop_adma_chan(dma_chan);
996 dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
997 PAGE_SIZE, DMA_FROM_DEVICE);
998 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
999 u32 *ptr = page_address(dest);
1000 if (ptr[i] != cmp_word) {
1001 dev_printk(KERN_ERR, dma_chan->device->dev,
1002 "Self-test xor failed compare, disabling\n");
1004 goto free_resources;
1007 dma_sync_single_for_device(&iop_chan->device->pdev->dev, dest_dma,
1008 PAGE_SIZE, DMA_TO_DEVICE);
1010 /* skip zero sum if the capability is not present */
1011 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask))
1012 goto free_resources;
1014 /* zero sum the sources with the destintation page */
1015 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
1016 zero_sum_srcs[i] = xor_srcs[i];
1017 zero_sum_srcs[i] = dest;
1019 zero_sum_result = 1;
1021 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1022 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1023 zero_sum_srcs[i], 0, PAGE_SIZE,
1025 tx = iop_adma_prep_dma_xor_val(dma_chan, dma_srcs,
1026 IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1028 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1030 cookie = iop_adma_tx_submit(tx);
1031 iop_adma_issue_pending(dma_chan);
1034 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1035 dev_printk(KERN_ERR, dma_chan->device->dev,
1036 "Self-test zero sum timed out, disabling\n");
1038 goto free_resources;
1041 if (zero_sum_result != 0) {
1042 dev_printk(KERN_ERR, dma_chan->device->dev,
1043 "Self-test zero sum failed compare, disabling\n");
1045 goto free_resources;
1049 dma_addr = dma_map_page(dma_chan->device->dev, dest, 0,
1050 PAGE_SIZE, DMA_FROM_DEVICE);
1051 tx = iop_adma_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE,
1052 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1054 cookie = iop_adma_tx_submit(tx);
1055 iop_adma_issue_pending(dma_chan);
1058 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1059 dev_printk(KERN_ERR, dma_chan->device->dev,
1060 "Self-test memset timed out, disabling\n");
1062 goto free_resources;
1065 for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) {
1066 u32 *ptr = page_address(dest);
1068 dev_printk(KERN_ERR, dma_chan->device->dev,
1069 "Self-test memset failed compare, disabling\n");
1071 goto free_resources;
1075 /* test for non-zero parity sum */
1076 zero_sum_result = 0;
1077 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1078 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1079 zero_sum_srcs[i], 0, PAGE_SIZE,
1081 tx = iop_adma_prep_dma_xor_val(dma_chan, dma_srcs,
1082 IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1084 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1086 cookie = iop_adma_tx_submit(tx);
1087 iop_adma_issue_pending(dma_chan);
1090 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1091 dev_printk(KERN_ERR, dma_chan->device->dev,
1092 "Self-test non-zero sum timed out, disabling\n");
1094 goto free_resources;
1097 if (zero_sum_result != 1) {
1098 dev_printk(KERN_ERR, dma_chan->device->dev,
1099 "Self-test non-zero sum failed compare, disabling\n");
1101 goto free_resources;
1105 iop_adma_free_chan_resources(dma_chan);
1107 src_idx = IOP_ADMA_NUM_SRC_TEST;
1109 __free_page(xor_srcs[src_idx]);
1114 static int __devexit iop_adma_remove(struct platform_device *dev)
1116 struct iop_adma_device *device = platform_get_drvdata(dev);
1117 struct dma_chan *chan, *_chan;
1118 struct iop_adma_chan *iop_chan;
1119 struct iop_adma_platform_data *plat_data = dev->dev.platform_data;
1121 dma_async_device_unregister(&device->common);
1123 dma_free_coherent(&dev->dev, plat_data->pool_size,
1124 device->dma_desc_pool_virt, device->dma_desc_pool);
1126 list_for_each_entry_safe(chan, _chan, &device->common.channels,
1128 iop_chan = to_iop_adma_chan(chan);
1129 list_del(&chan->device_node);
1137 static int __devinit iop_adma_probe(struct platform_device *pdev)
1139 struct resource *res;
1141 struct iop_adma_device *adev;
1142 struct iop_adma_chan *iop_chan;
1143 struct dma_device *dma_dev;
1144 struct iop_adma_platform_data *plat_data = pdev->dev.platform_data;
1146 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1150 if (!devm_request_mem_region(&pdev->dev, res->start,
1151 res->end - res->start, pdev->name))
1154 adev = kzalloc(sizeof(*adev), GFP_KERNEL);
1157 dma_dev = &adev->common;
1159 /* allocate coherent memory for hardware descriptors
1160 * note: writecombine gives slightly better performance, but
1161 * requires that we explicitly flush the writes
1163 if ((adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev,
1164 plat_data->pool_size,
1165 &adev->dma_desc_pool,
1166 GFP_KERNEL)) == NULL) {
1171 dev_dbg(&pdev->dev, "%s: allocted descriptor pool virt %p phys %p\n",
1172 __func__, adev->dma_desc_pool_virt,
1173 (void *) adev->dma_desc_pool);
1175 adev->id = plat_data->hw_id;
1177 /* discover transaction capabilites from the platform data */
1178 dma_dev->cap_mask = plat_data->cap_mask;
1181 platform_set_drvdata(pdev, adev);
1183 INIT_LIST_HEAD(&dma_dev->channels);
1185 /* set base routines */
1186 dma_dev->device_alloc_chan_resources = iop_adma_alloc_chan_resources;
1187 dma_dev->device_free_chan_resources = iop_adma_free_chan_resources;
1188 dma_dev->device_is_tx_complete = iop_adma_is_complete;
1189 dma_dev->device_issue_pending = iop_adma_issue_pending;
1190 dma_dev->dev = &pdev->dev;
1192 /* set prep routines based on capability */
1193 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1194 dma_dev->device_prep_dma_memcpy = iop_adma_prep_dma_memcpy;
1195 if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask))
1196 dma_dev->device_prep_dma_memset = iop_adma_prep_dma_memset;
1197 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1198 dma_dev->max_xor = iop_adma_get_max_xor();
1199 dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor;
1201 if (dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask))
1202 dma_dev->device_prep_dma_xor_val =
1203 iop_adma_prep_dma_xor_val;
1204 if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
1205 dma_dev->device_prep_dma_interrupt =
1206 iop_adma_prep_dma_interrupt;
1208 iop_chan = kzalloc(sizeof(*iop_chan), GFP_KERNEL);
1213 iop_chan->device = adev;
1215 iop_chan->mmr_base = devm_ioremap(&pdev->dev, res->start,
1216 res->end - res->start);
1217 if (!iop_chan->mmr_base) {
1219 goto err_free_iop_chan;
1221 tasklet_init(&iop_chan->irq_tasklet, iop_adma_tasklet, (unsigned long)
1224 /* clear errors before enabling interrupts */
1225 iop_adma_device_clear_err_status(iop_chan);
1227 for (i = 0; i < 3; i++) {
1228 irq_handler_t handler[] = { iop_adma_eot_handler,
1229 iop_adma_eoc_handler,
1230 iop_adma_err_handler };
1231 int irq = platform_get_irq(pdev, i);
1234 goto err_free_iop_chan;
1236 ret = devm_request_irq(&pdev->dev, irq,
1237 handler[i], 0, pdev->name, iop_chan);
1239 goto err_free_iop_chan;
1243 spin_lock_init(&iop_chan->lock);
1244 INIT_LIST_HEAD(&iop_chan->chain);
1245 INIT_LIST_HEAD(&iop_chan->all_slots);
1246 iop_chan->common.device = dma_dev;
1247 list_add_tail(&iop_chan->common.device_node, &dma_dev->channels);
1249 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1250 ret = iop_adma_memcpy_self_test(adev);
1251 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1253 goto err_free_iop_chan;
1256 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask) ||
1257 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
1258 ret = iop_adma_xor_val_self_test(adev);
1259 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1261 goto err_free_iop_chan;
1264 dev_printk(KERN_INFO, &pdev->dev, "Intel(R) IOP: "
1265 "( %s%s%s%s%s%s%s%s%s%s)\n",
1266 dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "pq " : "",
1267 dma_has_cap(DMA_PQ_UPDATE, dma_dev->cap_mask) ? "pq_update " : "",
1268 dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask) ? "pq_val " : "",
1269 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1270 dma_has_cap(DMA_DUAL_XOR, dma_dev->cap_mask) ? "dual_xor " : "",
1271 dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask) ? "xor_val " : "",
1272 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask) ? "fill " : "",
1273 dma_has_cap(DMA_MEMCPY_CRC32C, dma_dev->cap_mask) ? "cpy+crc " : "",
1274 dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1275 dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1277 dma_async_device_register(dma_dev);
1283 dma_free_coherent(&adev->pdev->dev, plat_data->pool_size,
1284 adev->dma_desc_pool_virt, adev->dma_desc_pool);
1291 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan)
1293 struct iop_adma_desc_slot *sw_desc, *grp_start;
1294 dma_cookie_t cookie;
1295 int slot_cnt, slots_per_op;
1297 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1299 spin_lock_bh(&iop_chan->lock);
1300 slot_cnt = iop_chan_memcpy_slot_count(0, &slots_per_op);
1301 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1303 grp_start = sw_desc->group_head;
1305 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1306 async_tx_ack(&sw_desc->async_tx);
1307 iop_desc_init_memcpy(grp_start, 0);
1308 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1309 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1310 iop_desc_set_memcpy_src_addr(grp_start, 0);
1312 cookie = iop_chan->common.cookie;
1317 /* initialize the completed cookie to be less than
1318 * the most recently used cookie
1320 iop_chan->completed_cookie = cookie - 1;
1321 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1323 /* channel should not be busy */
1324 BUG_ON(iop_chan_is_busy(iop_chan));
1326 /* clear any prior error-status bits */
1327 iop_adma_device_clear_err_status(iop_chan);
1329 /* disable operation */
1330 iop_chan_disable(iop_chan);
1332 /* set the descriptor address */
1333 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1335 /* 1/ don't add pre-chained descriptors
1336 * 2/ dummy read to flush next_desc write
1338 BUG_ON(iop_desc_get_next_desc(sw_desc));
1340 /* run the descriptor */
1341 iop_chan_enable(iop_chan);
1343 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1344 "failed to allocate null descriptor\n");
1345 spin_unlock_bh(&iop_chan->lock);
1348 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan)
1350 struct iop_adma_desc_slot *sw_desc, *grp_start;
1351 dma_cookie_t cookie;
1352 int slot_cnt, slots_per_op;
1354 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1356 spin_lock_bh(&iop_chan->lock);
1357 slot_cnt = iop_chan_xor_slot_count(0, 2, &slots_per_op);
1358 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1360 grp_start = sw_desc->group_head;
1361 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1362 async_tx_ack(&sw_desc->async_tx);
1363 iop_desc_init_null_xor(grp_start, 2, 0);
1364 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1365 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1366 iop_desc_set_xor_src_addr(grp_start, 0, 0);
1367 iop_desc_set_xor_src_addr(grp_start, 1, 0);
1369 cookie = iop_chan->common.cookie;
1374 /* initialize the completed cookie to be less than
1375 * the most recently used cookie
1377 iop_chan->completed_cookie = cookie - 1;
1378 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1380 /* channel should not be busy */
1381 BUG_ON(iop_chan_is_busy(iop_chan));
1383 /* clear any prior error-status bits */
1384 iop_adma_device_clear_err_status(iop_chan);
1386 /* disable operation */
1387 iop_chan_disable(iop_chan);
1389 /* set the descriptor address */
1390 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1392 /* 1/ don't add pre-chained descriptors
1393 * 2/ dummy read to flush next_desc write
1395 BUG_ON(iop_desc_get_next_desc(sw_desc));
1397 /* run the descriptor */
1398 iop_chan_enable(iop_chan);
1400 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1401 "failed to allocate null descriptor\n");
1402 spin_unlock_bh(&iop_chan->lock);
1405 MODULE_ALIAS("platform:iop-adma");
1407 static struct platform_driver iop_adma_driver = {
1408 .probe = iop_adma_probe,
1409 .remove = __devexit_p(iop_adma_remove),
1411 .owner = THIS_MODULE,
1416 static int __init iop_adma_init (void)
1418 return platform_driver_register(&iop_adma_driver);
1421 static void __exit iop_adma_exit (void)
1423 platform_driver_unregister(&iop_adma_driver);
1426 module_exit(iop_adma_exit);
1427 module_init(iop_adma_init);
1429 MODULE_AUTHOR("Intel Corporation");
1430 MODULE_DESCRIPTION("IOP ADMA Engine Driver");
1431 MODULE_LICENSE("GPL");