2 * Driver For Marvell Two-channel DMA Engine
4 * Copyright: Marvell International Ltd.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
12 #include <linux/err.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/types.h>
16 #include <linux/interrupt.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/slab.h>
19 #include <linux/dmaengine.h>
20 #include <linux/platform_device.h>
21 #include <linux/device.h>
22 #include <mach/regs-icu.h>
23 #include <linux/platform_data/dma-mmp_tdma.h>
24 #include <linux/of_device.h>
25 #include <linux/of_dma.h>
27 #include "dmaengine.h"
30 * Two-Channel DMA registers
32 #define TDBCR 0x00 /* Byte Count */
33 #define TDSAR 0x10 /* Src Addr */
34 #define TDDAR 0x20 /* Dst Addr */
35 #define TDNDPR 0x30 /* Next Desc */
36 #define TDCR 0x40 /* Control */
37 #define TDCP 0x60 /* Priority*/
38 #define TDCDPR 0x70 /* Current Desc */
39 #define TDIMR 0x80 /* Int Mask */
40 #define TDISR 0xa0 /* Int Status */
42 /* Two-Channel DMA Control Register */
43 #define TDCR_SSZ_8_BITS (0x0 << 22) /* Sample Size */
44 #define TDCR_SSZ_12_BITS (0x1 << 22)
45 #define TDCR_SSZ_16_BITS (0x2 << 22)
46 #define TDCR_SSZ_20_BITS (0x3 << 22)
47 #define TDCR_SSZ_24_BITS (0x4 << 22)
48 #define TDCR_SSZ_32_BITS (0x5 << 22)
49 #define TDCR_SSZ_SHIFT (0x1 << 22)
50 #define TDCR_SSZ_MASK (0x7 << 22)
51 #define TDCR_SSPMOD (0x1 << 21) /* SSP MOD */
52 #define TDCR_ABR (0x1 << 20) /* Channel Abort */
53 #define TDCR_CDE (0x1 << 17) /* Close Desc Enable */
54 #define TDCR_PACKMOD (0x1 << 16) /* Pack Mode (ADMA Only) */
55 #define TDCR_CHANACT (0x1 << 14) /* Channel Active */
56 #define TDCR_FETCHND (0x1 << 13) /* Fetch Next Desc */
57 #define TDCR_CHANEN (0x1 << 12) /* Channel Enable */
58 #define TDCR_INTMODE (0x1 << 10) /* Interrupt Mode */
59 #define TDCR_CHAINMOD (0x1 << 9) /* Chain Mode */
60 #define TDCR_BURSTSZ_MSK (0x7 << 6) /* Burst Size */
61 #define TDCR_BURSTSZ_4B (0x0 << 6)
62 #define TDCR_BURSTSZ_8B (0x1 << 6)
63 #define TDCR_BURSTSZ_16B (0x3 << 6)
64 #define TDCR_BURSTSZ_32B (0x6 << 6)
65 #define TDCR_BURSTSZ_64B (0x7 << 6)
66 #define TDCR_BURSTSZ_SQU_1B (0x5 << 6)
67 #define TDCR_BURSTSZ_SQU_2B (0x6 << 6)
68 #define TDCR_BURSTSZ_SQU_4B (0x0 << 6)
69 #define TDCR_BURSTSZ_SQU_8B (0x1 << 6)
70 #define TDCR_BURSTSZ_SQU_16B (0x3 << 6)
71 #define TDCR_BURSTSZ_SQU_32B (0x7 << 6)
72 #define TDCR_BURSTSZ_128B (0x5 << 6)
73 #define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */
74 #define TDCR_DSTDIR_ADDR_HOLD (0x2 << 4) /* Dst Addr Hold */
75 #define TDCR_DSTDIR_ADDR_INC (0x0 << 4) /* Dst Addr Increment */
76 #define TDCR_SRCDIR_MSK (0x3 << 2) /* Src Direction */
77 #define TDCR_SRCDIR_ADDR_HOLD (0x2 << 2) /* Src Addr Hold */
78 #define TDCR_SRCDIR_ADDR_INC (0x0 << 2) /* Src Addr Increment */
79 #define TDCR_DSTDESCCONT (0x1 << 1)
80 #define TDCR_SRCDESTCONT (0x1 << 0)
82 /* Two-Channel DMA Int Mask Register */
83 #define TDIMR_COMP (0x1 << 0)
85 /* Two-Channel DMA Int Status Register */
86 #define TDISR_COMP (0x1 << 0)
89 * Two-Channel DMA Descriptor Struct
90 * NOTE: desc's buf must be aligned to 16 bytes.
92 struct mmp_tdma_desc {
104 #define TDMA_ALIGNMENT 3
105 #define TDMA_MAX_XFER_BYTES SZ_64K
107 struct mmp_tdma_chan {
109 struct dma_chan chan;
110 struct dma_async_tx_descriptor desc;
111 struct tasklet_struct tasklet;
113 struct mmp_tdma_desc *desc_arr;
114 phys_addr_t desc_arr_phys;
116 enum dma_transfer_direction dir;
119 enum dma_slave_buswidth buswidth;
120 enum dma_status status;
123 enum mmp_tdma_type type;
125 void __iomem *reg_base;
131 struct gen_pool *pool;
134 #define TDMA_CHANNEL_NUM 2
135 struct mmp_tdma_device {
138 struct dma_device device;
139 struct mmp_tdma_chan *tdmac[TDMA_CHANNEL_NUM];
142 #define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan)
144 static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys)
146 writel(phys, tdmac->reg_base + TDNDPR);
147 writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND,
148 tdmac->reg_base + TDCR);
151 static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac)
154 writel(TDIMR_COMP, tdmac->reg_base + TDIMR);
155 /* enable dma chan */
156 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
157 tdmac->reg_base + TDCR);
158 tdmac->status = DMA_IN_PROGRESS;
161 static void mmp_tdma_disable_chan(struct mmp_tdma_chan *tdmac)
163 writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
164 tdmac->reg_base + TDCR);
167 writel(0, tdmac->reg_base + TDIMR);
169 tdmac->status = DMA_COMPLETE;
172 static void mmp_tdma_resume_chan(struct mmp_tdma_chan *tdmac)
174 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
175 tdmac->reg_base + TDCR);
176 tdmac->status = DMA_IN_PROGRESS;
179 static void mmp_tdma_pause_chan(struct mmp_tdma_chan *tdmac)
181 writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
182 tdmac->reg_base + TDCR);
183 tdmac->status = DMA_PAUSED;
186 static int mmp_tdma_config_chan(struct mmp_tdma_chan *tdmac)
188 unsigned int tdcr = 0;
190 mmp_tdma_disable_chan(tdmac);
192 if (tdmac->dir == DMA_MEM_TO_DEV)
193 tdcr = TDCR_DSTDIR_ADDR_HOLD | TDCR_SRCDIR_ADDR_INC;
194 else if (tdmac->dir == DMA_DEV_TO_MEM)
195 tdcr = TDCR_SRCDIR_ADDR_HOLD | TDCR_DSTDIR_ADDR_INC;
197 if (tdmac->type == MMP_AUD_TDMA) {
198 tdcr |= TDCR_PACKMOD;
200 switch (tdmac->burst_sz) {
202 tdcr |= TDCR_BURSTSZ_4B;
205 tdcr |= TDCR_BURSTSZ_8B;
208 tdcr |= TDCR_BURSTSZ_16B;
211 tdcr |= TDCR_BURSTSZ_32B;
214 tdcr |= TDCR_BURSTSZ_64B;
217 tdcr |= TDCR_BURSTSZ_128B;
220 dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n");
224 switch (tdmac->buswidth) {
225 case DMA_SLAVE_BUSWIDTH_1_BYTE:
226 tdcr |= TDCR_SSZ_8_BITS;
228 case DMA_SLAVE_BUSWIDTH_2_BYTES:
229 tdcr |= TDCR_SSZ_16_BITS;
231 case DMA_SLAVE_BUSWIDTH_4_BYTES:
232 tdcr |= TDCR_SSZ_32_BITS;
235 dev_err(tdmac->dev, "mmp_tdma: unknown bus size.\n");
238 } else if (tdmac->type == PXA910_SQU) {
241 switch (tdmac->burst_sz) {
243 tdcr |= TDCR_BURSTSZ_SQU_1B;
246 tdcr |= TDCR_BURSTSZ_SQU_2B;
249 tdcr |= TDCR_BURSTSZ_SQU_4B;
252 tdcr |= TDCR_BURSTSZ_SQU_8B;
255 tdcr |= TDCR_BURSTSZ_SQU_16B;
258 tdcr |= TDCR_BURSTSZ_SQU_32B;
261 dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n");
266 writel(tdcr, tdmac->reg_base + TDCR);
270 static int mmp_tdma_clear_chan_irq(struct mmp_tdma_chan *tdmac)
272 u32 reg = readl(tdmac->reg_base + TDISR);
274 if (reg & TDISR_COMP) {
277 writel(reg, tdmac->reg_base + TDISR);
284 static irqreturn_t mmp_tdma_chan_handler(int irq, void *dev_id)
286 struct mmp_tdma_chan *tdmac = dev_id;
288 if (mmp_tdma_clear_chan_irq(tdmac) == 0) {
289 tdmac->pos = (tdmac->pos + tdmac->period_len) % tdmac->buf_len;
290 tasklet_schedule(&tdmac->tasklet);
296 static irqreturn_t mmp_tdma_int_handler(int irq, void *dev_id)
298 struct mmp_tdma_device *tdev = dev_id;
302 for (i = 0; i < TDMA_CHANNEL_NUM; i++) {
303 struct mmp_tdma_chan *tdmac = tdev->tdmac[i];
305 ret = mmp_tdma_chan_handler(irq, tdmac);
306 if (ret == IRQ_HANDLED)
316 static void dma_do_tasklet(unsigned long data)
318 struct mmp_tdma_chan *tdmac = (struct mmp_tdma_chan *)data;
320 if (tdmac->desc.callback)
321 tdmac->desc.callback(tdmac->desc.callback_param);
325 static void mmp_tdma_free_descriptor(struct mmp_tdma_chan *tdmac)
327 struct gen_pool *gpool;
328 int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
332 gen_pool_free(gpool, (unsigned long)tdmac->desc_arr,
334 tdmac->desc_arr = NULL;
339 static dma_cookie_t mmp_tdma_tx_submit(struct dma_async_tx_descriptor *tx)
341 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(tx->chan);
343 mmp_tdma_chan_set_desc(tdmac, tdmac->desc_arr_phys);
348 static int mmp_tdma_alloc_chan_resources(struct dma_chan *chan)
350 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
353 dma_async_tx_descriptor_init(&tdmac->desc, chan);
354 tdmac->desc.tx_submit = mmp_tdma_tx_submit;
357 ret = devm_request_irq(tdmac->dev, tdmac->irq,
358 mmp_tdma_chan_handler, 0, "tdma", tdmac);
365 static void mmp_tdma_free_chan_resources(struct dma_chan *chan)
367 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
370 devm_free_irq(tdmac->dev, tdmac->irq, tdmac);
371 mmp_tdma_free_descriptor(tdmac);
375 struct mmp_tdma_desc *mmp_tdma_alloc_descriptor(struct mmp_tdma_chan *tdmac)
377 struct gen_pool *gpool;
378 int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
384 tdmac->desc_arr = gen_pool_dma_alloc(gpool, size, &tdmac->desc_arr_phys);
386 return tdmac->desc_arr;
389 static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic(
390 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
391 size_t period_len, enum dma_transfer_direction direction,
394 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
395 struct mmp_tdma_desc *desc;
396 int num_periods = buf_len / period_len;
399 if (tdmac->status != DMA_COMPLETE)
402 if (period_len > TDMA_MAX_XFER_BYTES) {
404 "maximum period size exceeded: %d > %d\n",
405 period_len, TDMA_MAX_XFER_BYTES);
409 tdmac->status = DMA_IN_PROGRESS;
410 tdmac->desc_num = num_periods;
411 desc = mmp_tdma_alloc_descriptor(tdmac);
415 while (buf < buf_len) {
416 desc = &tdmac->desc_arr[i];
418 if (i + 1 == num_periods)
419 desc->nxt_desc = tdmac->desc_arr_phys;
421 desc->nxt_desc = tdmac->desc_arr_phys +
422 sizeof(*desc) * (i + 1);
424 if (direction == DMA_MEM_TO_DEV) {
425 desc->src_addr = dma_addr;
426 desc->dst_addr = tdmac->dev_addr;
428 desc->src_addr = tdmac->dev_addr;
429 desc->dst_addr = dma_addr;
431 desc->byte_cnt = period_len;
432 dma_addr += period_len;
437 tdmac->buf_len = buf_len;
438 tdmac->period_len = period_len;
444 tdmac->status = DMA_ERROR;
448 static int mmp_tdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
451 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
452 struct dma_slave_config *dmaengine_cfg = (void *)arg;
456 case DMA_TERMINATE_ALL:
457 mmp_tdma_disable_chan(tdmac);
460 mmp_tdma_pause_chan(tdmac);
463 mmp_tdma_resume_chan(tdmac);
465 case DMA_SLAVE_CONFIG:
466 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
467 tdmac->dev_addr = dmaengine_cfg->src_addr;
468 tdmac->burst_sz = dmaengine_cfg->src_maxburst;
469 tdmac->buswidth = dmaengine_cfg->src_addr_width;
471 tdmac->dev_addr = dmaengine_cfg->dst_addr;
472 tdmac->burst_sz = dmaengine_cfg->dst_maxburst;
473 tdmac->buswidth = dmaengine_cfg->dst_addr_width;
475 tdmac->dir = dmaengine_cfg->direction;
476 return mmp_tdma_config_chan(tdmac);
484 static enum dma_status mmp_tdma_tx_status(struct dma_chan *chan,
485 dma_cookie_t cookie, struct dma_tx_state *txstate)
487 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
489 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
490 tdmac->buf_len - tdmac->pos);
492 return tdmac->status;
495 static void mmp_tdma_issue_pending(struct dma_chan *chan)
497 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
499 mmp_tdma_enable_chan(tdmac);
502 static int mmp_tdma_remove(struct platform_device *pdev)
504 struct mmp_tdma_device *tdev = platform_get_drvdata(pdev);
506 dma_async_device_unregister(&tdev->device);
510 static int mmp_tdma_chan_init(struct mmp_tdma_device *tdev,
512 int type, struct gen_pool *pool)
514 struct mmp_tdma_chan *tdmac;
516 if (idx >= TDMA_CHANNEL_NUM) {
517 dev_err(tdev->dev, "too many channels for device!\n");
522 tdmac = devm_kzalloc(tdev->dev, sizeof(*tdmac), GFP_KERNEL);
524 dev_err(tdev->dev, "no free memory for DMA channels!\n");
529 tdmac->dev = tdev->dev;
530 tdmac->chan.device = &tdev->device;
533 tdmac->reg_base = tdev->base + idx * 4;
535 tdmac->status = DMA_COMPLETE;
536 tdev->tdmac[tdmac->idx] = tdmac;
537 tasklet_init(&tdmac->tasklet, dma_do_tasklet, (unsigned long)tdmac);
539 /* add the channel to tdma_chan list */
540 list_add_tail(&tdmac->chan.device_node,
541 &tdev->device.channels);
545 struct mmp_tdma_filter_param {
546 struct device_node *of_node;
547 unsigned int chan_id;
550 static bool mmp_tdma_filter_fn(struct dma_chan *chan, void *fn_param)
552 struct mmp_tdma_filter_param *param = fn_param;
553 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
554 struct dma_device *pdma_device = tdmac->chan.device;
556 if (pdma_device->dev->of_node != param->of_node)
559 if (chan->chan_id != param->chan_id)
565 struct dma_chan *mmp_tdma_xlate(struct of_phandle_args *dma_spec,
566 struct of_dma *ofdma)
568 struct mmp_tdma_device *tdev = ofdma->of_dma_data;
569 dma_cap_mask_t mask = tdev->device.cap_mask;
570 struct mmp_tdma_filter_param param;
572 if (dma_spec->args_count != 1)
575 param.of_node = ofdma->of_node;
576 param.chan_id = dma_spec->args[0];
578 if (param.chan_id >= TDMA_CHANNEL_NUM)
581 return dma_request_channel(mask, mmp_tdma_filter_fn, ¶m);
584 static struct of_device_id mmp_tdma_dt_ids[] = {
585 { .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA},
586 { .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU},
589 MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids);
591 static int mmp_tdma_probe(struct platform_device *pdev)
593 enum mmp_tdma_type type;
594 const struct of_device_id *of_id;
595 struct mmp_tdma_device *tdev;
596 struct resource *iores;
598 int irq = 0, irq_num = 0;
599 int chan_num = TDMA_CHANNEL_NUM;
600 struct gen_pool *pool;
602 of_id = of_match_device(mmp_tdma_dt_ids, &pdev->dev);
604 type = (enum mmp_tdma_type) of_id->data;
606 type = platform_get_device_id(pdev)->driver_data;
608 /* always have couple channels */
609 tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL);
613 tdev->dev = &pdev->dev;
615 for (i = 0; i < chan_num; i++) {
616 if (platform_get_irq(pdev, i) > 0)
620 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
621 tdev->base = devm_ioremap_resource(&pdev->dev, iores);
622 if (IS_ERR(tdev->base))
623 return PTR_ERR(tdev->base);
625 INIT_LIST_HEAD(&tdev->device.channels);
627 if (pdev->dev.of_node)
628 pool = of_get_named_gen_pool(pdev->dev.of_node, "asram", 0);
630 pool = sram_get_gpool("asram");
632 dev_err(&pdev->dev, "asram pool not available\n");
636 if (irq_num != chan_num) {
637 irq = platform_get_irq(pdev, 0);
638 ret = devm_request_irq(&pdev->dev, irq,
639 mmp_tdma_int_handler, 0, "tdma", tdev);
644 /* initialize channel parameters */
645 for (i = 0; i < chan_num; i++) {
646 irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i);
647 ret = mmp_tdma_chan_init(tdev, i, irq, type, pool);
652 dma_cap_set(DMA_SLAVE, tdev->device.cap_mask);
653 dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask);
654 tdev->device.dev = &pdev->dev;
655 tdev->device.device_alloc_chan_resources =
656 mmp_tdma_alloc_chan_resources;
657 tdev->device.device_free_chan_resources =
658 mmp_tdma_free_chan_resources;
659 tdev->device.device_prep_dma_cyclic = mmp_tdma_prep_dma_cyclic;
660 tdev->device.device_tx_status = mmp_tdma_tx_status;
661 tdev->device.device_issue_pending = mmp_tdma_issue_pending;
662 tdev->device.device_control = mmp_tdma_control;
663 tdev->device.copy_align = TDMA_ALIGNMENT;
665 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
666 platform_set_drvdata(pdev, tdev);
668 ret = dma_async_device_register(&tdev->device);
670 dev_err(tdev->device.dev, "unable to register\n");
674 if (pdev->dev.of_node) {
675 ret = of_dma_controller_register(pdev->dev.of_node,
676 mmp_tdma_xlate, tdev);
678 dev_err(tdev->device.dev,
679 "failed to register controller\n");
680 dma_async_device_unregister(&tdev->device);
684 dev_info(tdev->device.dev, "initialized\n");
688 static const struct platform_device_id mmp_tdma_id_table[] = {
689 { "mmp-adma", MMP_AUD_TDMA },
690 { "pxa910-squ", PXA910_SQU },
694 static struct platform_driver mmp_tdma_driver = {
697 .owner = THIS_MODULE,
698 .of_match_table = mmp_tdma_dt_ids,
700 .id_table = mmp_tdma_id_table,
701 .probe = mmp_tdma_probe,
702 .remove = mmp_tdma_remove,
705 module_platform_driver(mmp_tdma_driver);
707 MODULE_LICENSE("GPL");
708 MODULE_DESCRIPTION("MMP Two-Channel DMA Driver");
709 MODULE_ALIAS("platform:mmp-tdma");
710 MODULE_AUTHOR("Leo Yan <leoy@marvell.com>");
711 MODULE_AUTHOR("Zhangfei Gao <zhangfei.gao@marvell.com>");