drivers/dma/nbpfaxi.c

   1 /*
   2  * Copyright (C) 2013-2014 Renesas Electronics Europe Ltd.
   3  * Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #include <linux/bitmap.h>
  11 #include <linux/bitops.h>
  12 #include <linux/clk.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/err.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/log2.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_dma.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/slab.h>
  25
  26 #include <dt-bindings/dma/nbpfaxi.h>
  27
  28 #include "dmaengine.h"
  29
  30 #define NBPF_REG_CHAN_OFFSET    0
  31 #define NBPF_REG_CHAN_SIZE      0x40
  32
  33 /* Channel Current Transaction Byte register */
  34 #define NBPF_CHAN_CUR_TR_BYTE   0x20
  35
  36 /* Channel Status register */
  37 #define NBPF_CHAN_STAT  0x24
  38 #define NBPF_CHAN_STAT_EN       1
  39 #define NBPF_CHAN_STAT_TACT     4
  40 #define NBPF_CHAN_STAT_ERR      0x10
  41 #define NBPF_CHAN_STAT_END      0x20
  42 #define NBPF_CHAN_STAT_TC       0x40
  43 #define NBPF_CHAN_STAT_DER      0x400
  44
  45 /* Channel Control register */
  46 #define NBPF_CHAN_CTRL  0x28
  47 #define NBPF_CHAN_CTRL_SETEN    1
  48 #define NBPF_CHAN_CTRL_CLREN    2
  49 #define NBPF_CHAN_CTRL_STG      4
  50 #define NBPF_CHAN_CTRL_SWRST    8
  51 #define NBPF_CHAN_CTRL_CLRRQ    0x10
  52 #define NBPF_CHAN_CTRL_CLREND   0x20
  53 #define NBPF_CHAN_CTRL_CLRTC    0x40
  54 #define NBPF_CHAN_CTRL_SETSUS   0x100
  55 #define NBPF_CHAN_CTRL_CLRSUS   0x200
  56
  57 /* Channel Configuration register */
  58 #define NBPF_CHAN_CFG   0x2c
  59 #define NBPF_CHAN_CFG_SEL       7               /* terminal SELect: 0..7 */
  60 #define NBPF_CHAN_CFG_REQD      8               /* REQuest Direction: DMAREQ is 0: input, 1: output */
  61 #define NBPF_CHAN_CFG_LOEN      0x10            /* LOw ENable: low DMA request line is: 0: inactive, 1: active */
  62 #define NBPF_CHAN_CFG_HIEN      0x20            /* HIgh ENable: high DMA request line is: 0: inactive, 1: active */
  63 #define NBPF_CHAN_CFG_LVL       0x40            /* LeVeL: DMA request line is sensed as 0: edge, 1: level */
  64 #define NBPF_CHAN_CFG_AM        0x700           /* ACK Mode: 0: Pulse mode, 1: Level mode, b'1x: Bus Cycle */
  65 #define NBPF_CHAN_CFG_SDS       0xf000          /* Source Data Size: 0: 8 bits,... , 7: 1024 bits */
  66 #define NBPF_CHAN_CFG_DDS       0xf0000         /* Destination Data Size: as above */
  67 #define NBPF_CHAN_CFG_SAD       0x100000        /* Source ADdress counting: 0: increment, 1: fixed */
  68 #define NBPF_CHAN_CFG_DAD       0x200000        /* Destination ADdress counting: 0: increment, 1: fixed */
  69 #define NBPF_CHAN_CFG_TM        0x400000        /* Transfer Mode: 0: single, 1: block TM */
  70 #define NBPF_CHAN_CFG_DEM       0x1000000       /* DMAEND interrupt Mask */
  71 #define NBPF_CHAN_CFG_TCM       0x2000000       /* DMATCO interrupt Mask */
  72 #define NBPF_CHAN_CFG_SBE       0x8000000       /* Sweep Buffer Enable */
  73 #define NBPF_CHAN_CFG_RSEL      0x10000000      /* RM: Register Set sELect */
  74 #define NBPF_CHAN_CFG_RSW       0x20000000      /* RM: Register Select sWitch */
  75 #define NBPF_CHAN_CFG_REN       0x40000000      /* RM: Register Set Enable */
  76 #define NBPF_CHAN_CFG_DMS       0x80000000      /* 0: register mode (RM), 1: link mode (LM) */
  77
  78 #define NBPF_CHAN_NXLA  0x38
  79 #define NBPF_CHAN_CRLA  0x3c
  80
  81 /* Link Header field */
  82 #define NBPF_HEADER_LV  1
  83 #define NBPF_HEADER_LE  2
  84 #define NBPF_HEADER_WBD 4
  85 #define NBPF_HEADER_DIM 8
  86
  87 #define NBPF_CTRL       0x300
  88 #define NBPF_CTRL_PR    1               /* 0: fixed priority, 1: round robin */
  89 #define NBPF_CTRL_LVINT 2               /* DMAEND and DMAERR signalling: 0: pulse, 1: level */
  90
  91 #define NBPF_DSTAT_ER   0x314
  92 #define NBPF_DSTAT_END  0x318
  93
  94 #define NBPF_DMA_BUSWIDTHS \
  95         (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
  96          BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
  97          BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
  98          BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
  99          BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
 100
 101 struct nbpf_config {
 102         int num_channels;
 103         int buffer_size;
 104 };
 105
 106 /*
 107  * We've got 3 types of objects, used to describe DMA transfers:
 108  * 1. high-level descriptor, containing a struct dma_async_tx_descriptor object
 109  *      in it, used to communicate with the user
 110  * 2. hardware DMA link descriptors, that we pass to DMAC for DMA transfer
 111  *      queuing, these must be DMAable, using either the streaming DMA API or
 112  *      allocated from coherent memory - one per SG segment
 113  * 3. one per SG segment descriptors, used to manage HW link descriptors from
 114  *      (2). They do not have to be DMAable. They can either be (a) allocated
 115  *      together with link descriptors as mixed (DMA / CPU) objects, or (b)
 116  *      separately. Even if allocated separately it would be best to link them
 117  *      to link descriptors once during channel resource allocation and always
 118  *      use them as a single object.
 119  * Therefore for both cases (a) and (b) at run-time objects (2) and (3) shall be
 120  * treated as a single SG segment descriptor.
 121  */
 122
 123 struct nbpf_link_reg {
 124         u32     header;
 125         u32     src_addr;
 126         u32     dst_addr;
 127         u32     transaction_size;
 128         u32     config;
 129         u32     interval;
 130         u32     extension;
 131         u32     next;
 132 } __packed;
 133
 134 struct nbpf_device;
 135 struct nbpf_channel;
 136 struct nbpf_desc;
 137
 138 struct nbpf_link_desc {
 139         struct nbpf_link_reg *hwdesc;
 140         dma_addr_t hwdesc_dma_addr;
 141         struct nbpf_desc *desc;
 142         struct list_head node;
 143 };
 144
 145 /**
 146  * struct nbpf_desc - DMA transfer descriptor
 147  * @async_tx:   dmaengine object
 148  * @user_wait:  waiting for a user ack
 149  * @length:     total transfer length
 150  * @sg:         list of hardware descriptors, represented by struct nbpf_link_desc
 151  * @node:       member in channel descriptor lists
 152  */
 153 struct nbpf_desc {
 154         struct dma_async_tx_descriptor async_tx;
 155         bool user_wait;
 156         size_t length;
 157         struct nbpf_channel *chan;
 158         struct list_head sg;
 159         struct list_head node;
 160 };
 161
 162 /* Take a wild guess: allocate 4 segments per descriptor */
 163 #define NBPF_SEGMENTS_PER_DESC 4
 164 #define NBPF_DESCS_PER_PAGE ((PAGE_SIZE - sizeof(struct list_head)) /   \
 165         (sizeof(struct nbpf_desc) +                                     \
 166          NBPF_SEGMENTS_PER_DESC *                                       \
 167          (sizeof(struct nbpf_link_desc) + sizeof(struct nbpf_link_reg))))
 168 #define NBPF_SEGMENTS_PER_PAGE (NBPF_SEGMENTS_PER_DESC * NBPF_DESCS_PER_PAGE)
 169
 170 struct nbpf_desc_page {
 171         struct list_head node;
 172         struct nbpf_desc desc[NBPF_DESCS_PER_PAGE];
 173         struct nbpf_link_desc ldesc[NBPF_SEGMENTS_PER_PAGE];
 174         struct nbpf_link_reg hwdesc[NBPF_SEGMENTS_PER_PAGE];
 175 };
 176
 177 /**
 178  * struct nbpf_channel - one DMAC channel
 179  * @dma_chan:   standard dmaengine channel object
 180  * @base:       register address base
 181  * @nbpf:       DMAC
 182  * @name:       IRQ name
 183  * @irq:        IRQ number
 184  * @slave_addr: address for slave DMA
 185  * @slave_width:slave data size in bytes
 186  * @slave_burst:maximum slave burst size in bytes
 187  * @terminal:   DMA terminal, assigned to this channel
 188  * @dmarq_cfg:  DMA request line configuration - high / low, edge / level for NBPF_CHAN_CFG
 189  * @flags:      configuration flags from DT
 190  * @lock:       protect descriptor lists
 191  * @free_links: list of free link descriptors
 192  * @free:       list of free descriptors
 193  * @queued:     list of queued descriptors
 194  * @active:     list of descriptors, scheduled for processing
 195  * @done:       list of completed descriptors, waiting post-processing
 196  * @desc_page:  list of additionally allocated descriptor pages - if any
 197  */
 198 struct nbpf_channel {
 199         struct dma_chan dma_chan;
 200         struct tasklet_struct tasklet;
 201         void __iomem *base;
 202         struct nbpf_device *nbpf;
 203         char name[16];
 204         int irq;
 205         dma_addr_t slave_src_addr;
 206         size_t slave_src_width;
 207         size_t slave_src_burst;
 208         dma_addr_t slave_dst_addr;
 209         size_t slave_dst_width;
 210         size_t slave_dst_burst;
 211         unsigned int terminal;
 212         u32 dmarq_cfg;
 213         unsigned long flags;
 214         spinlock_t lock;
 215         struct list_head free_links;
 216         struct list_head free;
 217         struct list_head queued;
 218         struct list_head active;
 219         struct list_head done;
 220         struct list_head desc_page;
 221         struct nbpf_desc *running;
 222         bool paused;
 223 };
 224
 225 struct nbpf_device {
 226         struct dma_device dma_dev;
 227         void __iomem *base;
 228         struct clk *clk;
 229         const struct nbpf_config *config;
 230         struct nbpf_channel chan[];
 231 };
 232
 233 enum nbpf_model {
 234         NBPF1B4,
 235         NBPF1B8,
 236         NBPF1B16,
 237         NBPF4B4,
 238         NBPF4B8,
 239         NBPF4B16,
 240         NBPF8B4,
 241         NBPF8B8,
 242         NBPF8B16,
 243 };
 244
 245 static struct nbpf_config nbpf_cfg[] = {
 246         [NBPF1B4] = {
 247                 .num_channels = 1,
 248                 .buffer_size = 4,
 249         },
 250         [NBPF1B8] = {
 251                 .num_channels = 1,
 252                 .buffer_size = 8,
 253         },
 254         [NBPF1B16] = {
 255                 .num_channels = 1,
 256                 .buffer_size = 16,
 257         },
 258         [NBPF4B4] = {
 259                 .num_channels = 4,
 260                 .buffer_size = 4,
 261         },
 262         [NBPF4B8] = {
 263                 .num_channels = 4,
 264                 .buffer_size = 8,
 265         },
 266         [NBPF4B16] = {
 267                 .num_channels = 4,
 268                 .buffer_size = 16,
 269         },
 270         [NBPF8B4] = {
 271                 .num_channels = 8,
 272                 .buffer_size = 4,
 273         },
 274         [NBPF8B8] = {
 275                 .num_channels = 8,
 276                 .buffer_size = 8,
 277         },
 278         [NBPF8B16] = {
 279                 .num_channels = 8,
 280                 .buffer_size = 16,
 281         },
 282 };
 283
 284 #define nbpf_to_chan(d) container_of(d, struct nbpf_channel, dma_chan)
 285
 286 /*
 287  * dmaengine drivers seem to have a lot in common and instead of sharing more
 288  * code, they reimplement those common algorithms independently. In this driver
 289  * we try to separate the hardware-specific part from the (largely) generic
 290  * part. This improves code readability and makes it possible in the future to
 291  * reuse the generic code in form of a helper library. That generic code should
 292  * be suitable for various DMA controllers, using transfer descriptors in RAM
 293  * and pushing one SG list at a time to the DMA controller.
 294  */
 295
 296 /*              Hardware-specific part          */
 297
 298 static inline u32 nbpf_chan_read(struct nbpf_channel *chan,
 299                                  unsigned int offset)
 300 {
 301         u32 data = ioread32(chan->base + offset);
 302         dev_dbg(chan->dma_chan.device->dev, "%s(0x%p + 0x%x) = 0x%x\n",
 303                 __func__, chan->base, offset, data);
 304         return data;
 305 }
 306
 307 static inline void nbpf_chan_write(struct nbpf_channel *chan,
 308                                    unsigned int offset, u32 data)
 309 {
 310         iowrite32(data, chan->base + offset);
 311         dev_dbg(chan->dma_chan.device->dev, "%s(0x%p + 0x%x) = 0x%x\n",
 312                 __func__, chan->base, offset, data);
 313 }
 314
 315 static inline u32 nbpf_read(struct nbpf_device *nbpf,
 316                             unsigned int offset)
 317 {
 318         u32 data = ioread32(nbpf->base + offset);
 319         dev_dbg(nbpf->dma_dev.dev, "%s(0x%p + 0x%x) = 0x%x\n",
 320                 __func__, nbpf->base, offset, data);
 321         return data;
 322 }
 323
 324 static inline void nbpf_write(struct nbpf_device *nbpf,
 325                               unsigned int offset, u32 data)
 326 {
 327         iowrite32(data, nbpf->base + offset);
 328         dev_dbg(nbpf->dma_dev.dev, "%s(0x%p + 0x%x) = 0x%x\n",
 329                 __func__, nbpf->base, offset, data);
 330 }
 331
 332 static void nbpf_chan_halt(struct nbpf_channel *chan)
 333 {
 334         nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_CLREN);
 335 }
 336
 337 static bool nbpf_status_get(struct nbpf_channel *chan)
 338 {
 339         u32 status = nbpf_read(chan->nbpf, NBPF_DSTAT_END);
 340
 341         return status & BIT(chan - chan->nbpf->chan);
 342 }
 343
 344 static void nbpf_status_ack(struct nbpf_channel *chan)
 345 {
 346         nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_CLREND);
 347 }
 348
 349 static u32 nbpf_error_get(struct nbpf_device *nbpf)
 350 {
 351         return nbpf_read(nbpf, NBPF_DSTAT_ER);
 352 }
 353
 354 static struct nbpf_channel *nbpf_error_get_channel(struct nbpf_device *nbpf, u32 error)
 355 {
 356         return nbpf->chan + __ffs(error);
 357 }
 358
 359 static void nbpf_error_clear(struct nbpf_channel *chan)
 360 {
 361         u32 status;
 362         int i;
 363
 364         /* Stop the channel, make sure DMA has been aborted */
 365         nbpf_chan_halt(chan);
 366
 367         for (i = 1000; i; i--) {
 368                 status = nbpf_chan_read(chan, NBPF_CHAN_STAT);
 369                 if (!(status & NBPF_CHAN_STAT_TACT))
 370                         break;
 371                 cpu_relax();
 372         }
 373
 374         if (!i)
 375                 dev_err(chan->dma_chan.device->dev,
 376                         "%s(): abort timeout, channel status 0x%x\n", __func__, status);
 377
 378         nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_SWRST);
 379 }
 380
 381 static int nbpf_start(struct nbpf_desc *desc)
 382 {
 383         struct nbpf_channel *chan = desc->chan;
 384         struct nbpf_link_desc *ldesc = list_first_entry(&desc->sg, struct nbpf_link_desc, node);
 385
 386         nbpf_chan_write(chan, NBPF_CHAN_NXLA, (u32)ldesc->hwdesc_dma_addr);
 387         nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_SETEN | NBPF_CHAN_CTRL_CLRSUS);
 388         chan->paused = false;
 389
 390         /* Software trigger MEMCPY - only MEMCPY uses the block mode */
 391         if (ldesc->hwdesc->config & NBPF_CHAN_CFG_TM)
 392                 nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_STG);
 393
 394         dev_dbg(chan->nbpf->dma_dev.dev, "%s(): next 0x%x, cur 0x%x\n", __func__,
 395                 nbpf_chan_read(chan, NBPF_CHAN_NXLA), nbpf_chan_read(chan, NBPF_CHAN_CRLA));
 396
 397         return 0;
 398 }
 399
 400 static void nbpf_chan_prepare(struct nbpf_channel *chan)
 401 {
 402         chan->dmarq_cfg = (chan->flags & NBPF_SLAVE_RQ_HIGH ? NBPF_CHAN_CFG_HIEN : 0) |
 403                 (chan->flags & NBPF_SLAVE_RQ_LOW ? NBPF_CHAN_CFG_LOEN : 0) |
 404                 (chan->flags & NBPF_SLAVE_RQ_LEVEL ?
 405                  NBPF_CHAN_CFG_LVL | (NBPF_CHAN_CFG_AM & 0x200) : 0) |
 406                 chan->terminal;
 407 }
 408
 409 static void nbpf_chan_prepare_default(struct nbpf_channel *chan)
 410 {
 411         /* Don't output DMAACK */
 412         chan->dmarq_cfg = NBPF_CHAN_CFG_AM & 0x400;
 413         chan->terminal = 0;
 414         chan->flags = 0;
 415 }
 416
 417 static void nbpf_chan_configure(struct nbpf_channel *chan)
 418 {
 419         /*
 420          * We assume, that only the link mode and DMA request line configuration
 421          * have to be set in the configuration register manually. Dynamic
 422          * per-transfer configuration will be loaded from transfer descriptors.
 423          */
 424         nbpf_chan_write(chan, NBPF_CHAN_CFG, NBPF_CHAN_CFG_DMS | chan->dmarq_cfg);
 425 }
 426
 427 static u32 nbpf_xfer_ds(struct nbpf_device *nbpf, size_t size)
 428 {
 429         /* Maximum supported bursts depend on the buffer size */
 430         return min_t(int, __ffs(size), ilog2(nbpf->config->buffer_size * 8));
 431 }
 432
 433 static size_t nbpf_xfer_size(struct nbpf_device *nbpf,
 434                              enum dma_slave_buswidth width, u32 burst)
 435 {
 436         size_t size;
 437
 438         if (!burst)
 439                 burst = 1;
 440
 441         switch (width) {
 442         case DMA_SLAVE_BUSWIDTH_8_BYTES:
 443                 size = 8 * burst;
 444                 break;
 445
 446         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 447                 size = 4 * burst;
 448                 break;
 449
 450         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 451                 size = 2 * burst;
 452                 break;
 453
 454         default:
 455                 pr_warn("%s(): invalid bus width %u\n", __func__, width);
 456         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 457                 size = burst;
 458         }
 459
 460         return nbpf_xfer_ds(nbpf, size);
 461 }
 462
 463 /*
 464  * We need a way to recognise slaves, whose data is sent "raw" over the bus,
 465  * i.e. it isn't known in advance how many bytes will be received. Therefore
 466  * the slave driver has to provide a "large enough" buffer and either read the
 467  * buffer, when it is full, or detect, that some data has arrived, then wait for
 468  * a timeout, if no more data arrives - receive what's already there. We want to
 469  * handle such slaves in a special way to allow an optimised mode for other
 470  * users, for whom the amount of data is known in advance. So far there's no way
 471  * to recognise such slaves. We use a data-width check to distinguish between
 472  * the SD host and the PL011 UART.
 473  */
 474
 475 static int nbpf_prep_one(struct nbpf_link_desc *ldesc,
 476                          enum dma_transfer_direction direction,
 477                          dma_addr_t src, dma_addr_t dst, size_t size, bool last)
 478 {
 479         struct nbpf_link_reg *hwdesc = ldesc->hwdesc;
 480         struct nbpf_desc *desc = ldesc->desc;
 481         struct nbpf_channel *chan = desc->chan;
 482         struct device *dev = chan->dma_chan.device->dev;
 483         size_t mem_xfer, slave_xfer;
 484         bool can_burst;
 485
 486         hwdesc->header = NBPF_HEADER_WBD | NBPF_HEADER_LV |
 487                 (last ? NBPF_HEADER_LE : 0);
 488
 489         hwdesc->src_addr = src;
 490         hwdesc->dst_addr = dst;
 491         hwdesc->transaction_size = size;
 492
 493         /*
 494          * set config: SAD, DAD, DDS, SDS, etc.
 495          * Note on transfer sizes: the DMAC can perform unaligned DMA transfers,
 496          * but it is important to have transaction size a multiple of both
 497          * receiver and transmitter transfer sizes. It is also possible to use
 498          * different RAM and device transfer sizes, and it does work well with
 499          * some devices, e.g. with V08R07S01E SD host controllers, which can use
 500          * 128 byte transfers. But this doesn't work with other devices,
 501          * especially when the transaction size is unknown. This is the case,
 502          * e.g. with serial drivers like amba-pl011.c. For reception it sets up
 503          * the transaction size of 4K and if fewer bytes are received, it
 504          * pauses DMA and reads out data received via DMA as well as those left
 505          * in the Rx FIFO. For this to work with the RAM side using burst
 506          * transfers we enable the SBE bit and terminate the transfer in our
 507          * .device_pause handler.
 508          */
 509         mem_xfer = nbpf_xfer_ds(chan->nbpf, size);
 510
 511         switch (direction) {
 512         case DMA_DEV_TO_MEM:
 513                 can_burst = chan->slave_src_width >= 3;
 514                 slave_xfer = min(mem_xfer, can_burst ?
 515                                  chan->slave_src_burst : chan->slave_src_width);
 516                 /*
 517                  * Is the slave narrower than 64 bits, i.e. isn't using the full
 518                  * bus width and cannot use bursts?
 519                  */
 520                 if (mem_xfer > chan->slave_src_burst && !can_burst)
 521                         mem_xfer = chan->slave_src_burst;
 522                 /* Device-to-RAM DMA is unreliable without REQD set */
 523                 hwdesc->config = NBPF_CHAN_CFG_SAD | (NBPF_CHAN_CFG_DDS & (mem_xfer << 16)) |
 524                         (NBPF_CHAN_CFG_SDS & (slave_xfer << 12)) | NBPF_CHAN_CFG_REQD |
 525                         NBPF_CHAN_CFG_SBE;
 526                 break;
 527
 528         case DMA_MEM_TO_DEV:
 529                 slave_xfer = min(mem_xfer, chan->slave_dst_width >= 3 ?
 530                                  chan->slave_dst_burst : chan->slave_dst_width);
 531                 hwdesc->config = NBPF_CHAN_CFG_DAD | (NBPF_CHAN_CFG_SDS & (mem_xfer << 12)) |
 532                         (NBPF_CHAN_CFG_DDS & (slave_xfer << 16)) | NBPF_CHAN_CFG_REQD;
 533                 break;
 534
 535         case DMA_MEM_TO_MEM:
 536                 hwdesc->config = NBPF_CHAN_CFG_TCM | NBPF_CHAN_CFG_TM |
 537                         (NBPF_CHAN_CFG_SDS & (mem_xfer << 12)) |
 538                         (NBPF_CHAN_CFG_DDS & (mem_xfer << 16));
 539                 break;
 540
 541         default:
 542                 return -EINVAL;
 543         }
 544
 545         hwdesc->config |= chan->dmarq_cfg | (last ? 0 : NBPF_CHAN_CFG_DEM) |
 546                 NBPF_CHAN_CFG_DMS;
 547
 548         dev_dbg(dev, "%s(): desc @ %pad: hdr 0x%x, cfg 0x%x, %zu @ %pad -> %pad\n",
 549                 __func__, &ldesc->hwdesc_dma_addr, hwdesc->header,
 550                 hwdesc->config, size, &src, &dst);
 551
 552         dma_sync_single_for_device(dev, ldesc->hwdesc_dma_addr, sizeof(*hwdesc),
 553                                    DMA_TO_DEVICE);
 554
 555         return 0;
 556 }
 557
 558 static size_t nbpf_bytes_left(struct nbpf_channel *chan)
 559 {
 560         return nbpf_chan_read(chan, NBPF_CHAN_CUR_TR_BYTE);
 561 }
 562
 563 static void nbpf_configure(struct nbpf_device *nbpf)
 564 {
 565         nbpf_write(nbpf, NBPF_CTRL, NBPF_CTRL_LVINT);
 566 }
 567
 568 /*              Generic part                    */
 569
 570 /* DMA ENGINE functions */
 571 static void nbpf_issue_pending(struct dma_chan *dchan)
 572 {
 573         struct nbpf_channel *chan = nbpf_to_chan(dchan);
 574         unsigned long flags;
 575
 576         dev_dbg(dchan->device->dev, "Entry %s()\n", __func__);
 577
 578         spin_lock_irqsave(&chan->lock, flags);
 579         if (list_empty(&chan->queued))
 580                 goto unlock;
 581
 582         list_splice_tail_init(&chan->queued, &chan->active);
 583
 584         if (!chan->running) {
 585                 struct nbpf_desc *desc = list_first_entry(&chan->active,
 586                                                 struct nbpf_desc, node);
 587                 if (!nbpf_start(desc))
 588                         chan->running = desc;
 589         }
 590
 591 unlock:
 592         spin_unlock_irqrestore(&chan->lock, flags);
 593 }
 594
 595 static enum dma_status nbpf_tx_status(struct dma_chan *dchan,
 596                 dma_cookie_t cookie, struct dma_tx_state *state)
 597 {
 598         struct nbpf_channel *chan = nbpf_to_chan(dchan);
 599         enum dma_status status = dma_cookie_status(dchan, cookie, state);
 600
 601         if (state) {
 602                 dma_cookie_t running;
 603                 unsigned long flags;
 604
 605                 spin_lock_irqsave(&chan->lock, flags);
 606                 running = chan->running ? chan->running->async_tx.cookie : -EINVAL;
 607
 608                 if (cookie == running) {
 609                         state->residue = nbpf_bytes_left(chan);
 610                         dev_dbg(dchan->device->dev, "%s(): residue %u\n", __func__,
 611                                 state->residue);
 612                 } else if (status == DMA_IN_PROGRESS) {
 613                         struct nbpf_desc *desc;
 614                         bool found = false;
 615
 616                         list_for_each_entry(desc, &chan->active, node)
 617                                 if (desc->async_tx.cookie == cookie) {
 618                                         found = true;
 619                                         break;
 620                                 }
 621
 622                         if (!found)
 623                                 list_for_each_entry(desc, &chan->queued, node)
 624                                         if (desc->async_tx.cookie == cookie) {
 625                                                 found = true;
 626                                                 break;
 627
 628                                         }
 629
 630                         state->residue = found ? desc->length : 0;
 631                 }
 632
 633                 spin_unlock_irqrestore(&chan->lock, flags);
 634         }
 635
 636         if (chan->paused)
 637                 status = DMA_PAUSED;
 638
 639         return status;
 640 }
 641
 642 static dma_cookie_t nbpf_tx_submit(struct dma_async_tx_descriptor *tx)
 643 {
 644         struct nbpf_desc *desc = container_of(tx, struct nbpf_desc, async_tx);
 645         struct nbpf_channel *chan = desc->chan;
 646         unsigned long flags;
 647         dma_cookie_t cookie;
 648
 649         spin_lock_irqsave(&chan->lock, flags);
 650         cookie = dma_cookie_assign(tx);
 651         list_add_tail(&desc->node, &chan->queued);
 652         spin_unlock_irqrestore(&chan->lock, flags);
 653
 654         dev_dbg(chan->dma_chan.device->dev, "Entry %s(%d)\n", __func__, cookie);
 655
 656         return cookie;
 657 }
 658
 659 static int nbpf_desc_page_alloc(struct nbpf_channel *chan)
 660 {
 661         struct dma_chan *dchan = &chan->dma_chan;
 662         struct nbpf_desc_page *dpage = (void *)get_zeroed_page(GFP_KERNEL | GFP_DMA);
 663         struct nbpf_link_desc *ldesc;
 664         struct nbpf_link_reg *hwdesc;
 665         struct nbpf_desc *desc;
 666         LIST_HEAD(head);
 667         LIST_HEAD(lhead);
 668         int i;
 669         struct device *dev = dchan->device->dev;
 670
 671         if (!dpage)
 672                 return -ENOMEM;
 673
 674         dev_dbg(dev, "%s(): alloc %lu descriptors, %lu segments, total alloc %zu\n",
 675                 __func__, NBPF_DESCS_PER_PAGE, NBPF_SEGMENTS_PER_PAGE, sizeof(*dpage));
 676
 677         for (i = 0, ldesc = dpage->ldesc, hwdesc = dpage->hwdesc;
 678              i < ARRAY_SIZE(dpage->ldesc);
 679              i++, ldesc++, hwdesc++) {
 680                 ldesc->hwdesc = hwdesc;
 681                 list_add_tail(&ldesc->node, &lhead);
 682                 ldesc->hwdesc_dma_addr = dma_map_single(dchan->device->dev,
 683                                         hwdesc, sizeof(*hwdesc), DMA_TO_DEVICE);
 684
 685                 dev_dbg(dev, "%s(): mapped 0x%p to %pad\n", __func__,
 686                         hwdesc, &ldesc->hwdesc_dma_addr);
 687         }
 688
 689         for (i = 0, desc = dpage->desc;
 690              i < ARRAY_SIZE(dpage->desc);
 691              i++, desc++) {
 692                 dma_async_tx_descriptor_init(&desc->async_tx, dchan);
 693                 desc->async_tx.tx_submit = nbpf_tx_submit;
 694                 desc->chan = chan;
 695                 INIT_LIST_HEAD(&desc->sg);
 696                 list_add_tail(&desc->node, &head);
 697         }
 698
 699         /*
 700          * This function cannot be called from interrupt context, so, no need to
 701          * save flags
 702          */
 703         spin_lock_irq(&chan->lock);
 704         list_splice_tail(&lhead, &chan->free_links);
 705         list_splice_tail(&head, &chan->free);
 706         list_add(&dpage->node, &chan->desc_page);
 707         spin_unlock_irq(&chan->lock);
 708
 709         return ARRAY_SIZE(dpage->desc);
 710 }
 711
 712 static void nbpf_desc_put(struct nbpf_desc *desc)
 713 {
 714         struct nbpf_channel *chan = desc->chan;
 715         struct nbpf_link_desc *ldesc, *tmp;
 716         unsigned long flags;
 717
 718         spin_lock_irqsave(&chan->lock, flags);
 719         list_for_each_entry_safe(ldesc, tmp, &desc->sg, node)
 720                 list_move(&ldesc->node, &chan->free_links);
 721
 722         list_add(&desc->node, &chan->free);
 723         spin_unlock_irqrestore(&chan->lock, flags);
 724 }
 725
 726 static void nbpf_scan_acked(struct nbpf_channel *chan)
 727 {
 728         struct nbpf_desc *desc, *tmp;
 729         unsigned long flags;
 730         LIST_HEAD(head);
 731
 732         spin_lock_irqsave(&chan->lock, flags);
 733         list_for_each_entry_safe(desc, tmp, &chan->done, node)
 734                 if (async_tx_test_ack(&desc->async_tx) && desc->user_wait) {
 735                         list_move(&desc->node, &head);
 736                         desc->user_wait = false;
 737                 }
 738         spin_unlock_irqrestore(&chan->lock, flags);
 739
 740         list_for_each_entry_safe(desc, tmp, &head, node) {
 741                 list_del(&desc->node);
 742                 nbpf_desc_put(desc);
 743         }
 744 }
 745
 746 /*
 747  * We have to allocate descriptors with the channel lock dropped. This means,
 748  * before we re-acquire the lock buffers can be taken already, so we have to
 749  * re-check after re-acquiring the lock and possibly retry, if buffers are gone
 750  * again.
 751  */
 752 static struct nbpf_desc *nbpf_desc_get(struct nbpf_channel *chan, size_t len)
 753 {
 754         struct nbpf_desc *desc = NULL;
 755         struct nbpf_link_desc *ldesc, *prev = NULL;
 756
 757         nbpf_scan_acked(chan);
 758
 759         spin_lock_irq(&chan->lock);
 760
 761         do {
 762                 int i = 0, ret;
 763
 764                 if (list_empty(&chan->free)) {
 765                         /* No more free descriptors */
 766                         spin_unlock_irq(&chan->lock);
 767                         ret = nbpf_desc_page_alloc(chan);
 768                         if (ret < 0)
 769                                 return NULL;
 770                         spin_lock_irq(&chan->lock);
 771                         continue;
 772                 }
 773                 desc = list_first_entry(&chan->free, struct nbpf_desc, node);
 774                 list_del(&desc->node);
 775
 776                 do {
 777                         if (list_empty(&chan->free_links)) {
 778                                 /* No more free link descriptors */
 779                                 spin_unlock_irq(&chan->lock);
 780                                 ret = nbpf_desc_page_alloc(chan);
 781                                 if (ret < 0) {
 782                                         nbpf_desc_put(desc);
 783                                         return NULL;
 784                                 }
 785                                 spin_lock_irq(&chan->lock);
 786                                 continue;
 787                         }
 788
 789                         ldesc = list_first_entry(&chan->free_links,
 790                                                  struct nbpf_link_desc, node);
 791                         ldesc->desc = desc;
 792                         if (prev)
 793                                 prev->hwdesc->next = (u32)ldesc->hwdesc_dma_addr;
 794
 795                         prev = ldesc;
 796                         list_move_tail(&ldesc->node, &desc->sg);
 797
 798                         i++;
 799                 } while (i < len);
 800         } while (!desc);
 801
 802         prev->hwdesc->next = 0;
 803
 804         spin_unlock_irq(&chan->lock);
 805
 806         return desc;
 807 }
 808
 809 static void nbpf_chan_idle(struct nbpf_channel *chan)
 810 {
 811         struct nbpf_desc *desc, *tmp;
 812         unsigned long flags;
 813         LIST_HEAD(head);
 814
 815         spin_lock_irqsave(&chan->lock, flags);
 816
 817         list_splice_init(&chan->done, &head);
 818         list_splice_init(&chan->active, &head);
 819         list_splice_init(&chan->queued, &head);
 820
 821         chan->running = NULL;
 822
 823         spin_unlock_irqrestore(&chan->lock, flags);
 824
 825         list_for_each_entry_safe(desc, tmp, &head, node) {
 826                 dev_dbg(chan->nbpf->dma_dev.dev, "%s(): force-free desc %p cookie %d\n",
 827                         __func__, desc, desc->async_tx.cookie);
 828                 list_del(&desc->node);
 829                 nbpf_desc_put(desc);
 830         }
 831 }
 832
 833 static int nbpf_pause(struct dma_chan *dchan)
 834 {
 835         struct nbpf_channel *chan = nbpf_to_chan(dchan);
 836
 837         dev_dbg(dchan->device->dev, "Entry %s\n", __func__);
 838
 839         chan->paused = true;
 840         nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_SETSUS);
 841         /* See comment in nbpf_prep_one() */
 842         nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_CLREN);
 843
 844         return 0;
 845 }
 846
 847 static int nbpf_terminate_all(struct dma_chan *dchan)
 848 {
 849         struct nbpf_channel *chan = nbpf_to_chan(dchan);
 850
 851         dev_dbg(dchan->device->dev, "Entry %s\n", __func__);
 852         dev_dbg(dchan->device->dev, "Terminating\n");
 853
 854         nbpf_chan_halt(chan);
 855         nbpf_chan_idle(chan);
 856
 857         return 0;
 858 }
 859
 860 static int nbpf_config(struct dma_chan *dchan,
 861                        struct dma_slave_config *config)
 862 {
 863         struct nbpf_channel *chan = nbpf_to_chan(dchan);
 864
 865         dev_dbg(dchan->device->dev, "Entry %s\n", __func__);
 866
 867         /*
 868          * We could check config->slave_id to match chan->terminal here,
 869          * but with DT they would be coming from the same source, so
 870          * such a check would be superflous
 871          */
 872
 873         chan->slave_dst_addr = config->dst_addr;
 874         chan->slave_dst_width = nbpf_xfer_size(chan->nbpf,
 875                                                config->dst_addr_width, 1);
 876         chan->slave_dst_burst = nbpf_xfer_size(chan->nbpf,
 877                                                config->dst_addr_width,
 878                                                config->dst_maxburst);
 879         chan->slave_src_addr = config->src_addr;
 880         chan->slave_src_width = nbpf_xfer_size(chan->nbpf,
 881                                                config->src_addr_width, 1);
 882         chan->slave_src_burst = nbpf_xfer_size(chan->nbpf,
 883                                                config->src_addr_width,
 884                                                config->src_maxburst);
 885
 886         return 0;
 887 }
 888
 889 static struct dma_async_tx_descriptor *nbpf_prep_sg(struct nbpf_channel *chan,
 890                 struct scatterlist *src_sg, struct scatterlist *dst_sg,
 891                 size_t len, enum dma_transfer_direction direction,
 892                 unsigned long flags)
 893 {
 894         struct nbpf_link_desc *ldesc;
 895         struct scatterlist *mem_sg;
 896         struct nbpf_desc *desc;
 897         bool inc_src, inc_dst;
 898         size_t data_len = 0;
 899         int i = 0;
 900
 901         switch (direction) {
 902         case DMA_DEV_TO_MEM:
 903                 mem_sg = dst_sg;
 904                 inc_src = false;
 905                 inc_dst = true;
 906                 break;
 907
 908         case DMA_MEM_TO_DEV:
 909                 mem_sg = src_sg;
 910                 inc_src = true;
 911                 inc_dst = false;
 912                 break;
 913
 914         default:
 915         case DMA_MEM_TO_MEM:
 916                 mem_sg = src_sg;
 917                 inc_src = true;
 918                 inc_dst = true;
 919         }
 920
 921         desc = nbpf_desc_get(chan, len);
 922         if (!desc)
 923                 return NULL;
 924
 925         desc->async_tx.flags = flags;
 926         desc->async_tx.cookie = -EBUSY;
 927         desc->user_wait = false;
 928
 929         /*
 930          * This is a private descriptor list, and we own the descriptor. No need
 931          * to lock.
 932          */
 933         list_for_each_entry(ldesc, &desc->sg, node) {
 934                 int ret = nbpf_prep_one(ldesc, direction,
 935                                         sg_dma_address(src_sg),
 936                                         sg_dma_address(dst_sg),
 937                                         sg_dma_len(mem_sg),
 938                                         i == len - 1);
 939                 if (ret < 0) {
 940                         nbpf_desc_put(desc);
 941                         return NULL;
 942                 }
 943                 data_len += sg_dma_len(mem_sg);
 944                 if (inc_src)
 945                         src_sg = sg_next(src_sg);
 946                 if (inc_dst)
 947                         dst_sg = sg_next(dst_sg);
 948                 mem_sg = direction == DMA_DEV_TO_MEM ? dst_sg : src_sg;
 949                 i++;
 950         }
 951
 952         desc->length = data_len;
 953
 954         /* The user has to return the descriptor to us ASAP via .tx_submit() */
 955         return &desc->async_tx;
 956 }
 957
 958 static struct dma_async_tx_descriptor *nbpf_prep_memcpy(
 959         struct dma_chan *dchan, dma_addr_t dst, dma_addr_t src,
 960         size_t len, unsigned long flags)
 961 {
 962         struct nbpf_channel *chan = nbpf_to_chan(dchan);
 963         struct scatterlist dst_sg;
 964         struct scatterlist src_sg;
 965
 966         sg_init_table(&dst_sg, 1);
 967         sg_init_table(&src_sg, 1);
 968
 969         sg_dma_address(&dst_sg) = dst;
 970         sg_dma_address(&src_sg) = src;
 971
 972         sg_dma_len(&dst_sg) = len;
 973         sg_dma_len(&src_sg) = len;
 974
 975         dev_dbg(dchan->device->dev, "%s(): %zu @ %pad -> %pad\n",
 976                 __func__, len, &src, &dst);
 977
 978         return nbpf_prep_sg(chan, &src_sg, &dst_sg, 1,
 979                             DMA_MEM_TO_MEM, flags);
 980 }
 981
 982 static struct dma_async_tx_descriptor *nbpf_prep_memcpy_sg(
 983         struct dma_chan *dchan,
 984         struct scatterlist *dst_sg, unsigned int dst_nents,
 985         struct scatterlist *src_sg, unsigned int src_nents,
 986         unsigned long flags)
 987 {
 988         struct nbpf_channel *chan = nbpf_to_chan(dchan);
 989
 990         if (dst_nents != src_nents)
 991                 return NULL;
 992
 993         return nbpf_prep_sg(chan, src_sg, dst_sg, src_nents,
 994                             DMA_MEM_TO_MEM, flags);
 995 }
 996
 997 static struct dma_async_tx_descriptor *nbpf_prep_slave_sg(
 998         struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
 999         enum dma_transfer_direction direction, unsigned long flags, void *context)
1000 {
1001         struct nbpf_channel *chan = nbpf_to_chan(dchan);
1002         struct scatterlist slave_sg;
1003
1004         dev_dbg(dchan->device->dev, "Entry %s()\n", __func__);
1005
1006         sg_init_table(&slave_sg, 1);
1007
1008         switch (direction) {
1009         case DMA_MEM_TO_DEV:
1010                 sg_dma_address(&slave_sg) = chan->slave_dst_addr;
1011                 return nbpf_prep_sg(chan, sgl, &slave_sg, sg_len,
1012                                     direction, flags);
1013
1014         case DMA_DEV_TO_MEM:
1015                 sg_dma_address(&slave_sg) = chan->slave_src_addr;
1016                 return nbpf_prep_sg(chan, &slave_sg, sgl, sg_len,
1017                                     direction, flags);
1018
1019         default:
1020                 return NULL;
1021         }
1022 }
1023
1024 static int nbpf_alloc_chan_resources(struct dma_chan *dchan)
1025 {
1026         struct nbpf_channel *chan = nbpf_to_chan(dchan);
1027         int ret;
1028
1029         INIT_LIST_HEAD(&chan->free);
1030         INIT_LIST_HEAD(&chan->free_links);
1031         INIT_LIST_HEAD(&chan->queued);
1032         INIT_LIST_HEAD(&chan->active);
1033         INIT_LIST_HEAD(&chan->done);
1034
1035         ret = nbpf_desc_page_alloc(chan);
1036         if (ret < 0)
1037                 return ret;
1038
1039         dev_dbg(dchan->device->dev, "Entry %s(): terminal %u\n", __func__,
1040                 chan->terminal);
1041
1042         nbpf_chan_configure(chan);
1043
1044         return ret;
1045 }
1046
1047 static void nbpf_free_chan_resources(struct dma_chan *dchan)
1048 {
1049         struct nbpf_channel *chan = nbpf_to_chan(dchan);
1050         struct nbpf_desc_page *dpage, *tmp;
1051
1052         dev_dbg(dchan->device->dev, "Entry %s()\n", __func__);
1053
1054         nbpf_chan_halt(chan);
1055         nbpf_chan_idle(chan);
1056         /* Clean up for if a channel is re-used for MEMCPY after slave DMA */
1057         nbpf_chan_prepare_default(chan);
1058
1059         list_for_each_entry_safe(dpage, tmp, &chan->desc_page, node) {
1060                 struct nbpf_link_desc *ldesc;
1061                 int i;
1062                 list_del(&dpage->node);
1063                 for (i = 0, ldesc = dpage->ldesc;
1064                      i < ARRAY_SIZE(dpage->ldesc);
1065                      i++, ldesc++)
1066                         dma_unmap_single(dchan->device->dev, ldesc->hwdesc_dma_addr,
1067                                          sizeof(*ldesc->hwdesc), DMA_TO_DEVICE);
1068                 free_page((unsigned long)dpage);
1069         }
1070 }
1071
1072 static struct dma_chan *nbpf_of_xlate(struct of_phandle_args *dma_spec,
1073                                       struct of_dma *ofdma)
1074 {
1075         struct nbpf_device *nbpf = ofdma->of_dma_data;
1076         struct dma_chan *dchan;
1077         struct nbpf_channel *chan;
1078
1079         if (dma_spec->args_count != 2)
1080                 return NULL;
1081
1082         dchan = dma_get_any_slave_channel(&nbpf->dma_dev);
1083         if (!dchan)
1084                 return NULL;
1085
1086         dev_dbg(dchan->device->dev, "Entry %s(%s)\n", __func__,
1087                 dma_spec->np->name);
1088
1089         chan = nbpf_to_chan(dchan);
1090
1091         chan->terminal = dma_spec->args[0];
1092         chan->flags = dma_spec->args[1];
1093
1094         nbpf_chan_prepare(chan);
1095         nbpf_chan_configure(chan);
1096
1097         return dchan;
1098 }
1099
1100 static void nbpf_chan_tasklet(unsigned long data)
1101 {
1102         struct nbpf_channel *chan = (struct nbpf_channel *)data;
1103         struct nbpf_desc *desc, *tmp;
1104         dma_async_tx_callback callback;
1105         void *param;
1106
1107         while (!list_empty(&chan->done)) {
1108                 bool found = false, must_put, recycling = false;
1109
1110                 spin_lock_irq(&chan->lock);
1111
1112                 list_for_each_entry_safe(desc, tmp, &chan->done, node) {
1113                         if (!desc->user_wait) {
1114                                 /* Newly completed descriptor, have to process */
1115                                 found = true;
1116                                 break;
1117                         } else if (async_tx_test_ack(&desc->async_tx)) {
1118                                 /*
1119                                  * This descriptor was waiting for a user ACK,
1120                                  * it can be recycled now.
1121                                  */
1122                                 list_del(&desc->node);
1123                                 spin_unlock_irq(&chan->lock);
1124                                 nbpf_desc_put(desc);
1125                                 recycling = true;
1126                                 break;
1127                         }
1128                 }
1129
1130                 if (recycling)
1131                         continue;
1132
1133                 if (!found) {
1134                         /* This can happen if TERMINATE_ALL has been called */
1135                         spin_unlock_irq(&chan->lock);
1136                         break;
1137                 }
1138
1139                 dma_cookie_complete(&desc->async_tx);
1140
1141                 /*
1142                  * With released lock we cannot dereference desc, maybe it's
1143                  * still on the "done" list
1144                  */
1145                 if (async_tx_test_ack(&desc->async_tx)) {
1146                         list_del(&desc->node);
1147                         must_put = true;
1148                 } else {
1149                         desc->user_wait = true;
1150                         must_put = false;
1151                 }
1152
1153                 callback = desc->async_tx.callback;
1154                 param = desc->async_tx.callback_param;
1155
1156                 /* ack and callback completed descriptor */
1157                 spin_unlock_irq(&chan->lock);
1158
1159                 if (callback)
1160                         callback(param);
1161
1162                 if (must_put)
1163                         nbpf_desc_put(desc);
1164         }
1165 }
1166
1167 static irqreturn_t nbpf_chan_irq(int irq, void *dev)
1168 {
1169         struct nbpf_channel *chan = dev;
1170         bool done = nbpf_status_get(chan);
1171         struct nbpf_desc *desc;
1172         irqreturn_t ret;
1173         bool bh = false;
1174
1175         if (!done)
1176                 return IRQ_NONE;
1177
1178         nbpf_status_ack(chan);
1179
1180         dev_dbg(&chan->dma_chan.dev->device, "%s()\n", __func__);
1181
1182         spin_lock(&chan->lock);
1183         desc = chan->running;
1184         if (WARN_ON(!desc)) {
1185                 ret = IRQ_NONE;
1186                 goto unlock;
1187         } else {
1188                 ret = IRQ_HANDLED;
1189                 bh = true;
1190         }
1191
1192         list_move_tail(&desc->node, &chan->done);
1193         chan->running = NULL;
1194
1195         if (!list_empty(&chan->active)) {
1196                 desc = list_first_entry(&chan->active,
1197                                         struct nbpf_desc, node);
1198                 if (!nbpf_start(desc))
1199                         chan->running = desc;
1200         }
1201
1202 unlock:
1203         spin_unlock(&chan->lock);
1204
1205         if (bh)
1206                 tasklet_schedule(&chan->tasklet);
1207
1208         return ret;
1209 }
1210
1211 static irqreturn_t nbpf_err_irq(int irq, void *dev)
1212 {
1213         struct nbpf_device *nbpf = dev;
1214         u32 error = nbpf_error_get(nbpf);
1215
1216         dev_warn(nbpf->dma_dev.dev, "DMA error IRQ %u\n", irq);
1217
1218         if (!error)
1219                 return IRQ_NONE;
1220
1221         do {
1222                 struct nbpf_channel *chan = nbpf_error_get_channel(nbpf, error);
1223                 /* On error: abort all queued transfers, no callback */
1224                 nbpf_error_clear(chan);
1225                 nbpf_chan_idle(chan);
1226                 error = nbpf_error_get(nbpf);
1227         } while (error);
1228
1229         return IRQ_HANDLED;
1230 }
1231
1232 static int nbpf_chan_probe(struct nbpf_device *nbpf, int n)
1233 {
1234         struct dma_device *dma_dev = &nbpf->dma_dev;
1235         struct nbpf_channel *chan = nbpf->chan + n;
1236         int ret;
1237
1238         chan->nbpf = nbpf;
1239         chan->base = nbpf->base + NBPF_REG_CHAN_OFFSET + NBPF_REG_CHAN_SIZE * n;
1240         INIT_LIST_HEAD(&chan->desc_page);
1241         spin_lock_init(&chan->lock);
1242         chan->dma_chan.device = dma_dev;
1243         dma_cookie_init(&chan->dma_chan);
1244         nbpf_chan_prepare_default(chan);
1245
1246         dev_dbg(dma_dev->dev, "%s(): channel %d: -> %p\n", __func__, n, chan->base);
1247
1248         snprintf(chan->name, sizeof(chan->name), "nbpf %d", n);
1249
1250         tasklet_init(&chan->tasklet, nbpf_chan_tasklet, (unsigned long)chan);
1251         ret = devm_request_irq(dma_dev->dev, chan->irq,
1252                         nbpf_chan_irq, IRQF_SHARED,
1253                         chan->name, chan);
1254         if (ret < 0)
1255                 return ret;
1256
1257         /* Add the channel to DMA device channel list */
1258         list_add_tail(&chan->dma_chan.device_node,
1259                       &dma_dev->channels);
1260
1261         return 0;
1262 }
1263
1264 static const struct of_device_id nbpf_match[] = {
1265         {.compatible = "renesas,nbpfaxi64dmac1b4",      .data = &nbpf_cfg[NBPF1B4]},
1266         {.compatible = "renesas,nbpfaxi64dmac1b8",      .data = &nbpf_cfg[NBPF1B8]},
1267         {.compatible = "renesas,nbpfaxi64dmac1b16",     .data = &nbpf_cfg[NBPF1B16]},
1268         {.compatible = "renesas,nbpfaxi64dmac4b4",      .data = &nbpf_cfg[NBPF4B4]},
1269         {.compatible = "renesas,nbpfaxi64dmac4b8",      .data = &nbpf_cfg[NBPF4B8]},
1270         {.compatible = "renesas,nbpfaxi64dmac4b16",     .data = &nbpf_cfg[NBPF4B16]},
1271         {.compatible = "renesas,nbpfaxi64dmac8b4",      .data = &nbpf_cfg[NBPF8B4]},
1272         {.compatible = "renesas,nbpfaxi64dmac8b8",      .data = &nbpf_cfg[NBPF8B8]},
1273         {.compatible = "renesas,nbpfaxi64dmac8b16",     .data = &nbpf_cfg[NBPF8B16]},
1274         {}
1275 };
1276 MODULE_DEVICE_TABLE(of, nbpf_match);
1277
1278 static int nbpf_probe(struct platform_device *pdev)
1279 {
1280         struct device *dev = &pdev->dev;
1281         const struct of_device_id *of_id = of_match_device(nbpf_match, dev);
1282         struct device_node *np = dev->of_node;
1283         struct nbpf_device *nbpf;
1284         struct dma_device *dma_dev;
1285         struct resource *iomem, *irq_res;
1286         const struct nbpf_config *cfg;
1287         int num_channels;
1288         int ret, irq, eirq, i;
1289         int irqbuf[9] /* maximum 8 channels + error IRQ */;
1290         unsigned int irqs = 0;
1291
1292         BUILD_BUG_ON(sizeof(struct nbpf_desc_page) > PAGE_SIZE);
1293
1294         /* DT only */
1295         if (!np || !of_id || !of_id->data)
1296                 return -ENODEV;
1297
1298         cfg = of_id->data;
1299         num_channels = cfg->num_channels;
1300
1301         nbpf = devm_kzalloc(dev, sizeof(*nbpf) + num_channels *
1302                             sizeof(nbpf->chan[0]), GFP_KERNEL);
1303         if (!nbpf) {
1304                 dev_err(dev, "Memory allocation failed\n");
1305                 return -ENOMEM;
1306         }
1307         dma_dev = &nbpf->dma_dev;
1308         dma_dev->dev = dev;
1309
1310         iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1311         nbpf->base = devm_ioremap_resource(dev, iomem);
1312         if (IS_ERR(nbpf->base))
1313                 return PTR_ERR(nbpf->base);
1314
1315         nbpf->clk = devm_clk_get(dev, NULL);
1316         if (IS_ERR(nbpf->clk))
1317                 return PTR_ERR(nbpf->clk);
1318
1319         nbpf->config = cfg;
1320
1321         for (i = 0; irqs < ARRAY_SIZE(irqbuf); i++) {
1322                 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1323                 if (!irq_res)
1324                         break;
1325
1326                 for (irq = irq_res->start; irq <= irq_res->end;
1327                      irq++, irqs++)
1328                         irqbuf[irqs] = irq;
1329         }
1330
1331         /*
1332          * 3 IRQ resource schemes are supported:
1333          * 1. 1 shared IRQ for error and all channels
1334          * 2. 2 IRQs: one for error and one shared for all channels
1335          * 3. 1 IRQ for error and an own IRQ for each channel
1336          */
1337         if (irqs != 1 && irqs != 2 && irqs != num_channels + 1)
1338                 return -ENXIO;
1339
1340         if (irqs == 1) {
1341                 eirq = irqbuf[0];
1342
1343                 for (i = 0; i <= num_channels; i++)
1344                         nbpf->chan[i].irq = irqbuf[0];
1345         } else {
1346                 eirq = platform_get_irq_byname(pdev, "error");
1347                 if (eirq < 0)
1348                         return eirq;
1349
1350                 if (irqs == num_channels + 1) {
1351                         struct nbpf_channel *chan;
1352
1353                         for (i = 0, chan = nbpf->chan; i <= num_channels;
1354                              i++, chan++) {
1355                                 /* Skip the error IRQ */
1356                                 if (irqbuf[i] == eirq)
1357                                         i++;
1358                                 chan->irq = irqbuf[i];
1359                         }
1360
1361                         if (chan != nbpf->chan + num_channels)
1362                                 return -EINVAL;
1363                 } else {
1364                         /* 2 IRQs and more than one channel */
1365                         if (irqbuf[0] == eirq)
1366                                 irq = irqbuf[1];
1367                         else
1368                                 irq = irqbuf[0];
1369
1370                         for (i = 0; i <= num_channels; i++)
1371                                 nbpf->chan[i].irq = irq;
1372                 }
1373         }
1374
1375         ret = devm_request_irq(dev, eirq, nbpf_err_irq,
1376                                IRQF_SHARED, "dma error", nbpf);
1377         if (ret < 0)
1378                 return ret;
1379
1380         INIT_LIST_HEAD(&dma_dev->channels);
1381
1382         /* Create DMA Channel */
1383         for (i = 0; i < num_channels; i++) {
1384                 ret = nbpf_chan_probe(nbpf, i);
1385                 if (ret < 0)
1386                         return ret;
1387         }
1388
1389         dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
1390         dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
1391         dma_cap_set(DMA_PRIVATE, dma_dev->cap_mask);
1392         dma_cap_set(DMA_SG, dma_dev->cap_mask);
1393
1394         /* Common and MEMCPY operations */
1395         dma_dev->device_alloc_chan_resources
1396                 = nbpf_alloc_chan_resources;
1397         dma_dev->device_free_chan_resources = nbpf_free_chan_resources;
1398         dma_dev->device_prep_dma_sg = nbpf_prep_memcpy_sg;
1399         dma_dev->device_prep_dma_memcpy = nbpf_prep_memcpy;
1400         dma_dev->device_tx_status = nbpf_tx_status;
1401         dma_dev->device_issue_pending = nbpf_issue_pending;
1402
1403         /*
1404          * If we drop support for unaligned MEMCPY buffer addresses and / or
1405          * lengths by setting
1406          * dma_dev->copy_align = 4;
1407          * then we can set transfer length to 4 bytes in nbpf_prep_one() for
1408          * DMA_MEM_TO_MEM
1409          */
1410
1411         /* Compulsory for DMA_SLAVE fields */
1412         dma_dev->device_prep_slave_sg = nbpf_prep_slave_sg;
1413         dma_dev->device_config = nbpf_config;
1414         dma_dev->device_pause = nbpf_pause;
1415         dma_dev->device_terminate_all = nbpf_terminate_all;
1416
1417         dma_dev->src_addr_widths = NBPF_DMA_BUSWIDTHS;
1418         dma_dev->dst_addr_widths = NBPF_DMA_BUSWIDTHS;
1419         dma_dev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1420
1421         platform_set_drvdata(pdev, nbpf);
1422
1423         ret = clk_prepare_enable(nbpf->clk);
1424         if (ret < 0)
1425                 return ret;
1426
1427         nbpf_configure(nbpf);
1428
1429         ret = dma_async_device_register(dma_dev);
1430         if (ret < 0)
1431                 goto e_clk_off;
1432
1433         ret = of_dma_controller_register(np, nbpf_of_xlate, nbpf);
1434         if (ret < 0)
1435                 goto e_dma_dev_unreg;
1436
1437         return 0;
1438
1439 e_dma_dev_unreg:
1440         dma_async_device_unregister(dma_dev);
1441 e_clk_off:
1442         clk_disable_unprepare(nbpf->clk);
1443
1444         return ret;
1445 }
1446
1447 static int nbpf_remove(struct platform_device *pdev)
1448 {
1449         struct nbpf_device *nbpf = platform_get_drvdata(pdev);
1450
1451         of_dma_controller_free(pdev->dev.of_node);
1452         dma_async_device_unregister(&nbpf->dma_dev);
1453         clk_disable_unprepare(nbpf->clk);
1454
1455         return 0;
1456 }
1457
1458 static struct platform_device_id nbpf_ids[] = {
1459         {"nbpfaxi64dmac1b4",    (kernel_ulong_t)&nbpf_cfg[NBPF1B4]},
1460         {"nbpfaxi64dmac1b8",    (kernel_ulong_t)&nbpf_cfg[NBPF1B8]},
1461         {"nbpfaxi64dmac1b16",   (kernel_ulong_t)&nbpf_cfg[NBPF1B16]},
1462         {"nbpfaxi64dmac4b4",    (kernel_ulong_t)&nbpf_cfg[NBPF4B4]},
1463         {"nbpfaxi64dmac4b8",    (kernel_ulong_t)&nbpf_cfg[NBPF4B8]},
1464         {"nbpfaxi64dmac4b16",   (kernel_ulong_t)&nbpf_cfg[NBPF4B16]},
1465         {"nbpfaxi64dmac8b4",    (kernel_ulong_t)&nbpf_cfg[NBPF8B4]},
1466         {"nbpfaxi64dmac8b8",    (kernel_ulong_t)&nbpf_cfg[NBPF8B8]},
1467         {"nbpfaxi64dmac8b16",   (kernel_ulong_t)&nbpf_cfg[NBPF8B16]},
1468         {},
1469 };
1470 MODULE_DEVICE_TABLE(platform, nbpf_ids);
1471
1472 #ifdef CONFIG_PM
1473 static int nbpf_runtime_suspend(struct device *dev)
1474 {
1475         struct nbpf_device *nbpf = platform_get_drvdata(to_platform_device(dev));
1476         clk_disable_unprepare(nbpf->clk);
1477         return 0;
1478 }
1479
1480 static int nbpf_runtime_resume(struct device *dev)
1481 {
1482         struct nbpf_device *nbpf = platform_get_drvdata(to_platform_device(dev));
1483         return clk_prepare_enable(nbpf->clk);
1484 }
1485 #endif
1486
1487 static const struct dev_pm_ops nbpf_pm_ops = {
1488         SET_RUNTIME_PM_OPS(nbpf_runtime_suspend, nbpf_runtime_resume, NULL)
1489 };
1490
1491 static struct platform_driver nbpf_driver = {
1492         .driver = {
1493                 .name = "dma-nbpf",
1494                 .of_match_table = nbpf_match,
1495                 .pm = &nbpf_pm_ops,
1496         },
1497         .id_table = nbpf_ids,
1498         .probe = nbpf_probe,
1499         .remove = nbpf_remove,
1500 };
1501
1502 module_platform_driver(nbpf_driver);
1503
1504 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1505 MODULE_DESCRIPTION("dmaengine driver for NBPFAXI64* DMACs");
1506 MODULE_LICENSE("GPL v2");