2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/string.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/amba/bus.h>
25 #include <linux/amba/pl330.h>
26 #include <linux/scatterlist.h>
28 #include <linux/of_dma.h>
29 #include <linux/err.h>
31 #include "dmaengine.h"
32 #define PL330_MAX_CHAN 8
33 #define PL330_MAX_IRQS 32
34 #define PL330_MAX_PERI 32
36 enum pl330_cachectrl {
37 CCTRL0, /* Noncacheable and nonbufferable */
38 CCTRL1, /* Bufferable only */
39 CCTRL2, /* Cacheable, but do not allocate */
40 CCTRL3, /* Cacheable and bufferable, but do not allocate */
41 INVALID1, /* AWCACHE = 0x1000 */
43 CCTRL6, /* Cacheable write-through, allocate on writes only */
44 CCTRL7, /* Cacheable write-back, allocate on writes only */
55 /* Register and Bit field Definitions */
57 #define DS_ST_STOP 0x0
58 #define DS_ST_EXEC 0x1
59 #define DS_ST_CMISS 0x2
60 #define DS_ST_UPDTPC 0x3
62 #define DS_ST_ATBRR 0x5
63 #define DS_ST_QBUSY 0x6
65 #define DS_ST_KILL 0x8
66 #define DS_ST_CMPLT 0x9
67 #define DS_ST_FLTCMP 0xe
68 #define DS_ST_FAULT 0xf
73 #define INTSTATUS 0x28
80 #define FTC(n) (_FTC + (n)*0x4)
83 #define CS(n) (_CS + (n)*0x8)
84 #define CS_CNS (1 << 21)
87 #define CPC(n) (_CPC + (n)*0x8)
90 #define SA(n) (_SA + (n)*0x20)
93 #define DA(n) (_DA + (n)*0x20)
96 #define CC(n) (_CC + (n)*0x20)
98 #define CC_SRCINC (1 << 0)
99 #define CC_DSTINC (1 << 14)
100 #define CC_SRCPRI (1 << 8)
101 #define CC_DSTPRI (1 << 22)
102 #define CC_SRCNS (1 << 9)
103 #define CC_DSTNS (1 << 23)
104 #define CC_SRCIA (1 << 10)
105 #define CC_DSTIA (1 << 24)
106 #define CC_SRCBRSTLEN_SHFT 4
107 #define CC_DSTBRSTLEN_SHFT 18
108 #define CC_SRCBRSTSIZE_SHFT 1
109 #define CC_DSTBRSTSIZE_SHFT 15
110 #define CC_SRCCCTRL_SHFT 11
111 #define CC_SRCCCTRL_MASK 0x7
112 #define CC_DSTCCTRL_SHFT 25
113 #define CC_DRCCCTRL_MASK 0x7
114 #define CC_SWAP_SHFT 28
117 #define LC0(n) (_LC0 + (n)*0x20)
120 #define LC1(n) (_LC1 + (n)*0x20)
122 #define DBGSTATUS 0xd00
123 #define DBG_BUSY (1 << 0)
126 #define DBGINST0 0xd08
127 #define DBGINST1 0xd0c
136 #define PERIPH_ID 0xfe0
137 #define PERIPH_REV_SHIFT 20
138 #define PERIPH_REV_MASK 0xf
139 #define PERIPH_REV_R0P0 0
140 #define PERIPH_REV_R1P0 1
141 #define PERIPH_REV_R1P1 2
143 #define CR0_PERIPH_REQ_SET (1 << 0)
144 #define CR0_BOOT_EN_SET (1 << 1)
145 #define CR0_BOOT_MAN_NS (1 << 2)
146 #define CR0_NUM_CHANS_SHIFT 4
147 #define CR0_NUM_CHANS_MASK 0x7
148 #define CR0_NUM_PERIPH_SHIFT 12
149 #define CR0_NUM_PERIPH_MASK 0x1f
150 #define CR0_NUM_EVENTS_SHIFT 17
151 #define CR0_NUM_EVENTS_MASK 0x1f
153 #define CR1_ICACHE_LEN_SHIFT 0
154 #define CR1_ICACHE_LEN_MASK 0x7
155 #define CR1_NUM_ICACHELINES_SHIFT 4
156 #define CR1_NUM_ICACHELINES_MASK 0xf
158 #define CRD_DATA_WIDTH_SHIFT 0
159 #define CRD_DATA_WIDTH_MASK 0x7
160 #define CRD_WR_CAP_SHIFT 4
161 #define CRD_WR_CAP_MASK 0x7
162 #define CRD_WR_Q_DEP_SHIFT 8
163 #define CRD_WR_Q_DEP_MASK 0xf
164 #define CRD_RD_CAP_SHIFT 12
165 #define CRD_RD_CAP_MASK 0x7
166 #define CRD_RD_Q_DEP_SHIFT 16
167 #define CRD_RD_Q_DEP_MASK 0xf
168 #define CRD_DATA_BUFF_SHIFT 20
169 #define CRD_DATA_BUFF_MASK 0x3ff
172 #define DESIGNER 0x41
174 #define INTEG_CFG 0x0
175 #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
177 #define PL330_STATE_STOPPED (1 << 0)
178 #define PL330_STATE_EXECUTING (1 << 1)
179 #define PL330_STATE_WFE (1 << 2)
180 #define PL330_STATE_FAULTING (1 << 3)
181 #define PL330_STATE_COMPLETING (1 << 4)
182 #define PL330_STATE_WFP (1 << 5)
183 #define PL330_STATE_KILLING (1 << 6)
184 #define PL330_STATE_FAULT_COMPLETING (1 << 7)
185 #define PL330_STATE_CACHEMISS (1 << 8)
186 #define PL330_STATE_UPDTPC (1 << 9)
187 #define PL330_STATE_ATBARRIER (1 << 10)
188 #define PL330_STATE_QUEUEBUSY (1 << 11)
189 #define PL330_STATE_INVALID (1 << 15)
191 #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
192 | PL330_STATE_WFE | PL330_STATE_FAULTING)
194 #define CMD_DMAADDH 0x54
195 #define CMD_DMAEND 0x00
196 #define CMD_DMAFLUSHP 0x35
197 #define CMD_DMAGO 0xa0
198 #define CMD_DMALD 0x04
199 #define CMD_DMALDP 0x25
200 #define CMD_DMALP 0x20
201 #define CMD_DMALPEND 0x28
202 #define CMD_DMAKILL 0x01
203 #define CMD_DMAMOV 0xbc
204 #define CMD_DMANOP 0x18
205 #define CMD_DMARMB 0x12
206 #define CMD_DMASEV 0x34
207 #define CMD_DMAST 0x08
208 #define CMD_DMASTP 0x29
209 #define CMD_DMASTZ 0x0c
210 #define CMD_DMAWFE 0x36
211 #define CMD_DMAWFP 0x30
212 #define CMD_DMAWMB 0x13
216 #define SZ_DMAFLUSHP 2
220 #define SZ_DMALPEND 2
234 #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
235 #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
237 #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
238 #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
241 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
242 * at 1byte/burst for P<->M and M<->M respectively.
243 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
244 * should be enough for P<->M and M<->M respectively.
246 #define MCODE_BUFF_PER_REQ 256
248 /* Use this _only_ to wait on transient states */
249 #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
251 #ifdef PL330_DEBUG_MCGEN
252 static unsigned cmd_line;
253 #define PL330_DBGCMD_DUMP(off, x...) do { \
254 printk("%x:", cmd_line); \
258 #define PL330_DBGMC_START(addr) (cmd_line = addr)
260 #define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
261 #define PL330_DBGMC_START(addr) do {} while (0)
264 /* The number of default descriptors */
266 #define NR_DEFAULT_DESC 16
268 /* Populated by the PL330 core driver for DMA API driver's info */
269 struct pl330_config {
271 #define DMAC_MODE_NS (1 << 0)
273 unsigned int data_bus_width:10; /* In number of bits */
274 unsigned int data_buf_dep:10;
275 unsigned int num_chan:4;
276 unsigned int num_peri:6;
278 unsigned int num_events:6;
283 * Request Configuration.
284 * The PL330 core does not modify this and uses the last
285 * working configuration if the request doesn't provide any.
287 * The Client may want to provide this info only for the
288 * first request and a request with new settings.
290 struct pl330_reqcfg {
291 /* Address Incrementing */
296 * For now, the SRC & DST protection levels
297 * and burst size/length are assumed same.
303 unsigned brst_size:3; /* in power of 2 */
305 enum pl330_cachectrl dcctl;
306 enum pl330_cachectrl scctl;
307 enum pl330_byteswap swap;
308 struct pl330_config *pcfg;
312 * One cycle of DMAC operation.
313 * There may be more than one xfer in a request.
322 /* The xfer callbacks are made with one of these arguments. */
324 /* The all xfers in the request were success. */
326 /* If req aborted due to global error. */
328 /* If req failed due to problem with Channel. */
333 /* Start the channel */
335 /* Abort the active xfer */
337 /* Stop xfer and flush queue */
358 struct dma_pl330_desc;
363 struct dma_pl330_desc *desc;
366 /* ToBeDone for tasklet */
374 struct pl330_thread {
377 /* If the channel is not yet acquired by any client */
380 struct pl330_dmac *dmac;
381 /* Only two at a time */
382 struct _pl330_req req[2];
383 /* Index of the last enqueued request */
385 /* Index of the last submitted request or -1 if the DMA is stopped */
389 enum pl330_dmac_state {
396 /* In the DMAC pool */
399 * Allocated to some channel during prep_xxx
400 * Also may be sitting on the work_list.
404 * Sitting on the work_list and already submitted
405 * to the PL330 core. Not more than two descriptors
406 * of a channel can be BUSY at any time.
410 * Sitting on the channel work_list but xfer done
416 struct dma_pl330_chan {
417 /* Schedule desc completion */
418 struct tasklet_struct task;
420 /* DMA-Engine Channel */
421 struct dma_chan chan;
423 /* List of submitted descriptors */
424 struct list_head submitted_list;
425 /* List of issued descriptors */
426 struct list_head work_list;
427 /* List of completed descriptors */
428 struct list_head completed_list;
430 /* Pointer to the DMAC that manages this channel,
431 * NULL if the channel is available to be acquired.
432 * As the parent, this DMAC also provides descriptors
435 struct pl330_dmac *dmac;
437 /* To protect channel manipulation */
441 * Hardware channel thread of PL330 DMAC. NULL if the channel is
444 struct pl330_thread *thread;
446 /* For D-to-M and M-to-D channels */
447 int burst_sz; /* the peripheral fifo width */
448 int burst_len; /* the number of burst */
449 dma_addr_t fifo_addr;
451 /* for cyclic capability */
456 /* DMA-Engine Device */
457 struct dma_device ddma;
459 /* Holds info about sg limitations */
460 struct device_dma_parameters dma_parms;
462 /* Pool of descriptors available for the DMAC's channels */
463 struct list_head desc_pool;
464 /* To protect desc_pool manipulation */
465 spinlock_t pool_lock;
467 /* Size of MicroCode buffers for each channel. */
469 /* ioremap'ed address of PL330 registers. */
471 /* Populated by the PL330 core driver during pl330_add */
472 struct pl330_config pcfg;
475 /* Maximum possible events/irqs */
477 /* BUS address of MicroCode buffer */
478 dma_addr_t mcode_bus;
479 /* CPU address of MicroCode buffer */
481 /* List of all Channel threads */
482 struct pl330_thread *channels;
483 /* Pointer to the MANAGER thread */
484 struct pl330_thread *manager;
485 /* To handle bad news in interrupt */
486 struct tasklet_struct tasks;
487 struct _pl330_tbd dmac_tbd;
488 /* State of DMAC operation */
489 enum pl330_dmac_state state;
490 /* Holds list of reqs with due callbacks */
491 struct list_head req_done;
493 /* Peripheral channels connected to this DMAC */
494 unsigned int num_peripherals;
495 struct dma_pl330_chan *peripherals; /* keep at end */
498 struct dma_pl330_desc {
499 /* To attach to a queue as child */
500 struct list_head node;
502 /* Descriptor for the DMA Engine API */
503 struct dma_async_tx_descriptor txd;
505 /* Xfer for PL330 core */
506 struct pl330_xfer px;
508 struct pl330_reqcfg rqcfg;
510 enum desc_status status;
512 /* The channel which currently holds this desc */
513 struct dma_pl330_chan *pchan;
515 enum dma_transfer_direction rqtype;
516 /* Index of peripheral for the xfer. */
518 /* Hook to attach to DMAC's list of reqs with due callback */
519 struct list_head rqd;
524 struct dma_pl330_desc *desc;
527 static inline bool _queue_empty(struct pl330_thread *thrd)
529 return thrd->req[0].desc == NULL && thrd->req[1].desc == NULL;
532 static inline bool _queue_full(struct pl330_thread *thrd)
534 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
537 static inline bool is_manager(struct pl330_thread *thrd)
539 return thrd->dmac->manager == thrd;
542 /* If manager of the thread is in Non-Secure mode */
543 static inline bool _manager_ns(struct pl330_thread *thrd)
545 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
548 static inline u32 get_revision(u32 periph_id)
550 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
553 static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
554 enum pl330_dst da, u16 val)
559 buf[0] = CMD_DMAADDH;
561 *((u16 *)&buf[1]) = val;
563 PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
564 da == 1 ? "DA" : "SA", val);
569 static inline u32 _emit_END(unsigned dry_run, u8 buf[])
576 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
581 static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
586 buf[0] = CMD_DMAFLUSHP;
592 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
597 static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
605 buf[0] |= (0 << 1) | (1 << 0);
606 else if (cond == BURST)
607 buf[0] |= (1 << 1) | (1 << 0);
609 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
610 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
615 static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
616 enum pl330_cond cond, u8 peri)
630 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
631 cond == SINGLE ? 'S' : 'B', peri >> 3);
636 static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
637 unsigned loop, u8 cnt)
647 cnt--; /* DMAC increments by 1 internally */
650 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
656 enum pl330_cond cond;
662 static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
663 const struct _arg_LPEND *arg)
665 enum pl330_cond cond = arg->cond;
666 bool forever = arg->forever;
667 unsigned loop = arg->loop;
668 u8 bjump = arg->bjump;
673 buf[0] = CMD_DMALPEND;
682 buf[0] |= (0 << 1) | (1 << 0);
683 else if (cond == BURST)
684 buf[0] |= (1 << 1) | (1 << 0);
688 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
689 forever ? "FE" : "END",
690 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
697 static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
702 buf[0] = CMD_DMAKILL;
707 static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
708 enum dmamov_dst dst, u32 val)
715 *((u32 *)&buf[2]) = val;
717 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
718 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
723 static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
730 PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
735 static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
742 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
747 static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
758 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
763 static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
771 buf[0] |= (0 << 1) | (1 << 0);
772 else if (cond == BURST)
773 buf[0] |= (1 << 1) | (1 << 0);
775 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
776 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
781 static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
782 enum pl330_cond cond, u8 peri)
796 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
797 cond == SINGLE ? 'S' : 'B', peri >> 3);
802 static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
809 PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
814 static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
829 PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
830 ev >> 3, invalidate ? ", I" : "");
835 static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
836 enum pl330_cond cond, u8 peri)
844 buf[0] |= (0 << 1) | (0 << 0);
845 else if (cond == BURST)
846 buf[0] |= (1 << 1) | (0 << 0);
848 buf[0] |= (0 << 1) | (1 << 0);
854 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
855 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
860 static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
867 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
878 static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
879 const struct _arg_GO *arg)
882 u32 addr = arg->addr;
883 unsigned ns = arg->ns;
893 *((u32 *)&buf[2]) = addr;
898 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
900 /* Returns Time-Out */
901 static bool _until_dmac_idle(struct pl330_thread *thrd)
903 void __iomem *regs = thrd->dmac->base;
904 unsigned long loops = msecs_to_loops(5);
907 /* Until Manager is Idle */
908 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
920 static inline void _execute_DBGINSN(struct pl330_thread *thrd,
921 u8 insn[], bool as_manager)
923 void __iomem *regs = thrd->dmac->base;
926 val = (insn[0] << 16) | (insn[1] << 24);
929 val |= (thrd->id << 8); /* Channel Number */
931 writel(val, regs + DBGINST0);
933 val = *((u32 *)&insn[2]);
934 writel(val, regs + DBGINST1);
936 /* If timed out due to halted state-machine */
937 if (_until_dmac_idle(thrd)) {
938 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
943 writel(0, regs + DBGCMD);
946 static inline u32 _state(struct pl330_thread *thrd)
948 void __iomem *regs = thrd->dmac->base;
951 if (is_manager(thrd))
952 val = readl(regs + DS) & 0xf;
954 val = readl(regs + CS(thrd->id)) & 0xf;
958 return PL330_STATE_STOPPED;
960 return PL330_STATE_EXECUTING;
962 return PL330_STATE_CACHEMISS;
964 return PL330_STATE_UPDTPC;
966 return PL330_STATE_WFE;
968 return PL330_STATE_FAULTING;
970 if (is_manager(thrd))
971 return PL330_STATE_INVALID;
973 return PL330_STATE_ATBARRIER;
975 if (is_manager(thrd))
976 return PL330_STATE_INVALID;
978 return PL330_STATE_QUEUEBUSY;
980 if (is_manager(thrd))
981 return PL330_STATE_INVALID;
983 return PL330_STATE_WFP;
985 if (is_manager(thrd))
986 return PL330_STATE_INVALID;
988 return PL330_STATE_KILLING;
990 if (is_manager(thrd))
991 return PL330_STATE_INVALID;
993 return PL330_STATE_COMPLETING;
995 if (is_manager(thrd))
996 return PL330_STATE_INVALID;
998 return PL330_STATE_FAULT_COMPLETING;
1000 return PL330_STATE_INVALID;
1004 static void _stop(struct pl330_thread *thrd)
1006 void __iomem *regs = thrd->dmac->base;
1007 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1009 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
1010 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1012 /* Return if nothing needs to be done */
1013 if (_state(thrd) == PL330_STATE_COMPLETING
1014 || _state(thrd) == PL330_STATE_KILLING
1015 || _state(thrd) == PL330_STATE_STOPPED)
1018 _emit_KILL(0, insn);
1020 /* Stop generating interrupts for SEV */
1021 writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
1023 _execute_DBGINSN(thrd, insn, is_manager(thrd));
1026 /* Start doing req 'idx' of thread 'thrd' */
1027 static bool _trigger(struct pl330_thread *thrd)
1029 void __iomem *regs = thrd->dmac->base;
1030 struct _pl330_req *req;
1031 struct dma_pl330_desc *desc;
1034 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1037 /* Return if already ACTIVE */
1038 if (_state(thrd) != PL330_STATE_STOPPED)
1041 idx = 1 - thrd->lstenq;
1042 if (thrd->req[idx].desc != NULL) {
1043 req = &thrd->req[idx];
1046 if (thrd->req[idx].desc != NULL)
1047 req = &thrd->req[idx];
1052 /* Return if no request */
1058 ns = desc->rqcfg.nonsecure ? 1 : 0;
1060 /* See 'Abort Sources' point-4 at Page 2-25 */
1061 if (_manager_ns(thrd) && !ns)
1062 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
1063 __func__, __LINE__);
1066 go.addr = req->mc_bus;
1068 _emit_GO(0, insn, &go);
1070 /* Set to generate interrupts for SEV */
1071 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1073 /* Only manager can execute GO */
1074 _execute_DBGINSN(thrd, insn, true);
1076 thrd->req_running = idx;
1081 static bool _start(struct pl330_thread *thrd)
1083 switch (_state(thrd)) {
1084 case PL330_STATE_FAULT_COMPLETING:
1085 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1087 if (_state(thrd) == PL330_STATE_KILLING)
1088 UNTIL(thrd, PL330_STATE_STOPPED)
1090 case PL330_STATE_FAULTING:
1093 case PL330_STATE_KILLING:
1094 case PL330_STATE_COMPLETING:
1095 UNTIL(thrd, PL330_STATE_STOPPED)
1097 case PL330_STATE_STOPPED:
1098 return _trigger(thrd);
1100 case PL330_STATE_WFP:
1101 case PL330_STATE_QUEUEBUSY:
1102 case PL330_STATE_ATBARRIER:
1103 case PL330_STATE_UPDTPC:
1104 case PL330_STATE_CACHEMISS:
1105 case PL330_STATE_EXECUTING:
1108 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1114 static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1115 const struct _xfer_spec *pxs, int cyc)
1118 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
1120 /* check lock-up free version */
1121 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1123 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1124 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1128 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1129 off += _emit_RMB(dry_run, &buf[off]);
1130 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1131 off += _emit_WMB(dry_run, &buf[off]);
1138 static inline int _ldst_devtomem(unsigned dry_run, u8 buf[],
1139 const struct _xfer_spec *pxs, int cyc)
1144 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
1145 off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
1146 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1147 off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
1153 static inline int _ldst_memtodev(unsigned dry_run, u8 buf[],
1154 const struct _xfer_spec *pxs, int cyc)
1159 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
1160 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1161 off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->desc->peri);
1162 off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
1168 static int _bursts(unsigned dry_run, u8 buf[],
1169 const struct _xfer_spec *pxs, int cyc)
1173 switch (pxs->desc->rqtype) {
1174 case DMA_MEM_TO_DEV:
1175 off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc);
1177 case DMA_DEV_TO_MEM:
1178 off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc);
1180 case DMA_MEM_TO_MEM:
1181 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1184 off += 0x40000000; /* Scare off the Client */
1191 /* Returns bytes consumed and updates bursts */
1192 static inline int _loop(unsigned dry_run, u8 buf[],
1193 unsigned long *bursts, const struct _xfer_spec *pxs)
1195 int cyc, cycmax, szlp, szlpend, szbrst, off;
1196 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1197 struct _arg_LPEND lpend;
1199 /* Max iterations possible in DMALP is 256 */
1200 if (*bursts >= 256*256) {
1203 cyc = *bursts / lcnt1 / lcnt0;
1204 } else if (*bursts > 256) {
1206 lcnt0 = *bursts / lcnt1;
1214 szlp = _emit_LP(1, buf, 0, 0);
1215 szbrst = _bursts(1, buf, pxs, 1);
1217 lpend.cond = ALWAYS;
1218 lpend.forever = false;
1221 szlpend = _emit_LPEND(1, buf, &lpend);
1229 * Max bursts that we can unroll due to limit on the
1230 * size of backward jump that can be encoded in DMALPEND
1231 * which is 8-bits and hence 255
1233 cycmax = (255 - (szlp + szlpend)) / szbrst;
1235 cyc = (cycmax < cyc) ? cycmax : cyc;
1240 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1244 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1247 off += _bursts(dry_run, &buf[off], pxs, cyc);
1249 lpend.cond = ALWAYS;
1250 lpend.forever = false;
1252 lpend.bjump = off - ljmp1;
1253 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1256 lpend.cond = ALWAYS;
1257 lpend.forever = false;
1259 lpend.bjump = off - ljmp0;
1260 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1263 *bursts = lcnt1 * cyc;
1270 static inline int _setup_loops(unsigned dry_run, u8 buf[],
1271 const struct _xfer_spec *pxs)
1273 struct pl330_xfer *x = &pxs->desc->px;
1275 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1280 off += _loop(dry_run, &buf[off], &c, pxs);
1287 static inline int _setup_xfer(unsigned dry_run, u8 buf[],
1288 const struct _xfer_spec *pxs)
1290 struct pl330_xfer *x = &pxs->desc->px;
1293 /* DMAMOV SAR, x->src_addr */
1294 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1295 /* DMAMOV DAR, x->dst_addr */
1296 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1299 off += _setup_loops(dry_run, &buf[off], pxs);
1305 * A req is a sequence of one or more xfer units.
1306 * Returns the number of bytes taken to setup the MC for the req.
1308 static int _setup_req(unsigned dry_run, struct pl330_thread *thrd,
1309 unsigned index, struct _xfer_spec *pxs)
1311 struct _pl330_req *req = &thrd->req[index];
1312 struct pl330_xfer *x;
1313 u8 *buf = req->mc_cpu;
1316 PL330_DBGMC_START(req->mc_bus);
1318 /* DMAMOV CCR, ccr */
1319 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1322 /* Error if xfer length is not aligned at burst size */
1323 if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1326 off += _setup_xfer(dry_run, &buf[off], pxs);
1328 /* DMASEV peripheral/event */
1329 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1331 off += _emit_END(dry_run, &buf[off]);
1336 static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1346 /* We set same protection levels for Src and DST for now */
1347 if (rqc->privileged)
1348 ccr |= CC_SRCPRI | CC_DSTPRI;
1350 ccr |= CC_SRCNS | CC_DSTNS;
1351 if (rqc->insnaccess)
1352 ccr |= CC_SRCIA | CC_DSTIA;
1354 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1355 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1357 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1358 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1360 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1361 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1363 ccr |= (rqc->swap << CC_SWAP_SHFT);
1369 * Submit a list of xfers after which the client wants notification.
1370 * Client is not notified after each xfer unit, just once after all
1371 * xfer units are done or some error occurs.
1373 static int pl330_submit_req(struct pl330_thread *thrd,
1374 struct dma_pl330_desc *desc)
1376 struct pl330_dmac *pl330 = thrd->dmac;
1377 struct _xfer_spec xs;
1378 unsigned long flags;
1384 /* No Req or Unacquired Channel or DMAC */
1385 if (!desc || !thrd || thrd->free)
1388 regs = thrd->dmac->base;
1390 if (pl330->state == DYING
1391 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1392 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
1393 __func__, __LINE__);
1397 /* If request for non-existing peripheral */
1398 if (desc->rqtype != DMA_MEM_TO_MEM &&
1399 desc->peri >= pl330->pcfg.num_peri) {
1400 dev_info(thrd->dmac->ddma.dev,
1401 "%s:%d Invalid peripheral(%u)!\n",
1402 __func__, __LINE__, desc->peri);
1406 spin_lock_irqsave(&pl330->lock, flags);
1408 if (_queue_full(thrd)) {
1413 /* Prefer Secure Channel */
1414 if (!_manager_ns(thrd))
1415 desc->rqcfg.nonsecure = 0;
1417 desc->rqcfg.nonsecure = 1;
1419 ccr = _prepare_ccr(&desc->rqcfg);
1421 idx = thrd->req[0].desc == NULL ? 0 : 1;
1426 /* First dry run to check if req is acceptable */
1427 ret = _setup_req(1, thrd, idx, &xs);
1431 if (ret > pl330->mcbufsz / 2) {
1432 dev_info(pl330->ddma.dev, "%s:%d Trying increasing mcbufsz\n",
1433 __func__, __LINE__);
1438 /* Hook the request */
1440 thrd->req[idx].desc = desc;
1441 _setup_req(0, thrd, idx, &xs);
1446 spin_unlock_irqrestore(&pl330->lock, flags);
1451 static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
1453 struct dma_pl330_chan *pch = desc->pchan;
1454 unsigned long flags;
1456 /* If desc aborted */
1460 spin_lock_irqsave(&pch->lock, flags);
1462 desc->status = DONE;
1464 spin_unlock_irqrestore(&pch->lock, flags);
1466 tasklet_schedule(&pch->task);
1469 static void pl330_dotask(unsigned long data)
1471 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1472 unsigned long flags;
1475 spin_lock_irqsave(&pl330->lock, flags);
1477 /* The DMAC itself gone nuts */
1478 if (pl330->dmac_tbd.reset_dmac) {
1479 pl330->state = DYING;
1480 /* Reset the manager too */
1481 pl330->dmac_tbd.reset_mngr = true;
1482 /* Clear the reset flag */
1483 pl330->dmac_tbd.reset_dmac = false;
1486 if (pl330->dmac_tbd.reset_mngr) {
1487 _stop(pl330->manager);
1488 /* Reset all channels */
1489 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
1490 /* Clear the reset flag */
1491 pl330->dmac_tbd.reset_mngr = false;
1494 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1496 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1497 struct pl330_thread *thrd = &pl330->channels[i];
1498 void __iomem *regs = pl330->base;
1499 enum pl330_op_err err;
1503 if (readl(regs + FSC) & (1 << thrd->id))
1504 err = PL330_ERR_FAIL;
1506 err = PL330_ERR_ABORT;
1508 spin_unlock_irqrestore(&pl330->lock, flags);
1509 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1510 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
1511 spin_lock_irqsave(&pl330->lock, flags);
1513 thrd->req[0].desc = NULL;
1514 thrd->req[1].desc = NULL;
1515 thrd->req_running = -1;
1517 /* Clear the reset flag */
1518 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1522 spin_unlock_irqrestore(&pl330->lock, flags);
1527 /* Returns 1 if state was updated, 0 otherwise */
1528 static int pl330_update(struct pl330_dmac *pl330)
1530 struct dma_pl330_desc *descdone, *tmp;
1531 unsigned long flags;
1534 int id, ev, ret = 0;
1538 spin_lock_irqsave(&pl330->lock, flags);
1540 val = readl(regs + FSM) & 0x1;
1542 pl330->dmac_tbd.reset_mngr = true;
1544 pl330->dmac_tbd.reset_mngr = false;
1546 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
1547 pl330->dmac_tbd.reset_chan |= val;
1550 while (i < pl330->pcfg.num_chan) {
1551 if (val & (1 << i)) {
1552 dev_info(pl330->ddma.dev,
1553 "Reset Channel-%d\t CS-%x FTC-%x\n",
1554 i, readl(regs + CS(i)),
1555 readl(regs + FTC(i)));
1556 _stop(&pl330->channels[i]);
1562 /* Check which event happened i.e, thread notified */
1563 val = readl(regs + ES);
1564 if (pl330->pcfg.num_events < 32
1565 && val & ~((1 << pl330->pcfg.num_events) - 1)) {
1566 pl330->dmac_tbd.reset_dmac = true;
1567 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1573 for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
1574 if (val & (1 << ev)) { /* Event occurred */
1575 struct pl330_thread *thrd;
1576 u32 inten = readl(regs + INTEN);
1579 /* Clear the event */
1580 if (inten & (1 << ev))
1581 writel(1 << ev, regs + INTCLR);
1585 id = pl330->events[ev];
1587 thrd = &pl330->channels[id];
1589 active = thrd->req_running;
1590 if (active == -1) /* Aborted */
1593 /* Detach the req */
1594 descdone = thrd->req[active].desc;
1595 thrd->req[active].desc = NULL;
1597 /* Get going again ASAP */
1600 /* For now, just make a list of callbacks to be done */
1601 list_add_tail(&descdone->rqd, &pl330->req_done);
1605 /* Now that we are in no hurry, do the callbacks */
1606 list_for_each_entry_safe(descdone, tmp, &pl330->req_done, rqd) {
1607 list_del(&descdone->rqd);
1608 spin_unlock_irqrestore(&pl330->lock, flags);
1609 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
1610 spin_lock_irqsave(&pl330->lock, flags);
1614 spin_unlock_irqrestore(&pl330->lock, flags);
1616 if (pl330->dmac_tbd.reset_dmac
1617 || pl330->dmac_tbd.reset_mngr
1618 || pl330->dmac_tbd.reset_chan) {
1620 tasklet_schedule(&pl330->tasks);
1626 static int pl330_chan_ctrl(struct pl330_thread *thrd, enum pl330_chan_op op)
1628 struct pl330_dmac *pl330;
1629 unsigned long flags;
1630 int ret = 0, active;
1632 if (!thrd || thrd->free || thrd->dmac->state == DYING)
1636 active = thrd->req_running;
1638 spin_lock_irqsave(&pl330->lock, flags);
1641 case PL330_OP_FLUSH:
1642 /* Make sure the channel is stopped */
1645 thrd->req[0].desc = NULL;
1646 thrd->req[1].desc = NULL;
1647 thrd->req_running = -1;
1650 case PL330_OP_ABORT:
1651 /* Make sure the channel is stopped */
1654 /* ABORT is only for the active req */
1658 thrd->req[active].desc = NULL;
1659 thrd->req_running = -1;
1661 /* Start the next */
1662 case PL330_OP_START:
1663 if ((active == -1) && !_start(thrd))
1671 spin_unlock_irqrestore(&pl330->lock, flags);
1675 /* Reserve an event */
1676 static inline int _alloc_event(struct pl330_thread *thrd)
1678 struct pl330_dmac *pl330 = thrd->dmac;
1681 for (ev = 0; ev < pl330->pcfg.num_events; ev++)
1682 if (pl330->events[ev] == -1) {
1683 pl330->events[ev] = thrd->id;
1690 static bool _chan_ns(const struct pl330_dmac *pl330, int i)
1692 return pl330->pcfg.irq_ns & (1 << i);
1695 /* Upon success, returns IdentityToken for the
1696 * allocated channel, NULL otherwise.
1698 static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
1700 struct pl330_thread *thrd = NULL;
1701 unsigned long flags;
1704 if (pl330->state == DYING)
1707 chans = pl330->pcfg.num_chan;
1709 spin_lock_irqsave(&pl330->lock, flags);
1711 for (i = 0; i < chans; i++) {
1712 thrd = &pl330->channels[i];
1713 if ((thrd->free) && (!_manager_ns(thrd) ||
1714 _chan_ns(pl330, i))) {
1715 thrd->ev = _alloc_event(thrd);
1716 if (thrd->ev >= 0) {
1719 thrd->req[0].desc = NULL;
1720 thrd->req[1].desc = NULL;
1721 thrd->req_running = -1;
1728 spin_unlock_irqrestore(&pl330->lock, flags);
1733 /* Release an event */
1734 static inline void _free_event(struct pl330_thread *thrd, int ev)
1736 struct pl330_dmac *pl330 = thrd->dmac;
1738 /* If the event is valid and was held by the thread */
1739 if (ev >= 0 && ev < pl330->pcfg.num_events
1740 && pl330->events[ev] == thrd->id)
1741 pl330->events[ev] = -1;
1744 static void pl330_release_channel(struct pl330_thread *thrd)
1746 struct pl330_dmac *pl330;
1747 unsigned long flags;
1749 if (!thrd || thrd->free)
1754 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1755 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
1759 spin_lock_irqsave(&pl330->lock, flags);
1760 _free_event(thrd, thrd->ev);
1762 spin_unlock_irqrestore(&pl330->lock, flags);
1765 /* Initialize the structure for PL330 configuration, that can be used
1766 * by the client driver the make best use of the DMAC
1768 static void read_dmac_config(struct pl330_dmac *pl330)
1770 void __iomem *regs = pl330->base;
1773 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1774 val &= CRD_DATA_WIDTH_MASK;
1775 pl330->pcfg.data_bus_width = 8 * (1 << val);
1777 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1778 val &= CRD_DATA_BUFF_MASK;
1779 pl330->pcfg.data_buf_dep = val + 1;
1781 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1782 val &= CR0_NUM_CHANS_MASK;
1784 pl330->pcfg.num_chan = val;
1786 val = readl(regs + CR0);
1787 if (val & CR0_PERIPH_REQ_SET) {
1788 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1790 pl330->pcfg.num_peri = val;
1791 pl330->pcfg.peri_ns = readl(regs + CR4);
1793 pl330->pcfg.num_peri = 0;
1796 val = readl(regs + CR0);
1797 if (val & CR0_BOOT_MAN_NS)
1798 pl330->pcfg.mode |= DMAC_MODE_NS;
1800 pl330->pcfg.mode &= ~DMAC_MODE_NS;
1802 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1803 val &= CR0_NUM_EVENTS_MASK;
1805 pl330->pcfg.num_events = val;
1807 pl330->pcfg.irq_ns = readl(regs + CR3);
1810 static inline void _reset_thread(struct pl330_thread *thrd)
1812 struct pl330_dmac *pl330 = thrd->dmac;
1814 thrd->req[0].mc_cpu = pl330->mcode_cpu
1815 + (thrd->id * pl330->mcbufsz);
1816 thrd->req[0].mc_bus = pl330->mcode_bus
1817 + (thrd->id * pl330->mcbufsz);
1818 thrd->req[0].desc = NULL;
1820 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1821 + pl330->mcbufsz / 2;
1822 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1823 + pl330->mcbufsz / 2;
1824 thrd->req[1].desc = NULL;
1826 thrd->req_running = -1;
1829 static int dmac_alloc_threads(struct pl330_dmac *pl330)
1831 int chans = pl330->pcfg.num_chan;
1832 struct pl330_thread *thrd;
1835 /* Allocate 1 Manager and 'chans' Channel threads */
1836 pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
1838 if (!pl330->channels)
1841 /* Init Channel threads */
1842 for (i = 0; i < chans; i++) {
1843 thrd = &pl330->channels[i];
1846 _reset_thread(thrd);
1850 /* MANAGER is indexed at the end */
1851 thrd = &pl330->channels[chans];
1855 pl330->manager = thrd;
1860 static int dmac_alloc_resources(struct pl330_dmac *pl330)
1862 int chans = pl330->pcfg.num_chan;
1866 * Alloc MicroCode buffer for 'chans' Channel threads.
1867 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1869 pl330->mcode_cpu = dma_alloc_coherent(pl330->ddma.dev,
1870 chans * pl330->mcbufsz,
1871 &pl330->mcode_bus, GFP_KERNEL);
1872 if (!pl330->mcode_cpu) {
1873 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
1874 __func__, __LINE__);
1878 ret = dmac_alloc_threads(pl330);
1880 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
1881 __func__, __LINE__);
1882 dma_free_coherent(pl330->ddma.dev,
1883 chans * pl330->mcbufsz,
1884 pl330->mcode_cpu, pl330->mcode_bus);
1891 static int pl330_add(struct pl330_dmac *pl330)
1898 /* Check if we can handle this DMAC */
1899 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1900 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1901 pl330->pcfg.periph_id);
1905 /* Read the configuration of the DMAC */
1906 read_dmac_config(pl330);
1908 if (pl330->pcfg.num_events == 0) {
1909 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
1910 __func__, __LINE__);
1914 spin_lock_init(&pl330->lock);
1916 INIT_LIST_HEAD(&pl330->req_done);
1918 /* Use default MC buffer size if not provided */
1919 if (!pl330->mcbufsz)
1920 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
1922 /* Mark all events as free */
1923 for (i = 0; i < pl330->pcfg.num_events; i++)
1924 pl330->events[i] = -1;
1926 /* Allocate resources needed by the DMAC */
1927 ret = dmac_alloc_resources(pl330);
1929 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
1933 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
1935 pl330->state = INIT;
1940 static int dmac_free_threads(struct pl330_dmac *pl330)
1942 struct pl330_thread *thrd;
1945 /* Release Channel threads */
1946 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1947 thrd = &pl330->channels[i];
1948 pl330_release_channel(thrd);
1952 kfree(pl330->channels);
1957 static void pl330_del(struct pl330_dmac *pl330)
1959 pl330->state = UNINIT;
1961 tasklet_kill(&pl330->tasks);
1963 /* Free DMAC resources */
1964 dmac_free_threads(pl330);
1966 dma_free_coherent(pl330->ddma.dev,
1967 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
1971 /* forward declaration */
1972 static struct amba_driver pl330_driver;
1974 static inline struct dma_pl330_chan *
1975 to_pchan(struct dma_chan *ch)
1980 return container_of(ch, struct dma_pl330_chan, chan);
1983 static inline struct dma_pl330_desc *
1984 to_desc(struct dma_async_tx_descriptor *tx)
1986 return container_of(tx, struct dma_pl330_desc, txd);
1989 static inline void fill_queue(struct dma_pl330_chan *pch)
1991 struct dma_pl330_desc *desc;
1994 list_for_each_entry(desc, &pch->work_list, node) {
1996 /* If already submitted */
1997 if (desc->status == BUSY)
2000 ret = pl330_submit_req(pch->thread, desc);
2002 desc->status = BUSY;
2003 } else if (ret == -EAGAIN) {
2004 /* QFull or DMAC Dying */
2007 /* Unacceptable request */
2008 desc->status = DONE;
2009 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
2010 __func__, __LINE__, desc->txd.cookie);
2011 tasklet_schedule(&pch->task);
2016 static void pl330_tasklet(unsigned long data)
2018 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
2019 struct dma_pl330_desc *desc, *_dt;
2020 unsigned long flags;
2022 spin_lock_irqsave(&pch->lock, flags);
2024 /* Pick up ripe tomatoes */
2025 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2026 if (desc->status == DONE) {
2028 dma_cookie_complete(&desc->txd);
2029 list_move_tail(&desc->node, &pch->completed_list);
2032 /* Try to submit a req imm. next to the last completed cookie */
2035 /* Make sure the PL330 Channel thread is active */
2036 pl330_chan_ctrl(pch->thread, PL330_OP_START);
2038 while (!list_empty(&pch->completed_list)) {
2039 dma_async_tx_callback callback;
2040 void *callback_param;
2042 desc = list_first_entry(&pch->completed_list,
2043 struct dma_pl330_desc, node);
2045 callback = desc->txd.callback;
2046 callback_param = desc->txd.callback_param;
2049 desc->status = PREP;
2050 list_move_tail(&desc->node, &pch->work_list);
2052 desc->status = FREE;
2053 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2056 dma_descriptor_unmap(&desc->txd);
2059 spin_unlock_irqrestore(&pch->lock, flags);
2060 callback(callback_param);
2061 spin_lock_irqsave(&pch->lock, flags);
2064 spin_unlock_irqrestore(&pch->lock, flags);
2067 bool pl330_filter(struct dma_chan *chan, void *param)
2071 if (chan->device->dev->driver != &pl330_driver.drv)
2074 peri_id = chan->private;
2075 return *peri_id == (unsigned long)param;
2077 EXPORT_SYMBOL(pl330_filter);
2079 static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2080 struct of_dma *ofdma)
2082 int count = dma_spec->args_count;
2083 struct pl330_dmac *pl330 = ofdma->of_dma_data;
2084 unsigned int chan_id;
2092 chan_id = dma_spec->args[0];
2093 if (chan_id >= pl330->num_peripherals)
2096 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
2099 static int pl330_alloc_chan_resources(struct dma_chan *chan)
2101 struct dma_pl330_chan *pch = to_pchan(chan);
2102 struct pl330_dmac *pl330 = pch->dmac;
2103 unsigned long flags;
2105 spin_lock_irqsave(&pch->lock, flags);
2107 dma_cookie_init(chan);
2108 pch->cyclic = false;
2110 pch->thread = pl330_request_channel(pl330);
2112 spin_unlock_irqrestore(&pch->lock, flags);
2116 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2118 spin_unlock_irqrestore(&pch->lock, flags);
2123 static int pl330_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg)
2125 struct dma_pl330_chan *pch = to_pchan(chan);
2126 struct dma_pl330_desc *desc;
2127 unsigned long flags;
2128 struct pl330_dmac *pl330 = pch->dmac;
2129 struct dma_slave_config *slave_config;
2133 case DMA_TERMINATE_ALL:
2134 spin_lock_irqsave(&pch->lock, flags);
2136 /* FLUSH the PL330 Channel thread */
2137 pl330_chan_ctrl(pch->thread, PL330_OP_FLUSH);
2139 /* Mark all desc done */
2140 list_for_each_entry(desc, &pch->submitted_list, node) {
2141 desc->status = FREE;
2142 dma_cookie_complete(&desc->txd);
2145 list_for_each_entry(desc, &pch->work_list , node) {
2146 desc->status = FREE;
2147 dma_cookie_complete(&desc->txd);
2150 list_for_each_entry(desc, &pch->completed_list , node) {
2151 desc->status = FREE;
2152 dma_cookie_complete(&desc->txd);
2155 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2156 list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2157 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2158 spin_unlock_irqrestore(&pch->lock, flags);
2160 case DMA_SLAVE_CONFIG:
2161 slave_config = (struct dma_slave_config *)arg;
2163 if (slave_config->direction == DMA_MEM_TO_DEV) {
2164 if (slave_config->dst_addr)
2165 pch->fifo_addr = slave_config->dst_addr;
2166 if (slave_config->dst_addr_width)
2167 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2168 if (slave_config->dst_maxburst)
2169 pch->burst_len = slave_config->dst_maxburst;
2170 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
2171 if (slave_config->src_addr)
2172 pch->fifo_addr = slave_config->src_addr;
2173 if (slave_config->src_addr_width)
2174 pch->burst_sz = __ffs(slave_config->src_addr_width);
2175 if (slave_config->src_maxburst)
2176 pch->burst_len = slave_config->src_maxburst;
2180 dev_err(pch->dmac->ddma.dev, "Not supported command.\n");
2187 static void pl330_free_chan_resources(struct dma_chan *chan)
2189 struct dma_pl330_chan *pch = to_pchan(chan);
2190 unsigned long flags;
2192 tasklet_kill(&pch->task);
2194 spin_lock_irqsave(&pch->lock, flags);
2196 pl330_release_channel(pch->thread);
2200 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2202 spin_unlock_irqrestore(&pch->lock, flags);
2205 static enum dma_status
2206 pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2207 struct dma_tx_state *txstate)
2209 return dma_cookie_status(chan, cookie, txstate);
2212 static void pl330_issue_pending(struct dma_chan *chan)
2214 struct dma_pl330_chan *pch = to_pchan(chan);
2215 unsigned long flags;
2217 spin_lock_irqsave(&pch->lock, flags);
2218 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2219 spin_unlock_irqrestore(&pch->lock, flags);
2221 pl330_tasklet((unsigned long)pch);
2225 * We returned the last one of the circular list of descriptor(s)
2226 * from prep_xxx, so the argument to submit corresponds to the last
2227 * descriptor of the list.
2229 static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2231 struct dma_pl330_desc *desc, *last = to_desc(tx);
2232 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2233 dma_cookie_t cookie;
2234 unsigned long flags;
2236 spin_lock_irqsave(&pch->lock, flags);
2238 /* Assign cookies to all nodes */
2239 while (!list_empty(&last->node)) {
2240 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2242 desc->txd.callback = last->txd.callback;
2243 desc->txd.callback_param = last->txd.callback_param;
2246 dma_cookie_assign(&desc->txd);
2248 list_move_tail(&desc->node, &pch->submitted_list);
2251 cookie = dma_cookie_assign(&last->txd);
2252 list_add_tail(&last->node, &pch->submitted_list);
2253 spin_unlock_irqrestore(&pch->lock, flags);
2258 static inline void _init_desc(struct dma_pl330_desc *desc)
2260 desc->rqcfg.swap = SWAP_NO;
2261 desc->rqcfg.scctl = CCTRL0;
2262 desc->rqcfg.dcctl = CCTRL0;
2263 desc->txd.tx_submit = pl330_tx_submit;
2265 INIT_LIST_HEAD(&desc->node);
2268 /* Returns the number of descriptors added to the DMAC pool */
2269 static int add_desc(struct pl330_dmac *pl330, gfp_t flg, int count)
2271 struct dma_pl330_desc *desc;
2272 unsigned long flags;
2275 desc = kcalloc(count, sizeof(*desc), flg);
2279 spin_lock_irqsave(&pl330->pool_lock, flags);
2281 for (i = 0; i < count; i++) {
2282 _init_desc(&desc[i]);
2283 list_add_tail(&desc[i].node, &pl330->desc_pool);
2286 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2291 static struct dma_pl330_desc *pluck_desc(struct pl330_dmac *pl330)
2293 struct dma_pl330_desc *desc = NULL;
2294 unsigned long flags;
2296 spin_lock_irqsave(&pl330->pool_lock, flags);
2298 if (!list_empty(&pl330->desc_pool)) {
2299 desc = list_entry(pl330->desc_pool.next,
2300 struct dma_pl330_desc, node);
2302 list_del_init(&desc->node);
2304 desc->status = PREP;
2305 desc->txd.callback = NULL;
2308 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2313 static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2315 struct pl330_dmac *pl330 = pch->dmac;
2316 u8 *peri_id = pch->chan.private;
2317 struct dma_pl330_desc *desc;
2319 /* Pluck one desc from the pool of DMAC */
2320 desc = pluck_desc(pl330);
2322 /* If the DMAC pool is empty, alloc new */
2324 if (!add_desc(pl330, GFP_ATOMIC, 1))
2328 desc = pluck_desc(pl330);
2330 dev_err(pch->dmac->ddma.dev,
2331 "%s:%d ALERT!\n", __func__, __LINE__);
2336 /* Initialize the descriptor */
2338 desc->txd.cookie = 0;
2339 async_tx_ack(&desc->txd);
2341 desc->peri = peri_id ? pch->chan.chan_id : 0;
2342 desc->rqcfg.pcfg = &pch->dmac->pcfg;
2344 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2349 static inline void fill_px(struct pl330_xfer *px,
2350 dma_addr_t dst, dma_addr_t src, size_t len)
2357 static struct dma_pl330_desc *
2358 __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2359 dma_addr_t src, size_t len)
2361 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2364 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2365 __func__, __LINE__);
2370 * Ideally we should lookout for reqs bigger than
2371 * those that can be programmed with 256 bytes of
2372 * MC buffer, but considering a req size is seldom
2373 * going to be word-unaligned and more than 200MB,
2375 * Also, should the limit is reached we'd rather
2376 * have the platform increase MC buffer size than
2377 * complicating this API driver.
2379 fill_px(&desc->px, dst, src, len);
2384 /* Call after fixing burst size */
2385 static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2387 struct dma_pl330_chan *pch = desc->pchan;
2388 struct pl330_dmac *pl330 = pch->dmac;
2391 burst_len = pl330->pcfg.data_bus_width / 8;
2392 burst_len *= pl330->pcfg.data_buf_dep;
2393 burst_len >>= desc->rqcfg.brst_size;
2395 /* src/dst_burst_len can't be more than 16 */
2399 while (burst_len > 1) {
2400 if (!(len % (burst_len << desc->rqcfg.brst_size)))
2408 static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2409 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2410 size_t period_len, enum dma_transfer_direction direction,
2411 unsigned long flags, void *context)
2413 struct dma_pl330_desc *desc = NULL, *first = NULL;
2414 struct dma_pl330_chan *pch = to_pchan(chan);
2415 struct pl330_dmac *pl330 = pch->dmac;
2420 if (len % period_len != 0)
2423 if (!is_slave_direction(direction)) {
2424 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
2425 __func__, __LINE__);
2429 for (i = 0; i < len / period_len; i++) {
2430 desc = pl330_get_desc(pch);
2432 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2433 __func__, __LINE__);
2438 spin_lock_irqsave(&pl330->pool_lock, flags);
2440 while (!list_empty(&first->node)) {
2441 desc = list_entry(first->node.next,
2442 struct dma_pl330_desc, node);
2443 list_move_tail(&desc->node, &pl330->desc_pool);
2446 list_move_tail(&first->node, &pl330->desc_pool);
2448 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2453 switch (direction) {
2454 case DMA_MEM_TO_DEV:
2455 desc->rqcfg.src_inc = 1;
2456 desc->rqcfg.dst_inc = 0;
2458 dst = pch->fifo_addr;
2460 case DMA_DEV_TO_MEM:
2461 desc->rqcfg.src_inc = 0;
2462 desc->rqcfg.dst_inc = 1;
2463 src = pch->fifo_addr;
2470 desc->rqtype = direction;
2471 desc->rqcfg.brst_size = pch->burst_sz;
2472 desc->rqcfg.brst_len = 1;
2473 fill_px(&desc->px, dst, src, period_len);
2478 list_add_tail(&desc->node, &first->node);
2480 dma_addr += period_len;
2487 desc->txd.flags = flags;
2492 static struct dma_async_tx_descriptor *
2493 pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2494 dma_addr_t src, size_t len, unsigned long flags)
2496 struct dma_pl330_desc *desc;
2497 struct dma_pl330_chan *pch = to_pchan(chan);
2498 struct pl330_dmac *pl330 = pch->dmac;
2501 if (unlikely(!pch || !len))
2504 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2508 desc->rqcfg.src_inc = 1;
2509 desc->rqcfg.dst_inc = 1;
2510 desc->rqtype = DMA_MEM_TO_MEM;
2512 /* Select max possible burst size */
2513 burst = pl330->pcfg.data_bus_width / 8;
2521 desc->rqcfg.brst_size = 0;
2522 while (burst != (1 << desc->rqcfg.brst_size))
2523 desc->rqcfg.brst_size++;
2525 desc->rqcfg.brst_len = get_burst_len(desc, len);
2527 desc->txd.flags = flags;
2532 static void __pl330_giveback_desc(struct pl330_dmac *pl330,
2533 struct dma_pl330_desc *first)
2535 unsigned long flags;
2536 struct dma_pl330_desc *desc;
2541 spin_lock_irqsave(&pl330->pool_lock, flags);
2543 while (!list_empty(&first->node)) {
2544 desc = list_entry(first->node.next,
2545 struct dma_pl330_desc, node);
2546 list_move_tail(&desc->node, &pl330->desc_pool);
2549 list_move_tail(&first->node, &pl330->desc_pool);
2551 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2554 static struct dma_async_tx_descriptor *
2555 pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2556 unsigned int sg_len, enum dma_transfer_direction direction,
2557 unsigned long flg, void *context)
2559 struct dma_pl330_desc *first, *desc = NULL;
2560 struct dma_pl330_chan *pch = to_pchan(chan);
2561 struct scatterlist *sg;
2565 if (unlikely(!pch || !sgl || !sg_len))
2568 addr = pch->fifo_addr;
2572 for_each_sg(sgl, sg, sg_len, i) {
2574 desc = pl330_get_desc(pch);
2576 struct pl330_dmac *pl330 = pch->dmac;
2578 dev_err(pch->dmac->ddma.dev,
2579 "%s:%d Unable to fetch desc\n",
2580 __func__, __LINE__);
2581 __pl330_giveback_desc(pl330, first);
2589 list_add_tail(&desc->node, &first->node);
2591 if (direction == DMA_MEM_TO_DEV) {
2592 desc->rqcfg.src_inc = 1;
2593 desc->rqcfg.dst_inc = 0;
2595 addr, sg_dma_address(sg), sg_dma_len(sg));
2597 desc->rqcfg.src_inc = 0;
2598 desc->rqcfg.dst_inc = 1;
2600 sg_dma_address(sg), addr, sg_dma_len(sg));
2603 desc->rqcfg.brst_size = pch->burst_sz;
2604 desc->rqcfg.brst_len = 1;
2605 desc->rqtype = direction;
2608 /* Return the last desc in the chain */
2609 desc->txd.flags = flg;
2613 static irqreturn_t pl330_irq_handler(int irq, void *data)
2615 if (pl330_update(data))
2621 #define PL330_DMA_BUSWIDTHS \
2622 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2623 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2624 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2625 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2626 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2628 static int pl330_dma_device_slave_caps(struct dma_chan *dchan,
2629 struct dma_slave_caps *caps)
2631 caps->src_addr_widths = PL330_DMA_BUSWIDTHS;
2632 caps->dstn_addr_widths = PL330_DMA_BUSWIDTHS;
2633 caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2634 caps->cmd_pause = false;
2635 caps->cmd_terminate = true;
2636 caps->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
2642 pl330_probe(struct amba_device *adev, const struct amba_id *id)
2644 struct dma_pl330_platdata *pdat;
2645 struct pl330_config *pcfg;
2646 struct pl330_dmac *pl330;
2647 struct dma_pl330_chan *pch, *_p;
2648 struct dma_device *pd;
2649 struct resource *res;
2653 pdat = dev_get_platdata(&adev->dev);
2655 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
2659 /* Allocate a new DMAC and its Channels */
2660 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
2662 dev_err(&adev->dev, "unable to allocate mem\n");
2666 pl330->mcbufsz = pdat ? pdat->mcbuf_sz : 0;
2669 pl330->base = devm_ioremap_resource(&adev->dev, res);
2670 if (IS_ERR(pl330->base))
2671 return PTR_ERR(pl330->base);
2673 amba_set_drvdata(adev, pl330);
2675 for (i = 0; i < AMBA_NR_IRQS; i++) {
2678 ret = devm_request_irq(&adev->dev, irq,
2679 pl330_irq_handler, 0,
2680 dev_name(&adev->dev), pl330);
2688 pcfg = &pl330->pcfg;
2690 pcfg->periph_id = adev->periphid;
2691 ret = pl330_add(pl330);
2695 INIT_LIST_HEAD(&pl330->desc_pool);
2696 spin_lock_init(&pl330->pool_lock);
2698 /* Create a descriptor pool of default size */
2699 if (!add_desc(pl330, GFP_KERNEL, NR_DEFAULT_DESC))
2700 dev_warn(&adev->dev, "unable to allocate desc\n");
2703 INIT_LIST_HEAD(&pd->channels);
2705 /* Initialize channel parameters */
2707 num_chan = max_t(int, pdat->nr_valid_peri, pcfg->num_chan);
2709 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
2711 pl330->num_peripherals = num_chan;
2713 pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
2714 if (!pl330->peripherals) {
2716 dev_err(&adev->dev, "unable to allocate pl330->peripherals\n");
2720 for (i = 0; i < num_chan; i++) {
2721 pch = &pl330->peripherals[i];
2722 if (!adev->dev.of_node)
2723 pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
2725 pch->chan.private = adev->dev.of_node;
2727 INIT_LIST_HEAD(&pch->submitted_list);
2728 INIT_LIST_HEAD(&pch->work_list);
2729 INIT_LIST_HEAD(&pch->completed_list);
2730 spin_lock_init(&pch->lock);
2732 pch->chan.device = pd;
2735 /* Add the channel to the DMAC list */
2736 list_add_tail(&pch->chan.device_node, &pd->channels);
2739 pd->dev = &adev->dev;
2741 pd->cap_mask = pdat->cap_mask;
2743 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
2744 if (pcfg->num_peri) {
2745 dma_cap_set(DMA_SLAVE, pd->cap_mask);
2746 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
2747 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
2751 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
2752 pd->device_free_chan_resources = pl330_free_chan_resources;
2753 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
2754 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
2755 pd->device_tx_status = pl330_tx_status;
2756 pd->device_prep_slave_sg = pl330_prep_slave_sg;
2757 pd->device_control = pl330_control;
2758 pd->device_issue_pending = pl330_issue_pending;
2759 pd->device_slave_caps = pl330_dma_device_slave_caps;
2761 ret = dma_async_device_register(pd);
2763 dev_err(&adev->dev, "unable to register DMAC\n");
2767 if (adev->dev.of_node) {
2768 ret = of_dma_controller_register(adev->dev.of_node,
2769 of_dma_pl330_xlate, pl330);
2772 "unable to register DMA to the generic DT DMA helpers\n");
2776 adev->dev.dma_parms = &pl330->dma_parms;
2779 * This is the limit for transfers with a buswidth of 1, larger
2780 * buswidths will have larger limits.
2782 ret = dma_set_max_seg_size(&adev->dev, 1900800);
2784 dev_err(&adev->dev, "unable to set the seg size\n");
2787 dev_info(&adev->dev,
2788 "Loaded driver for PL330 DMAC-%d\n", adev->periphid);
2789 dev_info(&adev->dev,
2790 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
2791 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
2792 pcfg->num_peri, pcfg->num_events);
2797 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
2800 /* Remove the channel */
2801 list_del(&pch->chan.device_node);
2803 /* Flush the channel */
2804 pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0);
2805 pl330_free_chan_resources(&pch->chan);
2813 static int pl330_remove(struct amba_device *adev)
2815 struct pl330_dmac *pl330 = amba_get_drvdata(adev);
2816 struct dma_pl330_chan *pch, *_p;
2818 if (adev->dev.of_node)
2819 of_dma_controller_free(adev->dev.of_node);
2821 dma_async_device_unregister(&pl330->ddma);
2824 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
2827 /* Remove the channel */
2828 list_del(&pch->chan.device_node);
2830 /* Flush the channel */
2831 pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0);
2832 pl330_free_chan_resources(&pch->chan);
2840 static struct amba_id pl330_ids[] = {
2848 MODULE_DEVICE_TABLE(amba, pl330_ids);
2850 static struct amba_driver pl330_driver = {
2852 .owner = THIS_MODULE,
2853 .name = "dma-pl330",
2855 .id_table = pl330_ids,
2856 .probe = pl330_probe,
2857 .remove = pl330_remove,
2860 module_amba_driver(pl330_driver);
2862 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
2863 MODULE_DESCRIPTION("API Driver for PL330 DMAC");
2864 MODULE_LICENSE("GPL");