2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/string.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/amba/bus.h>
25 #include <linux/amba/pl330.h>
26 #include <linux/scatterlist.h>
28 #include <linux/of_dma.h>
29 #include <linux/err.h>
30 #include <linux/pm_runtime.h>
32 #include "dmaengine.h"
33 #define PL330_MAX_CHAN 8
34 #define PL330_MAX_IRQS 32
35 #define PL330_MAX_PERI 32
36 #define PL330_MAX_BURST 16
38 #define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
40 enum pl330_cachectrl {
41 CCTRL0, /* Noncacheable and nonbufferable */
42 CCTRL1, /* Bufferable only */
43 CCTRL2, /* Cacheable, but do not allocate */
44 CCTRL3, /* Cacheable and bufferable, but do not allocate */
45 INVALID1, /* AWCACHE = 0x1000 */
47 CCTRL6, /* Cacheable write-through, allocate on writes only */
48 CCTRL7, /* Cacheable write-back, allocate on writes only */
59 /* Register and Bit field Definitions */
61 #define DS_ST_STOP 0x0
62 #define DS_ST_EXEC 0x1
63 #define DS_ST_CMISS 0x2
64 #define DS_ST_UPDTPC 0x3
66 #define DS_ST_ATBRR 0x5
67 #define DS_ST_QBUSY 0x6
69 #define DS_ST_KILL 0x8
70 #define DS_ST_CMPLT 0x9
71 #define DS_ST_FLTCMP 0xe
72 #define DS_ST_FAULT 0xf
77 #define INTSTATUS 0x28
84 #define FTC(n) (_FTC + (n)*0x4)
87 #define CS(n) (_CS + (n)*0x8)
88 #define CS_CNS (1 << 21)
91 #define CPC(n) (_CPC + (n)*0x8)
94 #define SA(n) (_SA + (n)*0x20)
97 #define DA(n) (_DA + (n)*0x20)
100 #define CC(n) (_CC + (n)*0x20)
102 #define CC_SRCINC (1 << 0)
103 #define CC_DSTINC (1 << 14)
104 #define CC_SRCPRI (1 << 8)
105 #define CC_DSTPRI (1 << 22)
106 #define CC_SRCNS (1 << 9)
107 #define CC_DSTNS (1 << 23)
108 #define CC_SRCIA (1 << 10)
109 #define CC_DSTIA (1 << 24)
110 #define CC_SRCBRSTLEN_SHFT 4
111 #define CC_DSTBRSTLEN_SHFT 18
112 #define CC_SRCBRSTSIZE_SHFT 1
113 #define CC_DSTBRSTSIZE_SHFT 15
114 #define CC_SRCCCTRL_SHFT 11
115 #define CC_SRCCCTRL_MASK 0x7
116 #define CC_DSTCCTRL_SHFT 25
117 #define CC_DRCCCTRL_MASK 0x7
118 #define CC_SWAP_SHFT 28
121 #define LC0(n) (_LC0 + (n)*0x20)
124 #define LC1(n) (_LC1 + (n)*0x20)
126 #define DBGSTATUS 0xd00
127 #define DBG_BUSY (1 << 0)
130 #define DBGINST0 0xd08
131 #define DBGINST1 0xd0c
140 #define PERIPH_ID 0xfe0
141 #define PERIPH_REV_SHIFT 20
142 #define PERIPH_REV_MASK 0xf
143 #define PERIPH_REV_R0P0 0
144 #define PERIPH_REV_R1P0 1
145 #define PERIPH_REV_R1P1 2
147 #define CR0_PERIPH_REQ_SET (1 << 0)
148 #define CR0_BOOT_EN_SET (1 << 1)
149 #define CR0_BOOT_MAN_NS (1 << 2)
150 #define CR0_NUM_CHANS_SHIFT 4
151 #define CR0_NUM_CHANS_MASK 0x7
152 #define CR0_NUM_PERIPH_SHIFT 12
153 #define CR0_NUM_PERIPH_MASK 0x1f
154 #define CR0_NUM_EVENTS_SHIFT 17
155 #define CR0_NUM_EVENTS_MASK 0x1f
157 #define CR1_ICACHE_LEN_SHIFT 0
158 #define CR1_ICACHE_LEN_MASK 0x7
159 #define CR1_NUM_ICACHELINES_SHIFT 4
160 #define CR1_NUM_ICACHELINES_MASK 0xf
162 #define CRD_DATA_WIDTH_SHIFT 0
163 #define CRD_DATA_WIDTH_MASK 0x7
164 #define CRD_WR_CAP_SHIFT 4
165 #define CRD_WR_CAP_MASK 0x7
166 #define CRD_WR_Q_DEP_SHIFT 8
167 #define CRD_WR_Q_DEP_MASK 0xf
168 #define CRD_RD_CAP_SHIFT 12
169 #define CRD_RD_CAP_MASK 0x7
170 #define CRD_RD_Q_DEP_SHIFT 16
171 #define CRD_RD_Q_DEP_MASK 0xf
172 #define CRD_DATA_BUFF_SHIFT 20
173 #define CRD_DATA_BUFF_MASK 0x3ff
176 #define DESIGNER 0x41
178 #define INTEG_CFG 0x0
179 #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
181 #define PL330_STATE_STOPPED (1 << 0)
182 #define PL330_STATE_EXECUTING (1 << 1)
183 #define PL330_STATE_WFE (1 << 2)
184 #define PL330_STATE_FAULTING (1 << 3)
185 #define PL330_STATE_COMPLETING (1 << 4)
186 #define PL330_STATE_WFP (1 << 5)
187 #define PL330_STATE_KILLING (1 << 6)
188 #define PL330_STATE_FAULT_COMPLETING (1 << 7)
189 #define PL330_STATE_CACHEMISS (1 << 8)
190 #define PL330_STATE_UPDTPC (1 << 9)
191 #define PL330_STATE_ATBARRIER (1 << 10)
192 #define PL330_STATE_QUEUEBUSY (1 << 11)
193 #define PL330_STATE_INVALID (1 << 15)
195 #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
196 | PL330_STATE_WFE | PL330_STATE_FAULTING)
198 #define CMD_DMAADDH 0x54
199 #define CMD_DMAEND 0x00
200 #define CMD_DMAFLUSHP 0x35
201 #define CMD_DMAGO 0xa0
202 #define CMD_DMALD 0x04
203 #define CMD_DMALDP 0x25
204 #define CMD_DMALP 0x20
205 #define CMD_DMALPEND 0x28
206 #define CMD_DMAKILL 0x01
207 #define CMD_DMAMOV 0xbc
208 #define CMD_DMANOP 0x18
209 #define CMD_DMARMB 0x12
210 #define CMD_DMASEV 0x34
211 #define CMD_DMAST 0x08
212 #define CMD_DMASTP 0x29
213 #define CMD_DMASTZ 0x0c
214 #define CMD_DMAWFE 0x36
215 #define CMD_DMAWFP 0x30
216 #define CMD_DMAWMB 0x13
220 #define SZ_DMAFLUSHP 2
224 #define SZ_DMALPEND 2
238 #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
239 #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
241 #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
242 #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
243 #define BYTE_MOD_BURST_LEN(b, ccr) (((b) / BRST_SIZE(ccr)) % BRST_LEN(ccr))
246 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
247 * at 1byte/burst for P<->M and M<->M respectively.
248 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
249 * should be enough for P<->M and M<->M respectively.
251 #define MCODE_BUFF_PER_REQ 256
253 /* Use this _only_ to wait on transient states */
254 #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
256 #ifdef PL330_DEBUG_MCGEN
257 static unsigned cmd_line;
258 #define PL330_DBGCMD_DUMP(off, x...) do { \
259 printk("%x:", cmd_line); \
263 #define PL330_DBGMC_START(addr) (cmd_line = addr)
265 #define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
266 #define PL330_DBGMC_START(addr) do {} while (0)
269 /* The number of default descriptors */
271 #define NR_DEFAULT_DESC 16
273 /* Delay for runtime PM autosuspend, ms */
274 #define PL330_AUTOSUSPEND_DELAY 20
276 /* Populated by the PL330 core driver for DMA API driver's info */
277 struct pl330_config {
279 #define DMAC_MODE_NS (1 << 0)
281 unsigned int data_bus_width:10; /* In number of bits */
282 unsigned int data_buf_dep:11;
283 unsigned int num_chan:4;
284 unsigned int num_peri:6;
286 unsigned int num_events:6;
291 * Request Configuration.
292 * The PL330 core does not modify this and uses the last
293 * working configuration if the request doesn't provide any.
295 * The Client may want to provide this info only for the
296 * first request and a request with new settings.
298 struct pl330_reqcfg {
299 /* Address Incrementing */
304 * For now, the SRC & DST protection levels
305 * and burst size/length are assumed same.
311 unsigned brst_size:3; /* in power of 2 */
313 enum pl330_cachectrl dcctl;
314 enum pl330_cachectrl scctl;
315 enum pl330_byteswap swap;
316 struct pl330_config *pcfg;
320 * One cycle of DMAC operation.
321 * There may be more than one xfer in a request.
330 /* The xfer callbacks are made with one of these arguments. */
332 /* The all xfers in the request were success. */
334 /* If req aborted due to global error. */
336 /* If req failed due to problem with Channel. */
357 struct dma_pl330_desc;
362 struct dma_pl330_desc *desc;
365 /* ToBeDone for tasklet */
373 struct pl330_thread {
376 /* If the channel is not yet acquired by any client */
379 struct pl330_dmac *dmac;
380 /* Only two at a time */
381 struct _pl330_req req[2];
382 /* Index of the last enqueued request */
384 /* Index of the last submitted request or -1 if the DMA is stopped */
388 enum pl330_dmac_state {
395 /* In the DMAC pool */
398 * Allocated to some channel during prep_xxx
399 * Also may be sitting on the work_list.
403 * Sitting on the work_list and already submitted
404 * to the PL330 core. Not more than two descriptors
405 * of a channel can be BUSY at any time.
409 * Sitting on the channel work_list but xfer done
415 struct dma_pl330_chan {
416 /* Schedule desc completion */
417 struct tasklet_struct task;
419 /* DMA-Engine Channel */
420 struct dma_chan chan;
422 /* List of submitted descriptors */
423 struct list_head submitted_list;
424 /* List of issued descriptors */
425 struct list_head work_list;
426 /* List of completed descriptors */
427 struct list_head completed_list;
429 /* Pointer to the DMAC that manages this channel,
430 * NULL if the channel is available to be acquired.
431 * As the parent, this DMAC also provides descriptors
434 struct pl330_dmac *dmac;
436 /* To protect channel manipulation */
440 * Hardware channel thread of PL330 DMAC. NULL if the channel is
443 struct pl330_thread *thread;
445 /* For D-to-M and M-to-D channels */
446 int burst_sz; /* the peripheral fifo width */
447 int burst_len; /* the number of burst */
448 dma_addr_t fifo_addr;
450 /* for cyclic capability */
453 /* for runtime pm tracking */
458 /* DMA-Engine Device */
459 struct dma_device ddma;
461 /* Holds info about sg limitations */
462 struct device_dma_parameters dma_parms;
464 /* Pool of descriptors available for the DMAC's channels */
465 struct list_head desc_pool;
466 /* To protect desc_pool manipulation */
467 spinlock_t pool_lock;
469 /* Size of MicroCode buffers for each channel. */
471 /* ioremap'ed address of PL330 registers. */
473 /* Populated by the PL330 core driver during pl330_add */
474 struct pl330_config pcfg;
477 /* Maximum possible events/irqs */
479 /* BUS address of MicroCode buffer */
480 dma_addr_t mcode_bus;
481 /* CPU address of MicroCode buffer */
483 /* List of all Channel threads */
484 struct pl330_thread *channels;
485 /* Pointer to the MANAGER thread */
486 struct pl330_thread *manager;
487 /* To handle bad news in interrupt */
488 struct tasklet_struct tasks;
489 struct _pl330_tbd dmac_tbd;
490 /* State of DMAC operation */
491 enum pl330_dmac_state state;
492 /* Holds list of reqs with due callbacks */
493 struct list_head req_done;
495 /* Peripheral channels connected to this DMAC */
496 unsigned int num_peripherals;
497 struct dma_pl330_chan *peripherals; /* keep at end */
498 /* set peripherals request type according to soc config*/
499 enum pl330_cond peripherals_req_type;
503 static struct pl330_of_quirks {
508 .quirk = "arm,pl330-broken-no-flushp",
509 .id = PL330_QUIRK_BROKEN_NO_FLUSHP,
513 struct dma_pl330_desc {
514 /* To attach to a queue as child */
515 struct list_head node;
517 /* Descriptor for the DMA Engine API */
518 struct dma_async_tx_descriptor txd;
520 /* Xfer for PL330 core */
521 struct pl330_xfer px;
523 struct pl330_reqcfg rqcfg;
525 enum desc_status status;
530 /* The channel which currently holds this desc */
531 struct dma_pl330_chan *pchan;
533 enum dma_transfer_direction rqtype;
534 /* Index of peripheral for the xfer. */
536 /* Hook to attach to DMAC's list of reqs with due callback */
537 struct list_head rqd;
542 struct dma_pl330_desc *desc;
545 static inline bool _queue_empty(struct pl330_thread *thrd)
547 return thrd->req[0].desc == NULL && thrd->req[1].desc == NULL;
550 static inline bool _queue_full(struct pl330_thread *thrd)
552 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
555 static inline bool is_manager(struct pl330_thread *thrd)
557 return thrd->dmac->manager == thrd;
560 /* If manager of the thread is in Non-Secure mode */
561 static inline bool _manager_ns(struct pl330_thread *thrd)
563 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
566 static inline u32 get_revision(u32 periph_id)
568 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
571 static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
572 enum pl330_dst da, u16 val)
577 buf[0] = CMD_DMAADDH;
579 *((__le16 *)&buf[1]) = cpu_to_le16(val);
581 PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
582 da == 1 ? "DA" : "SA", val);
587 static inline u32 _emit_END(unsigned dry_run, u8 buf[])
594 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
599 static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
604 buf[0] = CMD_DMAFLUSHP;
610 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
615 static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
623 buf[0] |= (0 << 1) | (1 << 0);
624 else if (cond == BURST)
625 buf[0] |= (1 << 1) | (1 << 0);
627 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
628 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
633 static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
634 enum pl330_cond cond, u8 peri)
648 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
649 cond == SINGLE ? 'S' : 'B', peri >> 3);
654 static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
655 unsigned loop, u8 cnt)
665 cnt--; /* DMAC increments by 1 internally */
668 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
674 enum pl330_cond cond;
680 static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
681 const struct _arg_LPEND *arg)
683 enum pl330_cond cond = arg->cond;
684 bool forever = arg->forever;
685 unsigned loop = arg->loop;
686 u8 bjump = arg->bjump;
691 buf[0] = CMD_DMALPEND;
700 buf[0] |= (0 << 1) | (1 << 0);
701 else if (cond == BURST)
702 buf[0] |= (1 << 1) | (1 << 0);
706 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
707 forever ? "FE" : "END",
708 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
715 static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
720 buf[0] = CMD_DMAKILL;
725 static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
726 enum dmamov_dst dst, u32 val)
733 *((__le32 *)&buf[2]) = cpu_to_le32(val);
735 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
736 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
741 static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
748 PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
753 static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
760 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
765 static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
776 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
781 static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
789 buf[0] |= (0 << 1) | (1 << 0);
790 else if (cond == BURST)
791 buf[0] |= (1 << 1) | (1 << 0);
793 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
794 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
799 static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
800 enum pl330_cond cond, u8 peri)
814 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
815 cond == SINGLE ? 'S' : 'B', peri >> 3);
820 static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
827 PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
832 static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
847 PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
848 ev >> 3, invalidate ? ", I" : "");
853 static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
854 enum pl330_cond cond, u8 peri)
862 buf[0] |= (0 << 1) | (0 << 0);
863 else if (cond == BURST)
864 buf[0] |= (1 << 1) | (0 << 0);
866 buf[0] |= (0 << 1) | (1 << 0);
872 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
873 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
878 static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
885 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
896 static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
897 const struct _arg_GO *arg)
900 u32 addr = arg->addr;
901 unsigned ns = arg->ns;
911 *((__le32 *)&buf[2]) = cpu_to_le32(addr);
916 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
918 /* Returns Time-Out */
919 static bool _until_dmac_idle(struct pl330_thread *thrd)
921 void __iomem *regs = thrd->dmac->base;
922 unsigned long loops = msecs_to_loops(5);
925 /* Until Manager is Idle */
926 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
938 static inline void _execute_DBGINSN(struct pl330_thread *thrd,
939 u8 insn[], bool as_manager)
941 void __iomem *regs = thrd->dmac->base;
944 val = (insn[0] << 16) | (insn[1] << 24);
947 val |= (thrd->id << 8); /* Channel Number */
949 writel(val, regs + DBGINST0);
951 val = le32_to_cpu(*((__le32 *)&insn[2]));
952 writel(val, regs + DBGINST1);
954 /* If timed out due to halted state-machine */
955 if (_until_dmac_idle(thrd)) {
956 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
961 writel(0, regs + DBGCMD);
964 static inline u32 _state(struct pl330_thread *thrd)
966 void __iomem *regs = thrd->dmac->base;
969 if (is_manager(thrd))
970 val = readl(regs + DS) & 0xf;
972 val = readl(regs + CS(thrd->id)) & 0xf;
976 return PL330_STATE_STOPPED;
978 return PL330_STATE_EXECUTING;
980 return PL330_STATE_CACHEMISS;
982 return PL330_STATE_UPDTPC;
984 return PL330_STATE_WFE;
986 return PL330_STATE_FAULTING;
988 if (is_manager(thrd))
989 return PL330_STATE_INVALID;
991 return PL330_STATE_ATBARRIER;
993 if (is_manager(thrd))
994 return PL330_STATE_INVALID;
996 return PL330_STATE_QUEUEBUSY;
998 if (is_manager(thrd))
999 return PL330_STATE_INVALID;
1001 return PL330_STATE_WFP;
1003 if (is_manager(thrd))
1004 return PL330_STATE_INVALID;
1006 return PL330_STATE_KILLING;
1008 if (is_manager(thrd))
1009 return PL330_STATE_INVALID;
1011 return PL330_STATE_COMPLETING;
1013 if (is_manager(thrd))
1014 return PL330_STATE_INVALID;
1016 return PL330_STATE_FAULT_COMPLETING;
1018 return PL330_STATE_INVALID;
1022 static void _stop(struct pl330_thread *thrd)
1024 void __iomem *regs = thrd->dmac->base;
1025 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1027 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
1028 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1030 /* Return if nothing needs to be done */
1031 if (_state(thrd) == PL330_STATE_COMPLETING
1032 || _state(thrd) == PL330_STATE_KILLING
1033 || _state(thrd) == PL330_STATE_STOPPED)
1036 _emit_KILL(0, insn);
1038 /* Stop generating interrupts for SEV */
1039 writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
1041 _execute_DBGINSN(thrd, insn, is_manager(thrd));
1044 /* Start doing req 'idx' of thread 'thrd' */
1045 static bool _trigger(struct pl330_thread *thrd)
1047 void __iomem *regs = thrd->dmac->base;
1048 struct _pl330_req *req;
1049 struct dma_pl330_desc *desc;
1052 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1055 /* Return if already ACTIVE */
1056 if (_state(thrd) != PL330_STATE_STOPPED)
1059 idx = 1 - thrd->lstenq;
1060 if (thrd->req[idx].desc != NULL) {
1061 req = &thrd->req[idx];
1064 if (thrd->req[idx].desc != NULL)
1065 req = &thrd->req[idx];
1070 /* Return if no request */
1074 /* Return if req is running */
1075 if (idx == thrd->req_running)
1080 ns = desc->rqcfg.nonsecure ? 1 : 0;
1082 /* See 'Abort Sources' point-4 at Page 2-25 */
1083 if (_manager_ns(thrd) && !ns)
1084 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
1085 __func__, __LINE__);
1088 go.addr = req->mc_bus;
1090 _emit_GO(0, insn, &go);
1092 /* Set to generate interrupts for SEV */
1093 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1095 /* Only manager can execute GO */
1096 _execute_DBGINSN(thrd, insn, true);
1098 thrd->req_running = idx;
1103 static bool _start(struct pl330_thread *thrd)
1105 switch (_state(thrd)) {
1106 case PL330_STATE_FAULT_COMPLETING:
1107 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1109 if (_state(thrd) == PL330_STATE_KILLING)
1110 UNTIL(thrd, PL330_STATE_STOPPED)
1112 case PL330_STATE_FAULTING:
1115 case PL330_STATE_KILLING:
1116 case PL330_STATE_COMPLETING:
1117 UNTIL(thrd, PL330_STATE_STOPPED)
1119 case PL330_STATE_STOPPED:
1120 return _trigger(thrd);
1122 case PL330_STATE_WFP:
1123 case PL330_STATE_QUEUEBUSY:
1124 case PL330_STATE_ATBARRIER:
1125 case PL330_STATE_UPDTPC:
1126 case PL330_STATE_CACHEMISS:
1127 case PL330_STATE_EXECUTING:
1130 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1136 static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1137 const struct _xfer_spec *pxs, int cyc)
1140 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
1142 /* check lock-up free version */
1143 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1145 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1146 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1150 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1151 off += _emit_RMB(dry_run, &buf[off]);
1152 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1153 off += _emit_WMB(dry_run, &buf[off]);
1160 static inline int _ldst_devtomem(struct pl330_dmac *pl330, unsigned dry_run,
1161 u8 buf[], const struct _xfer_spec *pxs,
1165 enum pl330_cond cond = pl330->peripherals_req_type;
1168 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1169 off += _emit_LDP(dry_run, &buf[off], cond, pxs->desc->peri);
1170 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1172 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1173 off += _emit_FLUSHP(dry_run, &buf[off],
1180 static inline int _ldst_memtodev(struct pl330_dmac *pl330,
1181 unsigned dry_run, u8 buf[],
1182 const struct _xfer_spec *pxs, int cyc)
1185 enum pl330_cond cond = pl330->peripherals_req_type;
1188 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1189 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1190 off += _emit_STP(dry_run, &buf[off], cond, pxs->desc->peri);
1192 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1193 off += _emit_FLUSHP(dry_run, &buf[off],
1200 static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1201 const struct _xfer_spec *pxs, int cyc)
1205 switch (pxs->desc->rqtype) {
1206 case DMA_MEM_TO_DEV:
1207 off += _ldst_memtodev(pl330, dry_run, &buf[off], pxs, cyc);
1209 case DMA_DEV_TO_MEM:
1210 off += _ldst_devtomem(pl330, dry_run, &buf[off], pxs, cyc);
1212 case DMA_MEM_TO_MEM:
1213 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1216 off += 0x40000000; /* Scare off the Client */
1223 /* Returns bytes consumed and updates bursts */
1224 static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1225 unsigned long *bursts, const struct _xfer_spec *pxs)
1227 int cyc, cycmax, szlp, szlpend, szbrst, off;
1228 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1229 struct _arg_LPEND lpend;
1232 return _bursts(pl330, dry_run, buf, pxs, 1);
1234 /* Max iterations possible in DMALP is 256 */
1235 if (*bursts >= 256*256) {
1238 cyc = *bursts / lcnt1 / lcnt0;
1239 } else if (*bursts > 256) {
1241 lcnt0 = *bursts / lcnt1;
1249 szlp = _emit_LP(1, buf, 0, 0);
1250 szbrst = _bursts(pl330, 1, buf, pxs, 1);
1252 lpend.cond = ALWAYS;
1253 lpend.forever = false;
1256 szlpend = _emit_LPEND(1, buf, &lpend);
1264 * Max bursts that we can unroll due to limit on the
1265 * size of backward jump that can be encoded in DMALPEND
1266 * which is 8-bits and hence 255
1268 cycmax = (255 - (szlp + szlpend)) / szbrst;
1270 cyc = (cycmax < cyc) ? cycmax : cyc;
1275 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1279 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1282 off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
1284 lpend.cond = ALWAYS;
1285 lpend.forever = false;
1287 lpend.bjump = off - ljmp1;
1288 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1291 lpend.cond = ALWAYS;
1292 lpend.forever = false;
1294 lpend.bjump = off - ljmp0;
1295 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1298 *bursts = lcnt1 * cyc;
1305 static inline int _setup_loops(struct pl330_dmac *pl330,
1306 unsigned dry_run, u8 buf[],
1307 const struct _xfer_spec *pxs)
1309 struct pl330_xfer *x = &pxs->desc->px;
1311 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1316 off += _loop(pl330, dry_run, &buf[off], &c, pxs);
1323 static inline int _setup_xfer(struct pl330_dmac *pl330,
1324 unsigned dry_run, u8 buf[],
1325 const struct _xfer_spec *pxs)
1327 struct pl330_xfer *x = &pxs->desc->px;
1330 /* DMAMOV SAR, x->src_addr */
1331 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1332 /* DMAMOV DAR, x->dst_addr */
1333 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1336 off += _setup_loops(pl330, dry_run, &buf[off], pxs);
1338 if (pl330->peripherals_req_type == BURST) {
1339 unsigned int ccr = pxs->ccr;
1340 unsigned long c = 0;
1342 c = BYTE_MOD_BURST_LEN(x->bytes, pxs->ccr);
1345 ccr &= ~(0xf << CC_SRCBRSTLEN_SHFT);
1346 ccr &= ~(0xf << CC_DSTBRSTLEN_SHFT);
1347 off += _emit_MOV(dry_run, &buf[off], CCR, ccr);
1348 off += _loop(pl330, dry_run, &buf[off], &c, pxs);
1356 * A req is a sequence of one or more xfer units.
1357 * Returns the number of bytes taken to setup the MC for the req.
1359 static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
1360 struct pl330_thread *thrd, unsigned index,
1361 struct _xfer_spec *pxs)
1363 struct _pl330_req *req = &thrd->req[index];
1364 struct pl330_xfer *x;
1365 u8 *buf = req->mc_cpu;
1368 PL330_DBGMC_START(req->mc_bus);
1370 /* DMAMOV CCR, ccr */
1371 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1374 if (pl330->peripherals_req_type != BURST) {
1375 /* Error if xfer length is not aligned at burst size */
1376 if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1380 off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
1382 /* DMASEV peripheral/event */
1383 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1385 off += _emit_END(dry_run, &buf[off]);
1390 static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1400 /* We set same protection levels for Src and DST for now */
1401 if (rqc->privileged)
1402 ccr |= CC_SRCPRI | CC_DSTPRI;
1404 ccr |= CC_SRCNS | CC_DSTNS;
1405 if (rqc->insnaccess)
1406 ccr |= CC_SRCIA | CC_DSTIA;
1408 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1409 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1411 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1412 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1414 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1415 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1417 ccr |= (rqc->swap << CC_SWAP_SHFT);
1423 * Submit a list of xfers after which the client wants notification.
1424 * Client is not notified after each xfer unit, just once after all
1425 * xfer units are done or some error occurs.
1427 static int pl330_submit_req(struct pl330_thread *thrd,
1428 struct dma_pl330_desc *desc)
1430 struct pl330_dmac *pl330 = thrd->dmac;
1431 struct _xfer_spec xs;
1432 unsigned long flags;
1437 if (pl330->state == DYING
1438 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1439 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
1440 __func__, __LINE__);
1444 /* If request for non-existing peripheral */
1445 if (desc->rqtype != DMA_MEM_TO_MEM &&
1446 desc->peri >= pl330->pcfg.num_peri) {
1447 dev_info(thrd->dmac->ddma.dev,
1448 "%s:%d Invalid peripheral(%u)!\n",
1449 __func__, __LINE__, desc->peri);
1453 spin_lock_irqsave(&pl330->lock, flags);
1455 if (_queue_full(thrd)) {
1460 /* Prefer Secure Channel */
1461 if (!_manager_ns(thrd))
1462 desc->rqcfg.nonsecure = 0;
1464 desc->rqcfg.nonsecure = 1;
1466 ccr = _prepare_ccr(&desc->rqcfg);
1468 idx = thrd->req[0].desc == NULL ? 0 : 1;
1473 /* First dry run to check if req is acceptable */
1474 ret = _setup_req(pl330, 1, thrd, idx, &xs);
1478 if (ret > pl330->mcbufsz / 2) {
1479 dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1480 __func__, __LINE__, ret, pl330->mcbufsz / 2);
1485 /* Hook the request */
1487 thrd->req[idx].desc = desc;
1488 _setup_req(pl330, 0, thrd, idx, &xs);
1493 spin_unlock_irqrestore(&pl330->lock, flags);
1498 static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
1500 struct dma_pl330_chan *pch;
1501 unsigned long flags;
1508 /* If desc aborted */
1512 spin_lock_irqsave(&pch->lock, flags);
1514 desc->status = DONE;
1516 spin_unlock_irqrestore(&pch->lock, flags);
1518 tasklet_schedule(&pch->task);
1521 static void pl330_dotask(unsigned long data)
1523 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1524 unsigned long flags;
1527 spin_lock_irqsave(&pl330->lock, flags);
1529 /* The DMAC itself gone nuts */
1530 if (pl330->dmac_tbd.reset_dmac) {
1531 pl330->state = DYING;
1532 /* Reset the manager too */
1533 pl330->dmac_tbd.reset_mngr = true;
1534 /* Clear the reset flag */
1535 pl330->dmac_tbd.reset_dmac = false;
1538 if (pl330->dmac_tbd.reset_mngr) {
1539 _stop(pl330->manager);
1540 /* Reset all channels */
1541 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
1542 /* Clear the reset flag */
1543 pl330->dmac_tbd.reset_mngr = false;
1546 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1548 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1549 struct pl330_thread *thrd = &pl330->channels[i];
1550 void __iomem *regs = pl330->base;
1551 enum pl330_op_err err;
1555 if (readl(regs + FSC) & (1 << thrd->id))
1556 err = PL330_ERR_FAIL;
1558 err = PL330_ERR_ABORT;
1560 spin_unlock_irqrestore(&pl330->lock, flags);
1561 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1562 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
1563 spin_lock_irqsave(&pl330->lock, flags);
1565 thrd->req[0].desc = NULL;
1566 thrd->req[1].desc = NULL;
1567 thrd->req_running = -1;
1569 /* Clear the reset flag */
1570 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1574 spin_unlock_irqrestore(&pl330->lock, flags);
1579 /* Returns 1 if state was updated, 0 otherwise */
1580 static int pl330_update(struct pl330_dmac *pl330)
1582 struct dma_pl330_desc *descdone, *tmp;
1583 unsigned long flags;
1586 int id, ev, ret = 0;
1590 spin_lock_irqsave(&pl330->lock, flags);
1592 val = readl(regs + FSM) & 0x1;
1594 pl330->dmac_tbd.reset_mngr = true;
1596 pl330->dmac_tbd.reset_mngr = false;
1598 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
1599 pl330->dmac_tbd.reset_chan |= val;
1602 while (i < pl330->pcfg.num_chan) {
1603 if (val & (1 << i)) {
1604 dev_info(pl330->ddma.dev,
1605 "Reset Channel-%d\t CS-%x FTC-%x\n",
1606 i, readl(regs + CS(i)),
1607 readl(regs + FTC(i)));
1608 _stop(&pl330->channels[i]);
1614 /* Check which event happened i.e, thread notified */
1615 val = readl(regs + ES);
1616 if (pl330->pcfg.num_events < 32
1617 && val & ~((1 << pl330->pcfg.num_events) - 1)) {
1618 pl330->dmac_tbd.reset_dmac = true;
1619 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1625 for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
1626 if (val & (1 << ev)) { /* Event occurred */
1627 struct pl330_thread *thrd;
1628 u32 inten = readl(regs + INTEN);
1631 /* Clear the event */
1632 if (inten & (1 << ev))
1633 writel(1 << ev, regs + INTCLR);
1637 id = pl330->events[ev];
1639 thrd = &pl330->channels[id];
1641 active = thrd->req_running;
1642 if (active == -1) /* Aborted */
1645 /* Detach the req */
1646 descdone = thrd->req[active].desc;
1647 thrd->req[active].desc = NULL;
1649 thrd->req_running = -1;
1651 /* Get going again ASAP */
1654 /* For now, just make a list of callbacks to be done */
1655 list_add_tail(&descdone->rqd, &pl330->req_done);
1659 /* Now that we are in no hurry, do the callbacks */
1660 list_for_each_entry_safe(descdone, tmp, &pl330->req_done, rqd) {
1661 list_del(&descdone->rqd);
1662 spin_unlock_irqrestore(&pl330->lock, flags);
1663 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
1664 spin_lock_irqsave(&pl330->lock, flags);
1668 spin_unlock_irqrestore(&pl330->lock, flags);
1670 if (pl330->dmac_tbd.reset_dmac
1671 || pl330->dmac_tbd.reset_mngr
1672 || pl330->dmac_tbd.reset_chan) {
1674 tasklet_schedule(&pl330->tasks);
1680 /* Reserve an event */
1681 static inline int _alloc_event(struct pl330_thread *thrd)
1683 struct pl330_dmac *pl330 = thrd->dmac;
1686 for (ev = 0; ev < pl330->pcfg.num_events; ev++)
1687 if (pl330->events[ev] == -1) {
1688 pl330->events[ev] = thrd->id;
1695 static bool _chan_ns(const struct pl330_dmac *pl330, int i)
1697 return pl330->pcfg.irq_ns & (1 << i);
1700 /* Upon success, returns IdentityToken for the
1701 * allocated channel, NULL otherwise.
1703 static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
1705 struct pl330_thread *thrd = NULL;
1706 unsigned long flags;
1709 if (pl330->state == DYING)
1712 chans = pl330->pcfg.num_chan;
1714 spin_lock_irqsave(&pl330->lock, flags);
1716 for (i = 0; i < chans; i++) {
1717 thrd = &pl330->channels[i];
1718 if ((thrd->free) && (!_manager_ns(thrd) ||
1719 _chan_ns(pl330, i))) {
1720 thrd->ev = _alloc_event(thrd);
1721 if (thrd->ev >= 0) {
1724 thrd->req[0].desc = NULL;
1725 thrd->req[1].desc = NULL;
1726 thrd->req_running = -1;
1733 spin_unlock_irqrestore(&pl330->lock, flags);
1738 /* Release an event */
1739 static inline void _free_event(struct pl330_thread *thrd, int ev)
1741 struct pl330_dmac *pl330 = thrd->dmac;
1743 /* If the event is valid and was held by the thread */
1744 if (ev >= 0 && ev < pl330->pcfg.num_events
1745 && pl330->events[ev] == thrd->id)
1746 pl330->events[ev] = -1;
1749 static void pl330_release_channel(struct pl330_thread *thrd)
1751 struct pl330_dmac *pl330;
1752 unsigned long flags;
1754 if (!thrd || thrd->free)
1759 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1760 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
1764 spin_lock_irqsave(&pl330->lock, flags);
1765 _free_event(thrd, thrd->ev);
1767 spin_unlock_irqrestore(&pl330->lock, flags);
1770 /* Initialize the structure for PL330 configuration, that can be used
1771 * by the client driver the make best use of the DMAC
1773 static void read_dmac_config(struct pl330_dmac *pl330)
1775 void __iomem *regs = pl330->base;
1778 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1779 val &= CRD_DATA_WIDTH_MASK;
1780 pl330->pcfg.data_bus_width = 8 * (1 << val);
1782 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1783 val &= CRD_DATA_BUFF_MASK;
1784 pl330->pcfg.data_buf_dep = val + 1;
1786 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1787 val &= CR0_NUM_CHANS_MASK;
1789 pl330->pcfg.num_chan = val;
1791 val = readl(regs + CR0);
1792 if (val & CR0_PERIPH_REQ_SET) {
1793 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1795 pl330->pcfg.num_peri = val;
1796 pl330->pcfg.peri_ns = readl(regs + CR4);
1798 pl330->pcfg.num_peri = 0;
1801 val = readl(regs + CR0);
1802 if (val & CR0_BOOT_MAN_NS)
1803 pl330->pcfg.mode |= DMAC_MODE_NS;
1805 pl330->pcfg.mode &= ~DMAC_MODE_NS;
1807 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1808 val &= CR0_NUM_EVENTS_MASK;
1810 pl330->pcfg.num_events = val;
1812 pl330->pcfg.irq_ns = readl(regs + CR3);
1815 static inline void _reset_thread(struct pl330_thread *thrd)
1817 struct pl330_dmac *pl330 = thrd->dmac;
1819 thrd->req[0].mc_cpu = pl330->mcode_cpu
1820 + (thrd->id * pl330->mcbufsz);
1821 thrd->req[0].mc_bus = pl330->mcode_bus
1822 + (thrd->id * pl330->mcbufsz);
1823 thrd->req[0].desc = NULL;
1825 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1826 + pl330->mcbufsz / 2;
1827 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1828 + pl330->mcbufsz / 2;
1829 thrd->req[1].desc = NULL;
1831 thrd->req_running = -1;
1834 static int dmac_alloc_threads(struct pl330_dmac *pl330)
1836 int chans = pl330->pcfg.num_chan;
1837 struct pl330_thread *thrd;
1840 /* Allocate 1 Manager and 'chans' Channel threads */
1841 pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
1843 if (!pl330->channels)
1846 /* Init Channel threads */
1847 for (i = 0; i < chans; i++) {
1848 thrd = &pl330->channels[i];
1851 _reset_thread(thrd);
1855 /* MANAGER is indexed at the end */
1856 thrd = &pl330->channels[chans];
1860 pl330->manager = thrd;
1865 static int dmac_alloc_resources(struct pl330_dmac *pl330)
1867 int chans = pl330->pcfg.num_chan;
1871 * Alloc MicroCode buffer for 'chans' Channel threads.
1872 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1874 pl330->mcode_cpu = dma_alloc_coherent(pl330->ddma.dev,
1875 chans * pl330->mcbufsz,
1876 &pl330->mcode_bus, GFP_KERNEL);
1877 if (!pl330->mcode_cpu) {
1878 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
1879 __func__, __LINE__);
1883 ret = dmac_alloc_threads(pl330);
1885 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
1886 __func__, __LINE__);
1887 dma_free_coherent(pl330->ddma.dev,
1888 chans * pl330->mcbufsz,
1889 pl330->mcode_cpu, pl330->mcode_bus);
1896 static int pl330_add(struct pl330_dmac *pl330)
1903 /* Check if we can handle this DMAC */
1904 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1905 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1906 pl330->pcfg.periph_id);
1910 /* Read the configuration of the DMAC */
1911 read_dmac_config(pl330);
1913 if (pl330->pcfg.num_events == 0) {
1914 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
1915 __func__, __LINE__);
1919 spin_lock_init(&pl330->lock);
1921 INIT_LIST_HEAD(&pl330->req_done);
1923 /* Use default MC buffer size if not provided */
1924 if (!pl330->mcbufsz)
1925 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
1927 /* Mark all events as free */
1928 for (i = 0; i < pl330->pcfg.num_events; i++)
1929 pl330->events[i] = -1;
1931 /* Allocate resources needed by the DMAC */
1932 ret = dmac_alloc_resources(pl330);
1934 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
1938 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
1940 pl330->state = INIT;
1945 static int dmac_free_threads(struct pl330_dmac *pl330)
1947 struct pl330_thread *thrd;
1950 /* Release Channel threads */
1951 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1952 thrd = &pl330->channels[i];
1953 pl330_release_channel(thrd);
1957 kfree(pl330->channels);
1962 static void pl330_del(struct pl330_dmac *pl330)
1964 pl330->state = UNINIT;
1966 tasklet_kill(&pl330->tasks);
1968 /* Free DMAC resources */
1969 dmac_free_threads(pl330);
1971 dma_free_coherent(pl330->ddma.dev,
1972 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
1976 /* forward declaration */
1977 static struct amba_driver pl330_driver;
1979 static inline struct dma_pl330_chan *
1980 to_pchan(struct dma_chan *ch)
1985 return container_of(ch, struct dma_pl330_chan, chan);
1988 static inline struct dma_pl330_desc *
1989 to_desc(struct dma_async_tx_descriptor *tx)
1991 return container_of(tx, struct dma_pl330_desc, txd);
1994 static inline void fill_queue(struct dma_pl330_chan *pch)
1996 struct dma_pl330_desc *desc;
1999 list_for_each_entry(desc, &pch->work_list, node) {
2001 /* If already submitted */
2002 if (desc->status == BUSY)
2005 ret = pl330_submit_req(pch->thread, desc);
2007 desc->status = BUSY;
2008 } else if (ret == -EAGAIN) {
2009 /* QFull or DMAC Dying */
2012 /* Unacceptable request */
2013 desc->status = DONE;
2014 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
2015 __func__, __LINE__, desc->txd.cookie);
2016 tasklet_schedule(&pch->task);
2021 static void pl330_tasklet(unsigned long data)
2023 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
2024 struct dma_pl330_desc *desc, *_dt;
2025 unsigned long flags;
2026 bool power_down = false;
2028 spin_lock_irqsave(&pch->lock, flags);
2030 /* Pick up ripe tomatoes */
2031 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2032 if (desc->status == DONE) {
2034 dma_cookie_complete(&desc->txd);
2035 list_move_tail(&desc->node, &pch->completed_list);
2038 /* Try to submit a req imm. next to the last completed cookie */
2041 if (list_empty(&pch->work_list)) {
2042 spin_lock(&pch->thread->dmac->lock);
2044 spin_unlock(&pch->thread->dmac->lock);
2046 pch->active = false;
2048 /* Make sure the PL330 Channel thread is active */
2049 spin_lock(&pch->thread->dmac->lock);
2050 _start(pch->thread);
2051 spin_unlock(&pch->thread->dmac->lock);
2054 while (!list_empty(&pch->completed_list)) {
2055 dma_async_tx_callback callback;
2056 void *callback_param;
2058 desc = list_first_entry(&pch->completed_list,
2059 struct dma_pl330_desc, node);
2061 callback = desc->txd.callback;
2062 callback_param = desc->txd.callback_param;
2065 desc->status = PREP;
2066 list_move_tail(&desc->node, &pch->work_list);
2069 spin_lock(&pch->thread->dmac->lock);
2070 _start(pch->thread);
2071 spin_unlock(&pch->thread->dmac->lock);
2075 desc->status = FREE;
2076 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2079 dma_descriptor_unmap(&desc->txd);
2082 spin_unlock_irqrestore(&pch->lock, flags);
2083 callback(callback_param);
2084 spin_lock_irqsave(&pch->lock, flags);
2087 spin_unlock_irqrestore(&pch->lock, flags);
2089 /* If work list empty, power down */
2091 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2092 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2096 bool pl330_filter(struct dma_chan *chan, void *param)
2100 if (chan->device->dev->driver != &pl330_driver.drv)
2103 peri_id = chan->private;
2104 return *peri_id == (unsigned long)param;
2106 EXPORT_SYMBOL(pl330_filter);
2108 static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2109 struct of_dma *ofdma)
2111 int count = dma_spec->args_count;
2112 struct pl330_dmac *pl330 = ofdma->of_dma_data;
2113 unsigned int chan_id;
2121 chan_id = dma_spec->args[0];
2122 if (chan_id >= pl330->num_peripherals)
2125 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
2128 static int pl330_alloc_chan_resources(struct dma_chan *chan)
2130 struct dma_pl330_chan *pch = to_pchan(chan);
2131 struct pl330_dmac *pl330 = pch->dmac;
2132 unsigned long flags;
2134 spin_lock_irqsave(&pch->lock, flags);
2136 dma_cookie_init(chan);
2137 pch->cyclic = false;
2139 pch->thread = pl330_request_channel(pl330);
2141 spin_unlock_irqrestore(&pch->lock, flags);
2145 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2147 spin_unlock_irqrestore(&pch->lock, flags);
2152 static int pl330_config(struct dma_chan *chan,
2153 struct dma_slave_config *slave_config)
2155 struct dma_pl330_chan *pch = to_pchan(chan);
2157 if (slave_config->direction == DMA_MEM_TO_DEV) {
2158 if (slave_config->dst_addr)
2159 pch->fifo_addr = slave_config->dst_addr;
2160 if (slave_config->dst_addr_width)
2161 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2162 if (slave_config->dst_maxburst)
2163 pch->burst_len = slave_config->dst_maxburst;
2164 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
2165 if (slave_config->src_addr)
2166 pch->fifo_addr = slave_config->src_addr;
2167 if (slave_config->src_addr_width)
2168 pch->burst_sz = __ffs(slave_config->src_addr_width);
2169 if (slave_config->src_maxburst)
2170 pch->burst_len = slave_config->src_maxburst;
2176 static int pl330_terminate_all(struct dma_chan *chan)
2178 struct dma_pl330_chan *pch = to_pchan(chan);
2179 struct dma_pl330_desc *desc;
2180 unsigned long flags;
2181 struct pl330_dmac *pl330 = pch->dmac;
2183 bool power_down = false;
2185 pm_runtime_get_sync(pl330->ddma.dev);
2186 spin_lock_irqsave(&pch->lock, flags);
2187 spin_lock(&pl330->lock);
2189 spin_unlock(&pl330->lock);
2191 pch->thread->req[0].desc = NULL;
2192 pch->thread->req[1].desc = NULL;
2193 pch->thread->req_running = -1;
2194 power_down = pch->active;
2195 pch->active = false;
2197 /* Mark all desc done */
2198 list_for_each_entry(desc, &pch->submitted_list, node) {
2199 desc->status = FREE;
2200 dma_cookie_complete(&desc->txd);
2203 list_for_each_entry(desc, &pch->work_list , node) {
2204 desc->status = FREE;
2205 dma_cookie_complete(&desc->txd);
2208 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2209 list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2210 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2211 spin_unlock_irqrestore(&pch->lock, flags);
2212 pm_runtime_mark_last_busy(pl330->ddma.dev);
2214 pm_runtime_put_autosuspend(pl330->ddma.dev);
2215 pm_runtime_put_autosuspend(pl330->ddma.dev);
2221 * We don't support DMA_RESUME command because of hardware
2222 * limitations, so after pausing the channel we cannot restore
2223 * it to active state. We have to terminate channel and setup
2224 * DMA transfer again. This pause feature was implemented to
2225 * allow safely read residue before channel termination.
2227 static int pl330_pause(struct dma_chan *chan)
2229 struct dma_pl330_chan *pch = to_pchan(chan);
2230 struct pl330_dmac *pl330 = pch->dmac;
2231 unsigned long flags;
2233 pm_runtime_get_sync(pl330->ddma.dev);
2234 spin_lock_irqsave(&pch->lock, flags);
2236 spin_lock(&pl330->lock);
2238 spin_unlock(&pl330->lock);
2240 spin_unlock_irqrestore(&pch->lock, flags);
2241 pm_runtime_mark_last_busy(pl330->ddma.dev);
2242 pm_runtime_put_autosuspend(pl330->ddma.dev);
2247 static void pl330_free_chan_resources(struct dma_chan *chan)
2249 struct dma_pl330_chan *pch = to_pchan(chan);
2250 unsigned long flags;
2252 tasklet_kill(&pch->task);
2254 pm_runtime_get_sync(pch->dmac->ddma.dev);
2255 spin_lock_irqsave(&pch->lock, flags);
2257 pl330_release_channel(pch->thread);
2261 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2263 spin_unlock_irqrestore(&pch->lock, flags);
2264 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2265 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2268 static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
2269 struct dma_pl330_desc *desc)
2271 struct pl330_thread *thrd = pch->thread;
2272 struct pl330_dmac *pl330 = pch->dmac;
2273 void __iomem *regs = thrd->dmac->base;
2276 pm_runtime_get_sync(pl330->ddma.dev);
2278 if (desc->rqcfg.src_inc) {
2279 val = readl(regs + SA(thrd->id));
2280 addr = desc->px.src_addr;
2282 val = readl(regs + DA(thrd->id));
2283 addr = desc->px.dst_addr;
2285 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2286 pm_runtime_put_autosuspend(pl330->ddma.dev);
2290 static enum dma_status
2291 pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2292 struct dma_tx_state *txstate)
2294 enum dma_status ret;
2295 unsigned long flags;
2296 struct dma_pl330_desc *desc, *running = NULL;
2297 struct dma_pl330_chan *pch = to_pchan(chan);
2298 unsigned int transferred, residual = 0;
2300 ret = dma_cookie_status(chan, cookie, txstate);
2305 if (ret == DMA_COMPLETE)
2308 spin_lock_irqsave(&pch->lock, flags);
2310 if (pch->thread->req_running != -1)
2311 running = pch->thread->req[pch->thread->req_running].desc;
2313 /* Check in pending list */
2314 list_for_each_entry(desc, &pch->work_list, node) {
2315 if (desc->status == DONE)
2316 transferred = desc->bytes_requested;
2317 else if (running && desc == running)
2319 pl330_get_current_xferred_count(pch, desc);
2322 residual += desc->bytes_requested - transferred;
2323 if (desc->txd.cookie == cookie) {
2324 switch (desc->status) {
2330 ret = DMA_IN_PROGRESS;
2340 spin_unlock_irqrestore(&pch->lock, flags);
2343 dma_set_residue(txstate, residual);
2348 static void pl330_issue_pending(struct dma_chan *chan)
2350 struct dma_pl330_chan *pch = to_pchan(chan);
2351 unsigned long flags;
2353 spin_lock_irqsave(&pch->lock, flags);
2354 if (list_empty(&pch->work_list)) {
2356 * Warn on nothing pending. Empty submitted_list may
2357 * break our pm_runtime usage counter as it is
2358 * updated on work_list emptiness status.
2360 WARN_ON(list_empty(&pch->submitted_list));
2362 pm_runtime_get_sync(pch->dmac->ddma.dev);
2364 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2365 spin_unlock_irqrestore(&pch->lock, flags);
2367 pl330_tasklet((unsigned long)pch);
2371 * We returned the last one of the circular list of descriptor(s)
2372 * from prep_xxx, so the argument to submit corresponds to the last
2373 * descriptor of the list.
2375 static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2377 struct dma_pl330_desc *desc, *last = to_desc(tx);
2378 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2379 dma_cookie_t cookie;
2380 unsigned long flags;
2382 spin_lock_irqsave(&pch->lock, flags);
2384 /* Assign cookies to all nodes */
2385 while (!list_empty(&last->node)) {
2386 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2388 desc->txd.callback = last->txd.callback;
2389 desc->txd.callback_param = last->txd.callback_param;
2393 dma_cookie_assign(&desc->txd);
2395 list_move_tail(&desc->node, &pch->submitted_list);
2399 cookie = dma_cookie_assign(&last->txd);
2400 list_add_tail(&last->node, &pch->submitted_list);
2401 spin_unlock_irqrestore(&pch->lock, flags);
2406 static inline void _init_desc(struct dma_pl330_desc *desc)
2408 desc->rqcfg.swap = SWAP_NO;
2409 desc->rqcfg.scctl = CCTRL0;
2410 desc->rqcfg.dcctl = CCTRL0;
2411 desc->txd.tx_submit = pl330_tx_submit;
2413 INIT_LIST_HEAD(&desc->node);
2416 /* Returns the number of descriptors added to the DMAC pool */
2417 static int add_desc(struct pl330_dmac *pl330, gfp_t flg, int count)
2419 struct dma_pl330_desc *desc;
2420 unsigned long flags;
2423 desc = kcalloc(count, sizeof(*desc), flg);
2427 spin_lock_irqsave(&pl330->pool_lock, flags);
2429 for (i = 0; i < count; i++) {
2430 _init_desc(&desc[i]);
2431 list_add_tail(&desc[i].node, &pl330->desc_pool);
2434 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2439 static struct dma_pl330_desc *pluck_desc(struct pl330_dmac *pl330)
2441 struct dma_pl330_desc *desc = NULL;
2442 unsigned long flags;
2444 spin_lock_irqsave(&pl330->pool_lock, flags);
2446 if (!list_empty(&pl330->desc_pool)) {
2447 desc = list_entry(pl330->desc_pool.next,
2448 struct dma_pl330_desc, node);
2450 list_del_init(&desc->node);
2452 desc->status = PREP;
2453 desc->txd.callback = NULL;
2456 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2461 static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2463 struct pl330_dmac *pl330 = pch->dmac;
2464 u8 *peri_id = pch->chan.private;
2465 struct dma_pl330_desc *desc;
2467 /* Pluck one desc from the pool of DMAC */
2468 desc = pluck_desc(pl330);
2470 /* If the DMAC pool is empty, alloc new */
2472 if (!add_desc(pl330, GFP_ATOMIC, 1))
2476 desc = pluck_desc(pl330);
2478 dev_err(pch->dmac->ddma.dev,
2479 "%s:%d ALERT!\n", __func__, __LINE__);
2484 /* Initialize the descriptor */
2486 desc->txd.cookie = 0;
2487 async_tx_ack(&desc->txd);
2489 desc->peri = peri_id ? pch->chan.chan_id : 0;
2490 desc->rqcfg.pcfg = &pch->dmac->pcfg;
2492 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2497 static inline void fill_px(struct pl330_xfer *px,
2498 dma_addr_t dst, dma_addr_t src, size_t len)
2505 static struct dma_pl330_desc *
2506 __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2507 dma_addr_t src, size_t len)
2509 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2512 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2513 __func__, __LINE__);
2518 * Ideally we should lookout for reqs bigger than
2519 * those that can be programmed with 256 bytes of
2520 * MC buffer, but considering a req size is seldom
2521 * going to be word-unaligned and more than 200MB,
2523 * Also, should the limit is reached we'd rather
2524 * have the platform increase MC buffer size than
2525 * complicating this API driver.
2527 fill_px(&desc->px, dst, src, len);
2532 /* Call after fixing burst size */
2533 static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2535 struct dma_pl330_chan *pch = desc->pchan;
2536 struct pl330_dmac *pl330 = pch->dmac;
2539 burst_len = pl330->pcfg.data_bus_width / 8;
2540 burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
2541 burst_len >>= desc->rqcfg.brst_size;
2543 /* src/dst_burst_len can't be more than 16 */
2547 while (burst_len > 1) {
2548 if (!(len % (burst_len << desc->rqcfg.brst_size)))
2556 static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2557 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2558 size_t period_len, enum dma_transfer_direction direction,
2559 unsigned long flags)
2561 struct dma_pl330_desc *desc = NULL, *first = NULL;
2562 struct dma_pl330_chan *pch = to_pchan(chan);
2563 struct pl330_dmac *pl330 = pch->dmac;
2568 if (len % period_len != 0)
2571 if (!is_slave_direction(direction)) {
2572 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
2573 __func__, __LINE__);
2577 for (i = 0; i < len / period_len; i++) {
2578 desc = pl330_get_desc(pch);
2580 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2581 __func__, __LINE__);
2586 spin_lock_irqsave(&pl330->pool_lock, flags);
2588 while (!list_empty(&first->node)) {
2589 desc = list_entry(first->node.next,
2590 struct dma_pl330_desc, node);
2591 list_move_tail(&desc->node, &pl330->desc_pool);
2594 list_move_tail(&first->node, &pl330->desc_pool);
2596 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2601 switch (direction) {
2602 case DMA_MEM_TO_DEV:
2603 desc->rqcfg.src_inc = 1;
2604 desc->rqcfg.dst_inc = 0;
2606 dst = pch->fifo_addr;
2608 case DMA_DEV_TO_MEM:
2609 desc->rqcfg.src_inc = 0;
2610 desc->rqcfg.dst_inc = 1;
2611 src = pch->fifo_addr;
2618 desc->rqtype = direction;
2619 desc->rqcfg.brst_size = pch->burst_sz;
2621 if (pl330->peripherals_req_type == BURST)
2622 desc->rqcfg.brst_len = pch->burst_len;
2624 desc->rqcfg.brst_len = 1;
2626 desc->bytes_requested = period_len;
2627 fill_px(&desc->px, dst, src, period_len);
2632 list_add_tail(&desc->node, &first->node);
2634 dma_addr += period_len;
2641 desc->txd.flags = flags;
2646 static struct dma_async_tx_descriptor *
2647 pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2648 dma_addr_t src, size_t len, unsigned long flags)
2650 struct dma_pl330_desc *desc;
2651 struct dma_pl330_chan *pch = to_pchan(chan);
2652 struct pl330_dmac *pl330;
2655 if (unlikely(!pch || !len))
2660 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2664 desc->rqcfg.src_inc = 1;
2665 desc->rqcfg.dst_inc = 1;
2666 desc->rqtype = DMA_MEM_TO_MEM;
2668 /* Select max possible burst size */
2669 burst = pl330->pcfg.data_bus_width / 8;
2672 * Make sure we use a burst size that aligns with all the memcpy
2673 * parameters because our DMA programming algorithm doesn't cope with
2674 * transfers which straddle an entry in the DMA device's MFIFO.
2676 while ((src | dst | len) & (burst - 1))
2679 desc->rqcfg.brst_size = 0;
2680 while (burst != (1 << desc->rqcfg.brst_size))
2681 desc->rqcfg.brst_size++;
2684 * If burst size is smaller than bus width then make sure we only
2685 * transfer one at a time to avoid a burst stradling an MFIFO entry.
2687 if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)
2688 desc->rqcfg.brst_len = 1;
2690 desc->rqcfg.brst_len = get_burst_len(desc, len);
2691 desc->bytes_requested = len;
2693 desc->txd.flags = flags;
2698 static void __pl330_giveback_desc(struct pl330_dmac *pl330,
2699 struct dma_pl330_desc *first)
2701 unsigned long flags;
2702 struct dma_pl330_desc *desc;
2707 spin_lock_irqsave(&pl330->pool_lock, flags);
2709 while (!list_empty(&first->node)) {
2710 desc = list_entry(first->node.next,
2711 struct dma_pl330_desc, node);
2712 list_move_tail(&desc->node, &pl330->desc_pool);
2715 list_move_tail(&first->node, &pl330->desc_pool);
2717 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2720 static struct dma_async_tx_descriptor *
2721 pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2722 unsigned int sg_len, enum dma_transfer_direction direction,
2723 unsigned long flg, void *context)
2725 struct dma_pl330_desc *first, *desc = NULL;
2726 struct dma_pl330_chan *pch = to_pchan(chan);
2727 struct pl330_dmac *pl330 = pch->dmac;
2728 struct scatterlist *sg;
2732 if (unlikely(!pch || !sgl || !sg_len))
2735 addr = pch->fifo_addr;
2739 for_each_sg(sgl, sg, sg_len, i) {
2741 desc = pl330_get_desc(pch);
2743 struct pl330_dmac *pl330 = pch->dmac;
2745 dev_err(pch->dmac->ddma.dev,
2746 "%s:%d Unable to fetch desc\n",
2747 __func__, __LINE__);
2748 __pl330_giveback_desc(pl330, first);
2756 list_add_tail(&desc->node, &first->node);
2758 if (direction == DMA_MEM_TO_DEV) {
2759 desc->rqcfg.src_inc = 1;
2760 desc->rqcfg.dst_inc = 0;
2762 addr, sg_dma_address(sg), sg_dma_len(sg));
2764 desc->rqcfg.src_inc = 0;
2765 desc->rqcfg.dst_inc = 1;
2767 sg_dma_address(sg), addr, sg_dma_len(sg));
2770 desc->rqcfg.brst_size = pch->burst_sz;
2772 if (pl330->peripherals_req_type == BURST)
2773 desc->rqcfg.brst_len = pch->burst_len;
2775 desc->rqcfg.brst_len = 1;
2777 desc->rqtype = direction;
2778 desc->bytes_requested = sg_dma_len(sg);
2781 /* Return the last desc in the chain */
2782 desc->txd.flags = flg;
2786 static irqreturn_t pl330_irq_handler(int irq, void *data)
2788 if (pl330_update(data))
2794 #define PL330_DMA_BUSWIDTHS \
2795 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2796 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2797 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2798 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2799 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2802 * Runtime PM callbacks are provided by amba/bus.c driver.
2804 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2805 * bus driver will only disable/enable the clock in runtime PM callbacks.
2807 static int __maybe_unused pl330_suspend(struct device *dev)
2809 struct amba_device *pcdev = to_amba_device(dev);
2811 pm_runtime_disable(dev);
2813 if (!pm_runtime_status_suspended(dev)) {
2814 /* amba did not disable the clock */
2815 amba_pclk_disable(pcdev);
2817 amba_pclk_unprepare(pcdev);
2822 static int __maybe_unused pl330_resume(struct device *dev)
2824 struct amba_device *pcdev = to_amba_device(dev);
2827 ret = amba_pclk_prepare(pcdev);
2831 if (!pm_runtime_status_suspended(dev))
2832 ret = amba_pclk_enable(pcdev);
2834 pm_runtime_enable(dev);
2839 static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume);
2842 pl330_probe(struct amba_device *adev, const struct amba_id *id)
2844 struct dma_pl330_platdata *pdat;
2845 struct pl330_config *pcfg;
2846 struct pl330_dmac *pl330;
2847 struct dma_pl330_chan *pch, *_p;
2848 struct dma_device *pd;
2849 struct resource *res;
2852 struct device_node *np = adev->dev.of_node;
2854 pdat = dev_get_platdata(&adev->dev);
2856 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
2860 /* Allocate a new DMAC and its Channels */
2861 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
2863 dev_err(&adev->dev, "unable to allocate mem\n");
2868 pd->dev = &adev->dev;
2870 pl330->mcbufsz = pdat ? pdat->mcbuf_sz : 0;
2872 if (of_find_property(np, "peripherals-req-type-burst", NULL))
2873 pl330->peripherals_req_type = BURST;
2875 pl330->peripherals_req_type = SINGLE;
2878 for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
2879 if (of_property_read_bool(np, of_quirks[i].quirk))
2880 pl330->quirks |= of_quirks[i].id;
2883 pl330->base = devm_ioremap_resource(&adev->dev, res);
2884 if (IS_ERR(pl330->base))
2885 return PTR_ERR(pl330->base);
2887 amba_set_drvdata(adev, pl330);
2889 for (i = 0; i < AMBA_NR_IRQS; i++) {
2892 ret = devm_request_irq(&adev->dev, irq,
2893 pl330_irq_handler, 0,
2894 dev_name(&adev->dev), pl330);
2902 pcfg = &pl330->pcfg;
2904 pcfg->periph_id = adev->periphid;
2905 ret = pl330_add(pl330);
2909 INIT_LIST_HEAD(&pl330->desc_pool);
2910 spin_lock_init(&pl330->pool_lock);
2912 /* Create a descriptor pool of default size */
2913 if (!add_desc(pl330, GFP_KERNEL, NR_DEFAULT_DESC))
2914 dev_warn(&adev->dev, "unable to allocate desc\n");
2916 INIT_LIST_HEAD(&pd->channels);
2918 /* Initialize channel parameters */
2920 num_chan = max_t(int, pdat->nr_valid_peri, pcfg->num_chan);
2922 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
2924 pl330->num_peripherals = num_chan;
2926 pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
2927 if (!pl330->peripherals) {
2929 dev_err(&adev->dev, "unable to allocate pl330->peripherals\n");
2933 for (i = 0; i < num_chan; i++) {
2934 pch = &pl330->peripherals[i];
2935 if (!adev->dev.of_node)
2936 pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
2938 pch->chan.private = adev->dev.of_node;
2940 INIT_LIST_HEAD(&pch->submitted_list);
2941 INIT_LIST_HEAD(&pch->work_list);
2942 INIT_LIST_HEAD(&pch->completed_list);
2943 spin_lock_init(&pch->lock);
2945 pch->chan.device = pd;
2948 /* Add the channel to the DMAC list */
2949 list_add_tail(&pch->chan.device_node, &pd->channels);
2953 pd->cap_mask = pdat->cap_mask;
2955 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
2956 if (pcfg->num_peri) {
2957 dma_cap_set(DMA_SLAVE, pd->cap_mask);
2958 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
2959 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
2963 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
2964 pd->device_free_chan_resources = pl330_free_chan_resources;
2965 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
2966 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
2967 pd->device_tx_status = pl330_tx_status;
2968 pd->device_prep_slave_sg = pl330_prep_slave_sg;
2969 pd->device_config = pl330_config;
2970 pd->device_pause = pl330_pause;
2971 pd->device_terminate_all = pl330_terminate_all;
2972 pd->device_issue_pending = pl330_issue_pending;
2973 pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
2974 pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
2975 pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2976 pd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2977 pd->max_burst = ((pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) ?
2978 1 : PL330_MAX_BURST);
2980 ret = dma_async_device_register(pd);
2982 dev_err(&adev->dev, "unable to register DMAC\n");
2986 if (adev->dev.of_node) {
2987 ret = of_dma_controller_register(adev->dev.of_node,
2988 of_dma_pl330_xlate, pl330);
2991 "unable to register DMA to the generic DT DMA helpers\n");
2995 adev->dev.dma_parms = &pl330->dma_parms;
2998 * This is the limit for transfers with a buswidth of 1, larger
2999 * buswidths will have larger limits.
3001 ret = dma_set_max_seg_size(&adev->dev, 1900800);
3003 dev_err(&adev->dev, "unable to set the seg size\n");
3006 dev_info(&adev->dev,
3007 "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
3008 dev_info(&adev->dev,
3009 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
3010 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
3011 pcfg->num_peri, pcfg->num_events);
3013 pm_runtime_irq_safe(&adev->dev);
3014 pm_runtime_use_autosuspend(&adev->dev);
3015 pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
3016 pm_runtime_mark_last_busy(&adev->dev);
3017 pm_runtime_put_autosuspend(&adev->dev);
3022 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3025 /* Remove the channel */
3026 list_del(&pch->chan.device_node);
3028 /* Flush the channel */
3030 pl330_terminate_all(&pch->chan);
3031 pl330_free_chan_resources(&pch->chan);
3040 static int pl330_remove(struct amba_device *adev)
3042 struct pl330_dmac *pl330 = amba_get_drvdata(adev);
3043 struct dma_pl330_chan *pch, *_p;
3045 pm_runtime_get_noresume(pl330->ddma.dev);
3047 if (adev->dev.of_node)
3048 of_dma_controller_free(adev->dev.of_node);
3050 dma_async_device_unregister(&pl330->ddma);
3053 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3056 /* Remove the channel */
3057 list_del(&pch->chan.device_node);
3059 /* Flush the channel */
3061 pl330_terminate_all(&pch->chan);
3062 pl330_free_chan_resources(&pch->chan);
3071 static struct amba_id pl330_ids[] = {
3079 MODULE_DEVICE_TABLE(amba, pl330_ids);
3081 static struct amba_driver pl330_driver = {
3083 .owner = THIS_MODULE,
3084 .name = "dma-pl330",
3087 .id_table = pl330_ids,
3088 .probe = pl330_probe,
3089 .remove = pl330_remove,
3092 module_amba_driver(pl330_driver);
3094 MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
3095 MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3096 MODULE_LICENSE("GPL");