2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/string.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/amba/bus.h>
25 #include <linux/amba/pl330.h>
26 #include <linux/scatterlist.h>
28 #include <linux/of_dma.h>
29 #include <linux/err.h>
30 #include <asm/unaligned.h>
32 #include "dmaengine.h"
33 #define PL330_MAX_CHAN 8
34 #define PL330_MAX_IRQS 32
35 #define PL330_MAX_PERI 32
37 enum pl330_srccachectrl {
38 SCCTRL0, /* Noncacheable and nonbufferable */
39 SCCTRL1, /* Bufferable only */
40 SCCTRL2, /* Cacheable, but do not allocate */
41 SCCTRL3, /* Cacheable and bufferable, but do not allocate */
44 SCCTRL6, /* Cacheable write-through, allocate on reads only */
45 SCCTRL7, /* Cacheable write-back, allocate on reads only */
48 enum pl330_dstcachectrl {
49 DCCTRL0, /* Noncacheable and nonbufferable */
50 DCCTRL1, /* Bufferable only */
51 DCCTRL2, /* Cacheable, but do not allocate */
52 DCCTRL3, /* Cacheable and bufferable, but do not allocate */
53 DINVALID1, /* AWCACHE = 0x1000 */
55 DCCTRL6, /* Cacheable write-through, allocate on writes only */
56 DCCTRL7, /* Cacheable write-back, allocate on writes only */
74 /* Register and Bit field Definitions */
76 #define DS_ST_STOP 0x0
77 #define DS_ST_EXEC 0x1
78 #define DS_ST_CMISS 0x2
79 #define DS_ST_UPDTPC 0x3
81 #define DS_ST_ATBRR 0x5
82 #define DS_ST_QBUSY 0x6
84 #define DS_ST_KILL 0x8
85 #define DS_ST_CMPLT 0x9
86 #define DS_ST_FLTCMP 0xe
87 #define DS_ST_FAULT 0xf
92 #define INTSTATUS 0x28
99 #define FTC(n) (_FTC + (n)*0x4)
102 #define CS(n) (_CS + (n)*0x8)
103 #define CS_CNS (1 << 21)
106 #define CPC(n) (_CPC + (n)*0x8)
109 #define SA(n) (_SA + (n)*0x20)
112 #define DA(n) (_DA + (n)*0x20)
115 #define CC(n) (_CC + (n)*0x20)
117 #define CC_SRCINC (1 << 0)
118 #define CC_DSTINC (1 << 14)
119 #define CC_SRCPRI (1 << 8)
120 #define CC_DSTPRI (1 << 22)
121 #define CC_SRCNS (1 << 9)
122 #define CC_DSTNS (1 << 23)
123 #define CC_SRCIA (1 << 10)
124 #define CC_DSTIA (1 << 24)
125 #define CC_SRCBRSTLEN_SHFT 4
126 #define CC_DSTBRSTLEN_SHFT 18
127 #define CC_SRCBRSTSIZE_SHFT 1
128 #define CC_DSTBRSTSIZE_SHFT 15
129 #define CC_SRCCCTRL_SHFT 11
130 #define CC_SRCCCTRL_MASK 0x7
131 #define CC_DSTCCTRL_SHFT 25
132 #define CC_DRCCCTRL_MASK 0x7
133 #define CC_SWAP_SHFT 28
136 #define LC0(n) (_LC0 + (n)*0x20)
139 #define LC1(n) (_LC1 + (n)*0x20)
141 #define DBGSTATUS 0xd00
142 #define DBG_BUSY (1 << 0)
145 #define DBGINST0 0xd08
146 #define DBGINST1 0xd0c
155 #define PERIPH_ID 0xfe0
156 #define PERIPH_REV_SHIFT 20
157 #define PERIPH_REV_MASK 0xf
158 #define PERIPH_REV_R0P0 0
159 #define PERIPH_REV_R1P0 1
160 #define PERIPH_REV_R1P1 2
161 #define PCELL_ID 0xff0
163 #define CR0_PERIPH_REQ_SET (1 << 0)
164 #define CR0_BOOT_EN_SET (1 << 1)
165 #define CR0_BOOT_MAN_NS (1 << 2)
166 #define CR0_NUM_CHANS_SHIFT 4
167 #define CR0_NUM_CHANS_MASK 0x7
168 #define CR0_NUM_PERIPH_SHIFT 12
169 #define CR0_NUM_PERIPH_MASK 0x1f
170 #define CR0_NUM_EVENTS_SHIFT 17
171 #define CR0_NUM_EVENTS_MASK 0x1f
173 #define CR1_ICACHE_LEN_SHIFT 0
174 #define CR1_ICACHE_LEN_MASK 0x7
175 #define CR1_NUM_ICACHELINES_SHIFT 4
176 #define CR1_NUM_ICACHELINES_MASK 0xf
178 #define CRD_DATA_WIDTH_SHIFT 0
179 #define CRD_DATA_WIDTH_MASK 0x7
180 #define CRD_WR_CAP_SHIFT 4
181 #define CRD_WR_CAP_MASK 0x7
182 #define CRD_WR_Q_DEP_SHIFT 8
183 #define CRD_WR_Q_DEP_MASK 0xf
184 #define CRD_RD_CAP_SHIFT 12
185 #define CRD_RD_CAP_MASK 0x7
186 #define CRD_RD_Q_DEP_SHIFT 16
187 #define CRD_RD_Q_DEP_MASK 0xf
188 #define CRD_DATA_BUFF_SHIFT 20
189 #define CRD_DATA_BUFF_MASK 0x3ff
192 #define DESIGNER 0x41
194 #define INTEG_CFG 0x0
195 #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
197 #define PCELL_ID_VAL 0xb105f00d
199 #define PL330_STATE_STOPPED (1 << 0)
200 #define PL330_STATE_EXECUTING (1 << 1)
201 #define PL330_STATE_WFE (1 << 2)
202 #define PL330_STATE_FAULTING (1 << 3)
203 #define PL330_STATE_COMPLETING (1 << 4)
204 #define PL330_STATE_WFP (1 << 5)
205 #define PL330_STATE_KILLING (1 << 6)
206 #define PL330_STATE_FAULT_COMPLETING (1 << 7)
207 #define PL330_STATE_CACHEMISS (1 << 8)
208 #define PL330_STATE_UPDTPC (1 << 9)
209 #define PL330_STATE_ATBARRIER (1 << 10)
210 #define PL330_STATE_QUEUEBUSY (1 << 11)
211 #define PL330_STATE_INVALID (1 << 15)
213 #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
214 | PL330_STATE_WFE | PL330_STATE_FAULTING)
216 #define CMD_DMAADDH 0x54
217 #define CMD_DMAEND 0x00
218 #define CMD_DMAFLUSHP 0x35
219 #define CMD_DMAGO 0xa0
220 #define CMD_DMALD 0x04
221 #define CMD_DMALDP 0x25
222 #define CMD_DMALP 0x20
223 #define CMD_DMALPEND 0x28
224 #define CMD_DMAKILL 0x01
225 #define CMD_DMAMOV 0xbc
226 #define CMD_DMANOP 0x18
227 #define CMD_DMARMB 0x12
228 #define CMD_DMASEV 0x34
229 #define CMD_DMAST 0x08
230 #define CMD_DMASTP 0x29
231 #define CMD_DMASTZ 0x0c
232 #define CMD_DMAWFE 0x36
233 #define CMD_DMAWFP 0x30
234 #define CMD_DMAWMB 0x13
238 #define SZ_DMAFLUSHP 2
242 #define SZ_DMALPEND 2
256 #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
257 #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
259 #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
260 #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
263 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
264 * at 1byte/burst for P<->M and M<->M respectively.
265 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
266 * should be enough for P<->M and M<->M respectively.
268 #define MCODE_BUFF_PER_REQ 256
270 /* If the _pl330_req is available to the client */
271 #define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == CMD_DMAEND)
273 /* Use this _only_ to wait on transient states */
274 #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
276 #ifdef PL330_DEBUG_MCGEN
277 static unsigned cmd_line;
278 #define PL330_DBGCMD_DUMP(off, x...) do { \
279 printk("%x:", cmd_line); \
283 #define PL330_DBGMC_START(addr) (cmd_line = addr)
285 #define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
286 #define PL330_DBGMC_START(addr) do {} while (0)
289 /* The number of default descriptors */
291 #define NR_DEFAULT_DESC 32
293 /* Populated by the PL330 core driver for DMA API driver's info */
294 struct pl330_config {
297 #define DMAC_MODE_NS (1 << 0)
299 unsigned int data_bus_width:10; /* In number of bits */
300 unsigned int data_buf_dep:10;
301 unsigned int num_chan:4;
302 unsigned int num_peri:6;
304 unsigned int num_events:6;
308 /* Handle to the DMAC provided to the PL330 core */
312 /* Size of MicroCode buffers for each channel. */
314 /* ioremap'ed address of PL330 registers. */
316 /* Client can freely use it. */
318 /* PL330 core data, Client must not touch it. */
320 /* Populated by the PL330 core driver during pl330_add */
321 struct pl330_config pcfg;
323 * If the DMAC has some reset mechanism, then the
324 * client may want to provide pointer to the method.
326 void (*dmac_reset)(struct pl330_info *pi);
330 * Request Configuration.
331 * The PL330 core does not modify this and uses the last
332 * working configuration if the request doesn't provide any.
334 * The Client may want to provide this info only for the
335 * first request and a request with new settings.
337 struct pl330_reqcfg {
338 /* Address Incrementing */
343 * For now, the SRC & DST protection levels
344 * and burst size/length are assumed same.
350 unsigned brst_size:3; /* in power of 2 */
352 enum pl330_dstcachectrl dcctl;
353 enum pl330_srccachectrl scctl;
354 enum pl330_byteswap swap;
355 struct pl330_config *pcfg;
359 * One cycle of DMAC operation.
360 * There may be more than one xfer in a request.
368 * Pointer to next xfer in the list.
369 * The last xfer in the req must point to NULL.
371 struct pl330_xfer *next;
374 /* The xfer callbacks are made with one of these arguments. */
376 /* The all xfers in the request were success. */
378 /* If req aborted due to global error. */
380 /* If req failed due to problem with Channel. */
384 /* A request defining Scatter-Gather List ending with NULL xfer. */
386 enum pl330_reqtype rqtype;
387 /* Index of peripheral for the xfer. */
389 /* Unique token for this xfer, set by the client. */
391 /* Callback to be called after xfer. */
392 void (*xfer_cb)(void *token, enum pl330_op_err err);
393 /* If NULL, req will be done at last set parameters. */
394 struct pl330_reqcfg *cfg;
395 /* Pointer to first xfer in the request. */
396 struct pl330_xfer *x;
397 /* Hook to attach to DMAC's list of reqs with due callback */
398 struct list_head rqd;
399 unsigned int infiniteloop;
403 * To know the status of the channel and DMAC, the client
404 * provides a pointer to this structure. The PL330 core
405 * fills it with current information.
407 struct pl330_chanstatus {
409 * If the DMAC engine halted due to some error,
410 * the client should remove-add DMAC.
414 * If channel is halted due to some error,
415 * the client should ABORT/FLUSH and START the channel.
418 /* Location of last load */
420 /* Location of last store */
423 * Pointer to the currently active req, NULL if channel is
424 * inactive, even though the requests may be present.
426 struct pl330_req *top_req;
427 /* Pointer to req waiting second in the queue if any. */
428 struct pl330_req *wait_req;
432 /* Start the channel */
434 /* Abort the active xfer */
436 /* Stop xfer and flush queue */
443 struct pl330_xfer *x;
466 /* Number of bytes taken to setup MC for the req */
471 /* ToBeDone for tasklet */
479 struct pl330_thread {
482 /* If the channel is not yet acquired by any client */
485 struct pl330_dmac *dmac;
486 /* Only two at a time */
487 struct _pl330_req req[2];
488 /* Index of the last enqueued request */
490 /* Index of the last submitted request or -1 if the DMA is stopped */
494 enum pl330_dmac_state {
503 /* Holds list of reqs with due callbacks */
504 struct list_head req_done;
505 /* Pointer to platform specific stuff */
506 struct pl330_info *pinfo;
507 /* Maximum possible events/irqs */
509 /* BUS address of MicroCode buffer */
510 dma_addr_t mcode_bus;
511 /* CPU address of MicroCode buffer */
513 /* List of all Channel threads */
514 struct pl330_thread *channels;
515 /* Pointer to the MANAGER thread */
516 struct pl330_thread *manager;
517 /* To handle bad news in interrupt */
518 struct tasklet_struct tasks;
519 struct _pl330_tbd dmac_tbd;
520 /* State of DMAC operation */
521 enum pl330_dmac_state state;
525 /* In the DMAC pool */
528 * Allocated to some channel during prep_xxx
529 * Also may be sitting on the work_list.
533 * Sitting on the work_list and already submitted
534 * to the PL330 core. Not more than two descriptors
535 * of a channel can be BUSY at any time.
539 * Sitting on the channel work_list but xfer done
545 struct dma_pl330_chan {
546 /* Schedule desc completion */
547 struct tasklet_struct task;
549 /* DMA-Engine Channel */
550 struct dma_chan chan;
552 /* List of to be xfered descriptors */
553 struct list_head work_list;
555 /* Pointer to the DMAC that manages this channel,
556 * NULL if the channel is available to be acquired.
557 * As the parent, this DMAC also provides descriptors
560 struct dma_pl330_dmac *dmac;
562 /* To protect channel manipulation */
565 /* Token of a hardware channel thread of PL330 DMAC
566 * NULL if the channel is available to be acquired.
570 /* For D-to-M and M-to-D channels */
571 int burst_sz; /* the peripheral fifo width */
572 int burst_len; /* the number of burst */
573 dma_addr_t fifo_addr;
575 /* for cyclic capability */
578 enum dma_status chan_status;
581 struct dma_pl330_dmac {
582 struct pl330_info pif;
584 /* DMA-Engine Device */
585 struct dma_device ddma;
587 /* Pool of descriptors available for the DMAC's channels */
588 struct list_head desc_pool;
589 /* To protect desc_pool manipulation */
590 spinlock_t pool_lock;
592 /* Peripheral channels connected to this DMAC */
593 struct dma_pl330_chan *peripherals; /* keep at end */
596 struct dma_pl330_desc {
597 /* To attach to a queue as child */
598 struct list_head node;
600 /* Descriptor for the DMA Engine API */
601 struct dma_async_tx_descriptor txd;
603 /* Xfer for PL330 core */
604 struct pl330_xfer px;
606 struct pl330_reqcfg rqcfg;
607 struct pl330_req req;
609 enum desc_status status;
611 /* The channel which currently holds this desc */
612 struct dma_pl330_chan *pchan;
615 struct dma_pl330_filter_args {
616 struct dma_pl330_dmac *pdmac;
617 unsigned int chan_id;
620 static inline void _callback(struct pl330_req *r, enum pl330_op_err err)
623 r->xfer_cb(r->token, err);
626 static inline bool _queue_empty(struct pl330_thread *thrd)
628 return (IS_FREE(&thrd->req[0]) && IS_FREE(&thrd->req[1]))
632 static inline bool _queue_full(struct pl330_thread *thrd)
634 return (IS_FREE(&thrd->req[0]) || IS_FREE(&thrd->req[1]))
638 static inline bool is_manager(struct pl330_thread *thrd)
640 struct pl330_dmac *pl330 = thrd->dmac;
642 /* MANAGER is indexed at the end */
643 if (thrd->id == pl330->pinfo->pcfg.num_chan)
649 /* If manager of the thread is in Non-Secure mode */
650 static inline bool _manager_ns(struct pl330_thread *thrd)
652 struct pl330_dmac *pl330 = thrd->dmac;
654 return (pl330->pinfo->pcfg.mode & DMAC_MODE_NS) ? true : false;
657 static inline u32 get_id(struct pl330_info *pi, u32 off)
659 void __iomem *regs = pi->base;
662 #ifdef CONFIG_ARCH_ROCKCHIP
663 id |= ((readl(regs + off + 0x0) & 0xff) << 0);
664 id |= ((readl(regs + off + 0x4) & 0xff) << 8);
665 id |= ((readl(regs + off + 0x8) & 0xff) << 16);
666 id |= ((readl(regs + off + 0xc) & 0xff) << 24);
668 id |= (readb(regs + off + 0x0) << 0);
669 id |= (readb(regs + off + 0x4) << 8);
670 id |= (readb(regs + off + 0x8) << 16);
671 id |= (readb(regs + off + 0xc) << 24);
677 static inline u32 get_revision(u32 periph_id)
679 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
682 static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
683 enum pl330_dst da, u16 val)
688 buf[0] = CMD_DMAADDH;
690 put_unaligned(val, (u16 *)&buf[1]); //*((u16 *)&buf[1]) = val;
692 PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
693 da == 1 ? "DA" : "SA", val);
698 static inline u32 _emit_END(unsigned dry_run, u8 buf[])
705 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
710 static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
715 buf[0] = CMD_DMAFLUSHP;
721 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
726 static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
734 buf[0] |= (0 << 1) | (1 << 0);
735 else if (cond == BURST)
736 buf[0] |= (1 << 1) | (1 << 0);
738 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
739 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
744 static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
745 enum pl330_cond cond, u8 peri)
759 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
760 cond == SINGLE ? 'S' : 'B', peri >> 3);
765 static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
766 unsigned loop, u8 cnt)
776 cnt--; /* DMAC increments by 1 internally */
779 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
785 enum pl330_cond cond;
791 static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
792 const struct _arg_LPEND *arg)
794 enum pl330_cond cond = arg->cond;
795 bool forever = arg->forever;
796 unsigned loop = arg->loop;
797 u8 bjump = arg->bjump;
802 buf[0] = CMD_DMALPEND;
811 buf[0] |= (0 << 1) | (1 << 0);
812 else if (cond == BURST)
813 buf[0] |= (1 << 1) | (1 << 0);
817 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
818 forever ? "FE" : "END",
819 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
826 static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
831 buf[0] = CMD_DMAKILL;
836 static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
837 enum dmamov_dst dst, u32 val)
844 put_unaligned(val, (u32 *)&buf[2]); //*((u32 *)&buf[2]) = val;
846 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
847 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
852 static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
859 PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
864 static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
871 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
876 static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
887 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
892 static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
900 buf[0] |= (0 << 1) | (1 << 0);
901 else if (cond == BURST)
902 buf[0] |= (1 << 1) | (1 << 0);
904 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
905 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
910 static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
911 enum pl330_cond cond, u8 peri)
925 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
926 cond == SINGLE ? 'S' : 'B', peri >> 3);
931 static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
938 PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
943 static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
958 PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
959 ev >> 3, invalidate ? ", I" : "");
964 static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
965 enum pl330_cond cond, u8 peri)
973 buf[0] |= (0 << 1) | (0 << 0);
974 else if (cond == BURST)
975 buf[0] |= (1 << 1) | (0 << 0);
977 buf[0] |= (0 << 1) | (1 << 0);
983 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
984 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
989 static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
996 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
1007 static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
1008 const struct _arg_GO *arg)
1010 u8 chan = arg->chan;
1011 u32 addr = arg->addr;
1012 unsigned ns = arg->ns;
1018 buf[0] |= (ns << 1);
1020 buf[1] = chan & 0x7;
1022 put_unaligned(addr, (u32 *)&buf[2]); //*((u32 *)&buf[2]) = addr;
1027 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
1029 /* Returns Time-Out */
1030 static bool _until_dmac_idle(struct pl330_thread *thrd)
1032 void __iomem *regs = thrd->dmac->pinfo->base;
1033 unsigned long loops = msecs_to_loops(5);
1036 /* Until Manager is Idle */
1037 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
1049 static inline void _execute_DBGINSN(struct pl330_thread *thrd,
1050 u8 insn[], bool as_manager)
1052 void __iomem *regs = thrd->dmac->pinfo->base;
1055 val = (insn[0] << 16) | (insn[1] << 24);
1058 val |= (thrd->id << 8); /* Channel Number */
1060 writel(val, regs + DBGINST0);
1062 val = *((u32 *)&insn[2]);
1063 writel(val, regs + DBGINST1);
1065 /* If timed out due to halted state-machine */
1066 if (_until_dmac_idle(thrd)) {
1067 dev_err(thrd->dmac->pinfo->dev, "DMAC halted!\n");
1072 writel(0, regs + DBGCMD);
1076 * Mark a _pl330_req as free.
1077 * We do it by writing DMAEND as the first instruction
1078 * because no valid request is going to have DMAEND as
1079 * its first instruction to execute.
1081 static void mark_free(struct pl330_thread *thrd, int idx)
1083 struct _pl330_req *req = &thrd->req[idx];
1085 _emit_END(0, req->mc_cpu);
1088 thrd->req_running = -1;
1091 static inline u32 _state(struct pl330_thread *thrd)
1093 void __iomem *regs = thrd->dmac->pinfo->base;
1096 if (is_manager(thrd))
1097 val = readl(regs + DS) & 0xf;
1099 val = readl(regs + CS(thrd->id)) & 0xf;
1103 return PL330_STATE_STOPPED;
1105 return PL330_STATE_EXECUTING;
1107 return PL330_STATE_CACHEMISS;
1109 return PL330_STATE_UPDTPC;
1111 return PL330_STATE_WFE;
1113 return PL330_STATE_FAULTING;
1115 if (is_manager(thrd))
1116 return PL330_STATE_INVALID;
1118 return PL330_STATE_ATBARRIER;
1120 if (is_manager(thrd))
1121 return PL330_STATE_INVALID;
1123 return PL330_STATE_QUEUEBUSY;
1125 if (is_manager(thrd))
1126 return PL330_STATE_INVALID;
1128 return PL330_STATE_WFP;
1130 if (is_manager(thrd))
1131 return PL330_STATE_INVALID;
1133 return PL330_STATE_KILLING;
1135 if (is_manager(thrd))
1136 return PL330_STATE_INVALID;
1138 return PL330_STATE_COMPLETING;
1140 if (is_manager(thrd))
1141 return PL330_STATE_INVALID;
1143 return PL330_STATE_FAULT_COMPLETING;
1145 return PL330_STATE_INVALID;
1149 static void _stop(struct pl330_thread *thrd)
1151 void __iomem *regs = thrd->dmac->pinfo->base;
1152 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1154 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
1155 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1157 /* Return if nothing needs to be done */
1158 if (_state(thrd) == PL330_STATE_COMPLETING
1159 || _state(thrd) == PL330_STATE_KILLING
1160 || _state(thrd) == PL330_STATE_STOPPED)
1163 _emit_KILL(0, insn);
1165 /* Stop generating interrupts for SEV */
1166 writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
1168 _execute_DBGINSN(thrd, insn, is_manager(thrd));
1171 /* Start doing req 'idx' of thread 'thrd' */
1172 static bool _trigger(struct pl330_thread *thrd)
1174 void __iomem *regs = thrd->dmac->pinfo->base;
1175 struct _pl330_req *req;
1176 struct pl330_req *r;
1179 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1182 /* Return if already ACTIVE */
1183 if (_state(thrd) != PL330_STATE_STOPPED)
1186 idx = 1 - thrd->lstenq;
1187 if (!IS_FREE(&thrd->req[idx]))
1188 req = &thrd->req[idx];
1191 if (!IS_FREE(&thrd->req[idx]))
1192 req = &thrd->req[idx];
1197 /* Return if no request */
1198 if (!req || !req->r)
1204 ns = r->cfg->nonsecure ? 1 : 0;
1205 else if (readl(regs + CS(thrd->id)) & CS_CNS)
1210 /* See 'Abort Sources' point-4 at Page 2-25 */
1211 if (_manager_ns(thrd) && !ns)
1212 dev_info(thrd->dmac->pinfo->dev, "%s:%d Recipe for ABORT!\n",
1213 __func__, __LINE__);
1216 go.addr = req->mc_bus;
1218 _emit_GO(0, insn, &go);
1220 /* Set to generate interrupts for SEV */
1221 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1223 /* Only manager can execute GO */
1224 _execute_DBGINSN(thrd, insn, true);
1226 thrd->req_running = idx;
1231 static bool _start(struct pl330_thread *thrd)
1233 switch (_state(thrd)) {
1234 case PL330_STATE_FAULT_COMPLETING:
1235 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1237 if (_state(thrd) == PL330_STATE_KILLING)
1238 UNTIL(thrd, PL330_STATE_STOPPED)
1240 case PL330_STATE_FAULTING:
1243 case PL330_STATE_KILLING:
1244 case PL330_STATE_COMPLETING:
1245 UNTIL(thrd, PL330_STATE_STOPPED)
1247 case PL330_STATE_STOPPED:
1248 return _trigger(thrd);
1250 case PL330_STATE_WFP:
1251 case PL330_STATE_QUEUEBUSY:
1252 case PL330_STATE_ATBARRIER:
1253 case PL330_STATE_UPDTPC:
1254 case PL330_STATE_CACHEMISS:
1255 case PL330_STATE_EXECUTING:
1258 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1264 static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1265 const struct _xfer_spec *pxs, int cyc)
1268 struct pl330_config *pcfg = pxs->r->cfg->pcfg;
1270 /* check lock-up free version */
1271 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1273 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1274 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1278 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1279 off += _emit_RMB(dry_run, &buf[off]);
1280 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1281 off += _emit_WMB(dry_run, &buf[off]);
1288 static inline int _ldst_devtomem(unsigned dry_run, u8 buf[],
1289 const struct _xfer_spec *pxs, int cyc)
1294 #ifdef CONFIG_ARCH_ROCKCHIP
1295 off += _emit_WFP(dry_run, &buf[off], BURST, pxs->r->peri);
1296 off += _emit_LDP(dry_run, &buf[off], BURST, pxs->r->peri);
1297 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1298 //off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri); //for sdmmc sdio
1300 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1301 off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1302 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1303 off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri);
1310 static inline int _ldst_memtodev(unsigned dry_run, u8 buf[],
1311 const struct _xfer_spec *pxs, int cyc)
1316 #ifdef CONFIG_ARCH_ROCKCHIP
1317 off += _emit_WFP(dry_run, &buf[off], BURST, pxs->r->peri);
1318 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1319 off += _emit_STP(dry_run, &buf[off], BURST, pxs->r->peri);
1320 //off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri);
1322 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1323 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1324 off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1325 off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri);
1332 static int _bursts(unsigned dry_run, u8 buf[],
1333 const struct _xfer_spec *pxs, int cyc)
1337 switch (pxs->r->rqtype) {
1339 off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc);
1342 off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc);
1345 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1348 off += 0x40000000; /* Scare off the Client */
1355 /* Returns bytes consumed */
1356 static inline int _loop_infiniteloop(unsigned dry_run, u8 buf[],
1357 unsigned long bursts, const struct _xfer_spec *pxs, int ev)
1360 unsigned lcnt0, lcnt1, ljmp0, ljmp1, ljmpfe;
1361 struct _arg_LPEND lpend;
1365 lcnt0 = pxs->r->infiniteloop;
1376 off += _emit_MOV(dry_run, &buf[off], SAR, pxs->x->src_addr);
1377 off += _emit_MOV(dry_run, &buf[off], DAR, pxs->x->dst_addr);
1378 if (pxs->r->rqtype != MEMTOMEM)
1379 off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri);
1382 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1386 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1388 off += _bursts(dry_run, &buf[off], pxs, cyc);
1389 lpend.cond = ALWAYS;
1390 lpend.forever = false;
1392 lpend.bjump = off - ljmp1;
1393 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1396 lcnt1 = bursts - (lcnt1 * cyc);
1399 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1401 off += _bursts(dry_run, &buf[off], pxs, 1);
1402 lpend.cond = ALWAYS;
1403 lpend.forever = false;
1405 lpend.bjump = off - ljmp1;
1406 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1409 off += _emit_SEV(dry_run, &buf[off], ev);
1411 lpend.cond = ALWAYS;
1412 lpend.forever = false;
1414 lpend.bjump = off - ljmp0;
1415 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1417 lpend.cond = ALWAYS;
1418 lpend.forever = true;
1420 lpend.bjump = off - ljmpfe;
1421 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1426 /* Returns bytes consumed and updates bursts */
1427 static inline int _loop(unsigned dry_run, u8 buf[],
1428 unsigned long *bursts, const struct _xfer_spec *pxs)
1430 int cyc, cycmax, szlp, szlpend, szbrst, off;
1431 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1432 struct _arg_LPEND lpend;
1434 /* Max iterations possible in DMALP is 256 */
1435 if (*bursts >= 256*256) {
1438 cyc = *bursts / lcnt1 / lcnt0;
1439 } else if (*bursts > 256) {
1441 lcnt0 = *bursts / lcnt1;
1449 szlp = _emit_LP(1, buf, 0, 0);
1450 szbrst = _bursts(1, buf, pxs, 1);
1452 lpend.cond = ALWAYS;
1453 lpend.forever = false;
1456 szlpend = _emit_LPEND(1, buf, &lpend);
1464 * Max bursts that we can unroll due to limit on the
1465 * size of backward jump that can be encoded in DMALPEND
1466 * which is 8-bits and hence 255
1468 cycmax = (255 - (szlp + szlpend)) / szbrst;
1470 cyc = (cycmax < cyc) ? cycmax : cyc;
1475 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1479 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1482 off += _bursts(dry_run, &buf[off], pxs, cyc);
1484 lpend.cond = ALWAYS;
1485 lpend.forever = false;
1487 lpend.bjump = off - ljmp1;
1488 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1491 lpend.cond = ALWAYS;
1492 lpend.forever = false;
1494 lpend.bjump = off - ljmp0;
1495 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1498 *bursts = lcnt1 * cyc;
1505 static inline int _setup_xfer_infiniteloop(unsigned dry_run, u8 buf[],
1506 const struct _xfer_spec *pxs, int ev)
1508 struct pl330_xfer *x = pxs->x;
1510 unsigned long bursts = BYTE_TO_BURST(x->bytes, ccr);
1514 off += _loop_infiniteloop(dry_run, &buf[off], bursts, pxs, ev);
1519 static inline int _setup_loops(unsigned dry_run, u8 buf[],
1520 const struct _xfer_spec *pxs)
1522 struct pl330_xfer *x = pxs->x;
1524 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1529 off += _loop(dry_run, &buf[off], &c, pxs);
1536 static inline int _setup_xfer(unsigned dry_run, u8 buf[],
1537 const struct _xfer_spec *pxs)
1539 struct pl330_xfer *x = pxs->x;
1542 /* DMAMOV SAR, x->src_addr */
1543 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1544 /* DMAMOV DAR, x->dst_addr */
1545 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1548 off += _setup_loops(dry_run, &buf[off], pxs);
1554 * A req is a sequence of one or more xfer units.
1555 * Returns the number of bytes taken to setup the MC for the req.
1557 static int _setup_req(unsigned dry_run, struct pl330_thread *thrd,
1558 unsigned index, struct _xfer_spec *pxs)
1560 struct _pl330_req *req = &thrd->req[index];
1561 struct pl330_xfer *x;
1562 u8 *buf = req->mc_cpu;
1565 PL330_DBGMC_START(req->mc_bus);
1567 /* DMAMOV CCR, ccr */
1568 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1571 if (!pxs->r->infiniteloop) {
1573 /* Error if xfer length is not aligned at burst size */
1574 if (x->bytes % (BRST_SIZE(pxs->ccr) *
1575 BRST_LEN(pxs->ccr)))
1579 off += _setup_xfer(dry_run, &buf[off], pxs);
1584 /* DMASEV peripheral/event */
1585 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1587 off += _emit_END(dry_run, &buf[off]);
1589 /* Error if xfer length is not aligned at burst size */
1590 if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1594 off += _setup_xfer_infiniteloop(dry_run, &buf[off],
1601 static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1611 /* We set same protection levels for Src and DST for now */
1612 if (rqc->privileged)
1613 ccr |= CC_SRCPRI | CC_DSTPRI;
1615 ccr |= CC_SRCNS | CC_DSTNS;
1616 if (rqc->insnaccess)
1617 ccr |= CC_SRCIA | CC_DSTIA;
1619 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1620 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1622 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1623 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1625 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1626 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1628 ccr |= (rqc->swap << CC_SWAP_SHFT);
1633 static inline bool _is_valid(u32 ccr)
1635 enum pl330_dstcachectrl dcctl;
1636 enum pl330_srccachectrl scctl;
1638 dcctl = (ccr >> CC_DSTCCTRL_SHFT) & CC_DRCCCTRL_MASK;
1639 scctl = (ccr >> CC_SRCCCTRL_SHFT) & CC_SRCCCTRL_MASK;
1641 if (dcctl == DINVALID1 || dcctl == DINVALID2
1642 || scctl == SINVALID1 || scctl == SINVALID2)
1649 * Submit a list of xfers after which the client wants notification.
1650 * Client is not notified after each xfer unit, just once after all
1651 * xfer units are done or some error occurs.
1653 static int pl330_submit_req(void *ch_id, struct pl330_req *r)
1655 struct pl330_thread *thrd = ch_id;
1656 struct pl330_dmac *pl330;
1657 struct pl330_info *pi;
1658 struct _xfer_spec xs;
1659 unsigned long flags;
1665 /* No Req or Unacquired Channel or DMAC */
1666 if (!r || !thrd || thrd->free)
1673 if (pl330->state == DYING
1674 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1675 dev_info(thrd->dmac->pinfo->dev, "%s:%d\n",
1676 __func__, __LINE__);
1680 /* If request for non-existing peripheral */
1681 if (r->rqtype != MEMTOMEM && r->peri >= pi->pcfg.num_peri) {
1682 dev_info(thrd->dmac->pinfo->dev,
1683 "%s:%d Invalid peripheral(%u)!\n",
1684 __func__, __LINE__, r->peri);
1688 spin_lock_irqsave(&pl330->lock, flags);
1690 if (_queue_full(thrd)) {
1696 /* Use last settings, if not provided */
1698 /* Prefer Secure Channel */
1699 if (!_manager_ns(thrd))
1700 r->cfg->nonsecure = 0;
1702 r->cfg->nonsecure = 1;
1704 ccr = _prepare_ccr(r->cfg);
1706 ccr = readl(regs + CC(thrd->id));
1709 /* If this req doesn't have valid xfer settings */
1710 if (!_is_valid(ccr)) {
1712 dev_info(thrd->dmac->pinfo->dev, "%s:%d Invalid CCR(%x)!\n",
1713 __func__, __LINE__, ccr);
1717 idx = IS_FREE(&thrd->req[0]) ? 0 : 1;
1722 /* First dry run to check if req is acceptable */
1723 ret = _setup_req(1, thrd, idx, &xs);
1727 if (ret > pi->mcbufsz / 2) {
1728 dev_info(thrd->dmac->pinfo->dev,
1729 "%s:%d Trying increasing mcbufsz\n",
1730 __func__, __LINE__);
1735 /* Hook the request */
1737 thrd->req[idx].mc_len = _setup_req(0, thrd, idx, &xs);
1738 thrd->req[idx].r = r;
1743 spin_unlock_irqrestore(&pl330->lock, flags);
1748 static void pl330_dotask(unsigned long data)
1750 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1751 struct pl330_info *pi = pl330->pinfo;
1752 unsigned long flags;
1755 spin_lock_irqsave(&pl330->lock, flags);
1757 /* The DMAC itself gone nuts */
1758 if (pl330->dmac_tbd.reset_dmac) {
1759 pl330->state = DYING;
1760 /* Reset the manager too */
1761 pl330->dmac_tbd.reset_mngr = true;
1762 /* Clear the reset flag */
1763 pl330->dmac_tbd.reset_dmac = false;
1766 if (pl330->dmac_tbd.reset_mngr) {
1767 _stop(pl330->manager);
1768 /* Reset all channels */
1769 pl330->dmac_tbd.reset_chan = (1 << pi->pcfg.num_chan) - 1;
1770 /* Clear the reset flag */
1771 pl330->dmac_tbd.reset_mngr = false;
1774 for (i = 0; i < pi->pcfg.num_chan; i++) {
1776 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1777 struct pl330_thread *thrd = &pl330->channels[i];
1778 void __iomem *regs = pi->base;
1779 enum pl330_op_err err;
1783 if (readl(regs + FSC) & (1 << thrd->id))
1784 err = PL330_ERR_FAIL;
1786 err = PL330_ERR_ABORT;
1788 spin_unlock_irqrestore(&pl330->lock, flags);
1790 _callback(thrd->req[1 - thrd->lstenq].r, err);
1791 _callback(thrd->req[thrd->lstenq].r, err);
1793 spin_lock_irqsave(&pl330->lock, flags);
1795 thrd->req[0].r = NULL;
1796 thrd->req[1].r = NULL;
1800 /* Clear the reset flag */
1801 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1805 spin_unlock_irqrestore(&pl330->lock, flags);
1810 /* Returns 1 if state was updated, 0 otherwise */
1811 static int pl330_update(const struct pl330_info *pi)
1813 struct pl330_req *rqdone, *tmp;
1814 struct pl330_dmac *pl330;
1815 unsigned long flags;
1818 int id, ev, ret = 0;
1820 if (!pi || !pi->pl330_data)
1824 pl330 = pi->pl330_data;
1826 spin_lock_irqsave(&pl330->lock, flags);
1828 val = readl(regs + FSM) & 0x1;
1830 pl330->dmac_tbd.reset_mngr = true;
1832 pl330->dmac_tbd.reset_mngr = false;
1834 val = readl(regs + FSC) & ((1 << pi->pcfg.num_chan) - 1);
1835 pl330->dmac_tbd.reset_chan |= val;
1838 while (i < pi->pcfg.num_chan) {
1839 if (val & (1 << i)) {
1841 "Reset Channel-%d\t CS-%x FTC-%x\n",
1842 i, readl(regs + CS(i)),
1843 readl(regs + FTC(i)));
1844 _stop(&pl330->channels[i]);
1850 /* Check which event happened i.e, thread notified */
1851 val = readl(regs + ES);
1852 if (pi->pcfg.num_events < 32
1853 && val & ~((1 << pi->pcfg.num_events) - 1)) {
1854 pl330->dmac_tbd.reset_dmac = true;
1855 dev_err(pi->dev, "%s:%d Unexpected!\n", __func__, __LINE__);
1860 for (ev = 0; ev < pi->pcfg.num_events; ev++) {
1861 if (val & (1 << ev)) { /* Event occurred */
1862 struct pl330_thread *thrd;
1863 u32 inten = readl(regs + INTEN);
1866 /* Clear the event */
1867 if (inten & (1 << ev))
1868 writel(1 << ev, regs + INTCLR);
1872 id = pl330->events[ev];
1877 thrd = &pl330->channels[id];
1879 active = thrd->req_running;
1880 if (active == -1) /* Aborted */
1883 /* Detach the req */
1884 rqdone = thrd->req[active].r;
1885 if (!rqdone->infiniteloop) {
1887 /* Detach the req */
1888 thrd->req[active].r = NULL;
1890 mark_free(thrd, active);
1892 /* Get going again ASAP */
1896 /* For now, just make a list of callbacks to be done */
1897 list_add_tail(&rqdone->rqd, &pl330->req_done);
1901 /* Now that we are in no hurry, do the callbacks */
1902 list_for_each_entry_safe(rqdone, tmp, &pl330->req_done, rqd) {
1903 list_del(&rqdone->rqd);
1905 spin_unlock_irqrestore(&pl330->lock, flags);
1906 _callback(rqdone, PL330_ERR_NONE);
1907 spin_lock_irqsave(&pl330->lock, flags);
1911 spin_unlock_irqrestore(&pl330->lock, flags);
1913 if (pl330->dmac_tbd.reset_dmac
1914 || pl330->dmac_tbd.reset_mngr
1915 || pl330->dmac_tbd.reset_chan) {
1917 tasklet_schedule(&pl330->tasks);
1923 static int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op)
1925 struct pl330_thread *thrd = ch_id;
1926 struct pl330_dmac *pl330;
1927 unsigned long flags;
1928 int ret = 0, active;
1930 if (!thrd || thrd->free || thrd->dmac->state == DYING)
1934 active = thrd->req_running;
1936 spin_lock_irqsave(&pl330->lock, flags);
1939 case PL330_OP_FLUSH:
1940 /* Make sure the channel is stopped */
1943 thrd->req[0].r = NULL;
1944 thrd->req[1].r = NULL;
1949 case PL330_OP_ABORT:
1950 /* Make sure the channel is stopped */
1953 /* ABORT is only for the active req */
1957 thrd->req[active].r = NULL;
1958 mark_free(thrd, active);
1960 /* Start the next */
1961 case PL330_OP_START:
1962 if ((active == -1) && !_start(thrd))
1970 spin_unlock_irqrestore(&pl330->lock, flags);
1974 /* Reserve an event */
1975 static inline int _alloc_event(struct pl330_thread *thrd)
1977 struct pl330_dmac *pl330 = thrd->dmac;
1978 struct pl330_info *pi = pl330->pinfo;
1981 for (ev = 0; ev < pi->pcfg.num_events; ev++)
1982 if (pl330->events[ev] == -1) {
1983 pl330->events[ev] = thrd->id;
1990 static bool _chan_ns(const struct pl330_info *pi, int i)
1992 return pi->pcfg.irq_ns & (1 << i);
1995 /* Upon success, returns IdentityToken for the
1996 * allocated channel, NULL otherwise.
1998 static void *pl330_request_channel(const struct pl330_info *pi)
2000 struct pl330_thread *thrd = NULL;
2001 struct pl330_dmac *pl330;
2002 unsigned long flags;
2005 if (!pi || !pi->pl330_data)
2008 pl330 = pi->pl330_data;
2010 if (pl330->state == DYING)
2013 chans = pi->pcfg.num_chan;
2015 spin_lock_irqsave(&pl330->lock, flags);
2017 for (i = 0; i < chans; i++) {
2018 thrd = &pl330->channels[i];
2019 if ((thrd->free) && (!_manager_ns(thrd) ||
2021 thrd->ev = _alloc_event(thrd);
2022 if (thrd->ev >= 0) {
2025 thrd->req[0].r = NULL;
2027 thrd->req[1].r = NULL;
2035 spin_unlock_irqrestore(&pl330->lock, flags);
2040 /* Release an event */
2041 static inline void _free_event(struct pl330_thread *thrd, int ev)
2043 struct pl330_dmac *pl330 = thrd->dmac;
2044 struct pl330_info *pi = pl330->pinfo;
2045 void __iomem *regs = pi->base;
2046 u32 inten = readl(regs + INTEN);
2048 /* If the event is valid and was held by the thread */
2049 if (ev >= 0 && ev < pi->pcfg.num_events
2050 && pl330->events[ev] == thrd->id) {
2051 pl330->events[ev] = -1;
2053 if (readl(regs + ES) & (1 << ev)) {
2054 if (!(inten & (1 << ev)))
2055 writel(inten | (1 << ev), regs + INTEN);
2056 writel(1 << ev, regs + INTCLR);
2057 writel(inten & ~(1 << ev) , regs + INTEN);
2062 static void pl330_release_channel(void *ch_id)
2064 struct pl330_thread *thrd = ch_id;
2065 struct pl330_dmac *pl330;
2066 unsigned long flags;
2068 if (!thrd || thrd->free)
2073 _callback(thrd->req[1 - thrd->lstenq].r, PL330_ERR_ABORT);
2074 _callback(thrd->req[thrd->lstenq].r, PL330_ERR_ABORT);
2078 spin_lock_irqsave(&pl330->lock, flags);
2079 _free_event(thrd, thrd->ev);
2081 spin_unlock_irqrestore(&pl330->lock, flags);
2084 /* Initialize the structure for PL330 configuration, that can be used
2085 * by the client driver the make best use of the DMAC
2087 static void read_dmac_config(struct pl330_info *pi)
2089 void __iomem *regs = pi->base;
2092 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
2093 val &= CRD_DATA_WIDTH_MASK;
2094 pi->pcfg.data_bus_width = 8 * (1 << val);
2096 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
2097 val &= CRD_DATA_BUFF_MASK;
2098 pi->pcfg.data_buf_dep = val + 1;
2100 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
2101 val &= CR0_NUM_CHANS_MASK;
2103 pi->pcfg.num_chan = val;
2105 val = readl(regs + CR0);
2106 if (val & CR0_PERIPH_REQ_SET) {
2107 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
2109 pi->pcfg.num_peri = val;
2110 pi->pcfg.peri_ns = readl(regs + CR4);
2112 pi->pcfg.num_peri = 0;
2115 val = readl(regs + CR0);
2116 if (val & CR0_BOOT_MAN_NS)
2117 pi->pcfg.mode |= DMAC_MODE_NS;
2119 pi->pcfg.mode &= ~DMAC_MODE_NS;
2121 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
2122 val &= CR0_NUM_EVENTS_MASK;
2124 pi->pcfg.num_events = val;
2126 pi->pcfg.irq_ns = readl(regs + CR3);
2128 pi->pcfg.periph_id = get_id(pi, PERIPH_ID);
2129 pi->pcfg.pcell_id = get_id(pi, PCELL_ID);
2132 static inline void _reset_thread(struct pl330_thread *thrd)
2134 struct pl330_dmac *pl330 = thrd->dmac;
2135 struct pl330_info *pi = pl330->pinfo;
2137 thrd->req[0].mc_cpu = pl330->mcode_cpu
2138 + (thrd->id * pi->mcbufsz);
2139 thrd->req[0].mc_bus = pl330->mcode_bus
2140 + (thrd->id * pi->mcbufsz);
2141 thrd->req[0].r = NULL;
2144 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
2146 thrd->req[1].mc_bus = thrd->req[0].mc_bus
2148 thrd->req[1].r = NULL;
2152 static int dmac_alloc_threads(struct pl330_dmac *pl330)
2154 struct pl330_info *pi = pl330->pinfo;
2155 int chans = pi->pcfg.num_chan;
2156 struct pl330_thread *thrd;
2159 /* Allocate 1 Manager and 'chans' Channel threads */
2160 pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
2162 if (!pl330->channels)
2165 /* Init Channel threads */
2166 for (i = 0; i < chans; i++) {
2167 thrd = &pl330->channels[i];
2170 _reset_thread(thrd);
2174 /* MANAGER is indexed at the end */
2175 thrd = &pl330->channels[chans];
2179 pl330->manager = thrd;
2184 static int dmac_alloc_resources(struct pl330_dmac *pl330)
2186 struct pl330_info *pi = pl330->pinfo;
2187 int chans = pi->pcfg.num_chan;
2191 * Alloc MicroCode buffer for 'chans' Channel threads.
2192 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
2194 pl330->mcode_cpu = dma_alloc_coherent(pi->dev,
2195 chans * pi->mcbufsz,
2196 &pl330->mcode_bus, GFP_KERNEL);
2197 if (!pl330->mcode_cpu) {
2198 dev_err(pi->dev, "%s:%d Can't allocate memory!\n",
2199 __func__, __LINE__);
2203 ret = dmac_alloc_threads(pl330);
2205 dev_err(pi->dev, "%s:%d Can't to create channels for DMAC!\n",
2206 __func__, __LINE__);
2207 dma_free_coherent(pi->dev,
2208 chans * pi->mcbufsz,
2209 pl330->mcode_cpu, pl330->mcode_bus);
2216 static int pl330_add(struct pl330_info *pi)
2218 struct pl330_dmac *pl330;
2222 if (!pi || !pi->dev)
2225 /* If already added */
2230 * If the SoC can perform reset on the DMAC, then do it
2231 * before reading its configuration.
2238 /* Check if we can handle this DMAC */
2239 if ((get_id(pi, PERIPH_ID) & 0xfffff) != PERIPH_ID_VAL
2240 || get_id(pi, PCELL_ID) != PCELL_ID_VAL) {
2241 dev_err(pi->dev, "PERIPH_ID 0x%x, PCELL_ID 0x%x !\n",
2242 get_id(pi, PERIPH_ID), get_id(pi, PCELL_ID));
2246 /* Read the configuration of the DMAC */
2247 read_dmac_config(pi);
2249 if (pi->pcfg.num_events == 0) {
2250 dev_err(pi->dev, "%s:%d Can't work without events!\n",
2251 __func__, __LINE__);
2255 pl330 = kzalloc(sizeof(*pl330), GFP_KERNEL);
2257 dev_err(pi->dev, "%s:%d Can't allocate memory!\n",
2258 __func__, __LINE__);
2262 /* Assign the info structure and private data */
2264 pi->pl330_data = pl330;
2266 spin_lock_init(&pl330->lock);
2268 INIT_LIST_HEAD(&pl330->req_done);
2270 /* Use default MC buffer size if not provided */
2272 pi->mcbufsz = MCODE_BUFF_PER_REQ * 2;
2274 /* Mark all events as free */
2275 for (i = 0; i < pi->pcfg.num_events; i++)
2276 pl330->events[i] = -1;
2278 /* Allocate resources needed by the DMAC */
2279 ret = dmac_alloc_resources(pl330);
2281 dev_err(pi->dev, "Unable to create channels for DMAC\n");
2286 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
2288 pl330->state = INIT;
2293 static int dmac_free_threads(struct pl330_dmac *pl330)
2295 struct pl330_info *pi = pl330->pinfo;
2296 int chans = pi->pcfg.num_chan;
2297 struct pl330_thread *thrd;
2300 /* Release Channel threads */
2301 for (i = 0; i < chans; i++) {
2302 thrd = &pl330->channels[i];
2303 pl330_release_channel((void *)thrd);
2307 kfree(pl330->channels);
2312 static void dmac_free_resources(struct pl330_dmac *pl330)
2314 struct pl330_info *pi = pl330->pinfo;
2315 int chans = pi->pcfg.num_chan;
2317 dmac_free_threads(pl330);
2319 dma_free_coherent(pi->dev, chans * pi->mcbufsz,
2320 pl330->mcode_cpu, pl330->mcode_bus);
2323 static void pl330_del(struct pl330_info *pi)
2325 struct pl330_dmac *pl330;
2327 if (!pi || !pi->pl330_data)
2330 pl330 = pi->pl330_data;
2332 pl330->state = UNINIT;
2334 tasklet_kill(&pl330->tasks);
2336 /* Free DMAC resources */
2337 dmac_free_resources(pl330);
2340 pi->pl330_data = NULL;
2343 /* forward declaration */
2344 static struct amba_driver pl330_driver;
2346 static inline struct dma_pl330_chan *
2347 to_pchan(struct dma_chan *ch)
2352 return container_of(ch, struct dma_pl330_chan, chan);
2355 static inline struct dma_pl330_desc *
2356 to_desc(struct dma_async_tx_descriptor *tx)
2358 return container_of(tx, struct dma_pl330_desc, txd);
2361 static inline void free_desc_list(struct list_head *list)
2363 struct dma_pl330_dmac *pdmac;
2364 struct dma_pl330_desc *desc;
2365 struct dma_pl330_chan *pch = NULL;
2366 unsigned long flags;
2368 /* Finish off the work list */
2369 list_for_each_entry(desc, list, node) {
2370 dma_async_tx_callback callback;
2373 /* All desc in a list belong to same channel */
2375 callback = desc->txd.callback;
2376 param = desc->txd.callback_param;
2384 /* pch will be unset if list was empty */
2390 spin_lock_irqsave(&pdmac->pool_lock, flags);
2391 list_splice_tail_init(list, &pdmac->desc_pool);
2392 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2395 static inline void handle_cyclic_desc_list(struct list_head *list)
2397 struct dma_pl330_desc *desc;
2398 struct dma_pl330_chan *pch = NULL;
2399 unsigned long flags;
2401 list_for_each_entry(desc, list, node) {
2402 dma_async_tx_callback callback;
2404 /* Change status to reload it */
2405 desc->status = PREP;
2407 callback = desc->txd.callback;
2409 callback(desc->txd.callback_param);
2412 /* pch will be unset if list was empty */
2413 if (!pch || !pch->dmac)
2416 spin_lock_irqsave(&pch->lock, flags);
2417 if (pch->chan_status == DMA_PAUSED) {
2418 list_for_each_entry(desc, list, node) {
2419 desc->status = DONE;
2421 list_splice_tail_init(list, &pch->dmac->desc_pool);
2423 list_splice_tail_init(list, &pch->work_list);
2425 spin_unlock_irqrestore(&pch->lock, flags);
2428 static inline void fill_queue(struct dma_pl330_chan *pch)
2430 struct dma_pl330_desc *desc;
2433 list_for_each_entry(desc, &pch->work_list, node) {
2435 /* If already submitted */
2436 if (desc->status == BUSY)
2439 ret = pl330_submit_req(pch->pl330_chid,
2442 desc->status = BUSY;
2443 } else if (ret == -EAGAIN) {
2444 /* QFull or DMAC Dying */
2447 /* Unacceptable request */
2448 desc->status = DONE;
2449 dev_err(pch->dmac->pif.dev, "%s:%d Bad Desc(%d)\n",
2450 __func__, __LINE__, desc->txd.cookie);
2451 tasklet_schedule(&pch->task);
2456 static void pl330_tasklet(unsigned long data)
2458 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
2459 struct dma_pl330_desc *desc, *_dt;
2460 unsigned long flags;
2463 spin_lock_irqsave(&pch->lock, flags);
2465 pch->chan_status = DMA_SUCCESS;
2466 /* Pick up ripe tomatoes */
2467 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2468 if (desc->status == DONE) {
2470 dma_cookie_complete(&desc->txd);
2471 list_move_tail(&desc->node, &list);
2474 /* Try to submit a req imm. next to the last completed cookie */
2477 /* Make sure the PL330 Channel thread is active */
2478 pl330_chan_ctrl(pch->pl330_chid, PL330_OP_START);
2480 spin_unlock_irqrestore(&pch->lock, flags);
2483 handle_cyclic_desc_list(&list);
2485 free_desc_list(&list);
2488 static void dma_pl330_rqcb(void *token, enum pl330_op_err err)
2490 struct dma_pl330_desc *desc = token;
2491 struct dma_pl330_chan *pch = desc->pchan;
2492 unsigned long flags;
2494 /* If desc aborted */
2498 spin_lock_irqsave(&pch->lock, flags);
2500 desc->status = DONE;
2502 spin_unlock_irqrestore(&pch->lock, flags);
2504 tasklet_schedule(&pch->task);
2507 static bool pl330_dt_filter(struct dma_chan *chan, void *param)
2509 struct dma_pl330_filter_args *fargs = param;
2511 if (chan->device != &fargs->pdmac->ddma)
2514 return (chan->chan_id == fargs->chan_id);
2517 bool pl330_filter(struct dma_chan *chan, void *param)
2521 if (chan->device->dev->driver != &pl330_driver.drv)
2524 peri_id = chan->private;
2525 return *peri_id == (unsigned long)param;
2527 EXPORT_SYMBOL(pl330_filter);
2529 static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2530 struct of_dma *ofdma)
2532 int count = dma_spec->args_count;
2533 struct dma_pl330_dmac *pdmac = ofdma->of_dma_data;
2534 struct dma_pl330_filter_args fargs;
2543 fargs.pdmac = pdmac;
2544 fargs.chan_id = dma_spec->args[0];
2547 dma_cap_set(DMA_SLAVE, cap);
2548 dma_cap_set(DMA_CYCLIC, cap);
2550 return dma_request_channel(cap, pl330_dt_filter, &fargs);
2553 static int pl330_alloc_chan_resources(struct dma_chan *chan)
2555 struct dma_pl330_chan *pch = to_pchan(chan);
2556 struct dma_pl330_dmac *pdmac = pch->dmac;
2557 unsigned long flags;
2559 spin_lock_irqsave(&pch->lock, flags);
2561 dma_cookie_init(chan);
2562 pch->cyclic = false;
2564 pch->pl330_chid = pl330_request_channel(&pdmac->pif);
2565 if (!pch->pl330_chid) {
2566 spin_unlock_irqrestore(&pch->lock, flags);
2570 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2572 spin_unlock_irqrestore(&pch->lock, flags);
2577 static int pl330_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg)
2579 struct dma_pl330_chan *pch = to_pchan(chan);
2580 struct dma_pl330_desc *desc, *_dt;
2581 unsigned long flags;
2582 struct dma_pl330_dmac *pdmac = pch->dmac;
2583 struct dma_slave_config *slave_config;
2587 case DMA_TERMINATE_ALL:
2588 spin_lock_irqsave(&pch->lock, flags);
2590 /* FLUSH the PL330 Channel thread */
2591 pl330_chan_ctrl(pch->pl330_chid, PL330_OP_FLUSH);
2593 /* Mark all desc done */
2594 list_for_each_entry_safe(desc, _dt, &pch->work_list , node) {
2595 desc->status = DONE;
2596 list_move_tail(&desc->node, &list);
2599 list_splice_tail_init(&list, &pdmac->desc_pool);
2600 pch->chan_status = DMA_PAUSED;
2601 spin_unlock_irqrestore(&pch->lock, flags);
2603 case DMA_SLAVE_CONFIG:
2604 slave_config = (struct dma_slave_config *)arg;
2606 if (slave_config->direction == DMA_MEM_TO_DEV) {
2607 if (slave_config->dst_addr)
2608 pch->fifo_addr = slave_config->dst_addr;
2609 if (slave_config->dst_addr_width)
2610 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2611 if (slave_config->dst_maxburst)
2612 pch->burst_len = slave_config->dst_maxburst;
2613 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
2614 if (slave_config->src_addr)
2615 pch->fifo_addr = slave_config->src_addr;
2616 if (slave_config->src_addr_width)
2617 pch->burst_sz = __ffs(slave_config->src_addr_width);
2618 if (slave_config->src_maxburst)
2619 pch->burst_len = slave_config->src_maxburst;
2623 dev_err(pch->dmac->pif.dev, "Not supported command.\n");
2630 static void pl330_free_chan_resources(struct dma_chan *chan)
2632 struct dma_pl330_chan *pch = to_pchan(chan);
2633 unsigned long flags;
2635 tasklet_kill(&pch->task);
2637 spin_lock_irqsave(&pch->lock, flags);
2639 pl330_release_channel(pch->pl330_chid);
2640 pch->pl330_chid = NULL;
2643 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2645 spin_unlock_irqrestore(&pch->lock, flags);
2648 static enum dma_status
2649 pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2650 struct dma_tx_state *txstate)
2652 struct dma_pl330_chan *pch = to_pchan(chan);
2653 void __iomem *regs = pch->dmac->pif.base;
2654 struct pl330_thread *pt = pch->pl330_chid;
2656 st = dma_cookie_status(chan, cookie, txstate);
2657 txstate->residue = readl(regs + DA(pt->id));
2661 static void pl330_issue_pending(struct dma_chan *chan)
2663 pl330_tasklet((unsigned long) to_pchan(chan));
2667 * We returned the last one of the circular list of descriptor(s)
2668 * from prep_xxx, so the argument to submit corresponds to the last
2669 * descriptor of the list.
2671 static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2673 struct dma_pl330_desc *desc, *last = to_desc(tx);
2674 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2675 dma_cookie_t cookie;
2676 unsigned long flags;
2678 spin_lock_irqsave(&pch->lock, flags);
2680 /* Assign cookies to all nodes */
2681 while (!list_empty(&last->node)) {
2682 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2684 desc->txd.callback = last->txd.callback;
2685 desc->txd.callback_param = last->txd.callback_param;
2688 dma_cookie_assign(&desc->txd);
2690 list_move_tail(&desc->node, &pch->work_list);
2693 cookie = dma_cookie_assign(&last->txd);
2694 list_add_tail(&last->node, &pch->work_list);
2695 spin_unlock_irqrestore(&pch->lock, flags);
2700 static inline void _init_desc(struct dma_pl330_desc *desc)
2703 desc->req.x = &desc->px;
2704 desc->req.token = desc;
2705 desc->rqcfg.swap = SWAP_NO;
2706 desc->rqcfg.privileged = 0;
2707 desc->rqcfg.insnaccess = 0;
2708 desc->rqcfg.scctl = SCCTRL0;
2709 desc->rqcfg.dcctl = DCCTRL0;
2710 desc->req.cfg = &desc->rqcfg;
2711 desc->req.xfer_cb = dma_pl330_rqcb;
2712 desc->txd.tx_submit = pl330_tx_submit;
2714 INIT_LIST_HEAD(&desc->node);
2717 /* Returns the number of descriptors added to the DMAC pool */
2718 static int add_desc(struct dma_pl330_dmac *pdmac, gfp_t flg, int count)
2720 struct dma_pl330_desc *desc;
2721 unsigned long flags;
2727 desc = kzalloc(count * sizeof(*desc), flg);
2731 spin_lock_irqsave(&pdmac->pool_lock, flags);
2733 for (i = 0; i < count; i++) {
2734 _init_desc(&desc[i]);
2735 list_add_tail(&desc[i].node, &pdmac->desc_pool);
2738 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2743 static struct dma_pl330_desc *
2744 pluck_desc(struct dma_pl330_dmac *pdmac)
2746 struct dma_pl330_desc *desc = NULL;
2747 unsigned long flags;
2752 spin_lock_irqsave(&pdmac->pool_lock, flags);
2754 if (!list_empty(&pdmac->desc_pool)) {
2755 desc = list_entry(pdmac->desc_pool.next,
2756 struct dma_pl330_desc, node);
2758 list_del_init(&desc->node);
2760 desc->status = PREP;
2761 desc->txd.callback = NULL;
2764 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2769 static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2771 struct dma_pl330_dmac *pdmac = pch->dmac;
2772 u8 *peri_id = pch->chan.private;
2773 struct dma_pl330_desc *desc;
2776 /* Pluck one desc from the pool of DMAC */
2777 desc = pluck_desc(pdmac);
2779 /* If the DMAC pool is empty, alloc new */
2781 for(i = 0; i < 3; i++) {
2782 if (!add_desc(pdmac, GFP_ATOMIC, 1))
2786 desc = pluck_desc(pdmac);
2788 dev_err(pch->dmac->pif.dev,
2789 "%s:%d i=%d ALERT!\n", __func__, __LINE__,i);
2799 /* Initialize the descriptor */
2801 desc->txd.cookie = 0;
2802 async_tx_ack(&desc->txd);
2804 desc->req.infiniteloop = 0;
2805 desc->req.peri = peri_id ? pch->chan.chan_id : 0;
2806 desc->rqcfg.pcfg = &pch->dmac->pif.pcfg;
2808 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2813 static inline void fill_px(struct pl330_xfer *px,
2814 dma_addr_t dst, dma_addr_t src, size_t len)
2822 static struct dma_pl330_desc *
2823 __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2824 dma_addr_t src, size_t len)
2826 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2829 dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n",
2830 __func__, __LINE__);
2835 * Ideally we should lookout for reqs bigger than
2836 * those that can be programmed with 256 bytes of
2837 * MC buffer, but considering a req size is seldom
2838 * going to be word-unaligned and more than 200MB,
2840 * Also, should the limit is reached we'd rather
2841 * have the platform increase MC buffer size than
2842 * complicating this API driver.
2844 fill_px(&desc->px, dst, src, len);
2849 /* Call after fixing burst size */
2850 static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2852 struct dma_pl330_chan *pch = desc->pchan;
2853 struct pl330_info *pi = &pch->dmac->pif;
2856 burst_len = pi->pcfg.data_bus_width / 8;
2857 burst_len *= pi->pcfg.data_buf_dep;
2858 burst_len >>= desc->rqcfg.brst_size;
2860 /* src/dst_burst_len can't be more than 16 */
2864 while (burst_len > 1) {
2865 if (!(len % (burst_len << desc->rqcfg.brst_size)))
2873 static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2874 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2875 size_t period_len, enum dma_transfer_direction direction,
2876 unsigned long flags, void *context)
2878 struct dma_pl330_desc *desc = NULL, *first = NULL;
2879 struct dma_pl330_chan *pch = to_pchan(chan);
2880 struct dma_pl330_dmac *pdmac = pch->dmac;
2884 unsigned int *infinite = context;
2886 if (len % period_len != 0)
2889 if (!is_slave_direction(direction)) {
2890 dev_err(pch->dmac->pif.dev, "%s:%d Invalid dma direction\n",
2891 __func__, __LINE__);
2895 for (i = 0; i < len / period_len; i++) {
2896 desc = pl330_get_desc(pch);
2898 dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n",
2899 __func__, __LINE__);
2904 spin_lock_irqsave(&pdmac->pool_lock, flags);
2906 while (!list_empty(&first->node)) {
2907 desc = list_entry(first->node.next,
2908 struct dma_pl330_desc, node);
2909 list_move_tail(&desc->node, &pdmac->desc_pool);
2912 list_move_tail(&first->node, &pdmac->desc_pool);
2914 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2919 switch (direction) {
2920 case DMA_MEM_TO_DEV:
2921 desc->rqcfg.src_inc = 1;
2922 desc->rqcfg.dst_inc = 0;
2923 desc->req.rqtype = MEMTODEV;
2925 dst = pch->fifo_addr;
2927 case DMA_DEV_TO_MEM:
2928 desc->rqcfg.src_inc = 0;
2929 desc->rqcfg.dst_inc = 1;
2930 desc->req.rqtype = DEVTOMEM;
2931 src = pch->fifo_addr;
2938 desc->rqcfg.brst_size = pch->burst_sz;
2939 #ifdef CONFIG_ARCH_ROCKCHIP
2940 desc->rqcfg.brst_len = pch->burst_len;
2942 desc->rqcfg.brst_len = 1;
2944 desc->req.infiniteloop = *infinite;
2945 fill_px(&desc->px, dst, src, period_len);
2950 list_add_tail(&desc->node, &first->node);
2952 dma_addr += period_len;
2959 desc->txd.flags = flags;
2964 static struct dma_async_tx_descriptor *
2965 pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2966 dma_addr_t src, size_t len, unsigned long flags)
2968 struct dma_pl330_desc *desc;
2969 struct dma_pl330_chan *pch = to_pchan(chan);
2970 struct pl330_info *pi;
2973 if (unlikely(!pch || !len))
2976 pi = &pch->dmac->pif;
2978 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2982 desc->rqcfg.src_inc = 1;
2983 desc->rqcfg.dst_inc = 1;
2984 desc->req.rqtype = MEMTOMEM;
2986 /* Select max possible burst size */
2987 burst = pi->pcfg.data_bus_width / 8;
2995 desc->rqcfg.brst_size = 0;
2996 while (burst != (1 << desc->rqcfg.brst_size))
2997 desc->rqcfg.brst_size++;
2999 desc->rqcfg.brst_len = get_burst_len(desc, len);
3001 desc->txd.flags = flags;
3006 static struct dma_async_tx_descriptor *
3007 pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
3008 unsigned int sg_len, enum dma_transfer_direction direction,
3009 unsigned long flg, void *context)
3011 struct dma_pl330_desc *first, *desc = NULL;
3012 struct dma_pl330_chan *pch = to_pchan(chan);
3013 struct scatterlist *sg;
3014 unsigned long flags;
3018 if (unlikely(!pch || !sgl || !sg_len))
3021 addr = pch->fifo_addr;
3025 for_each_sg(sgl, sg, sg_len, i) {
3027 desc = pl330_get_desc(pch);
3029 struct dma_pl330_dmac *pdmac = pch->dmac;
3031 dev_err(pch->dmac->pif.dev,
3032 "%s:%d Unable to fetch desc\n",
3033 __func__, __LINE__);
3037 spin_lock_irqsave(&pdmac->pool_lock, flags);
3039 while (!list_empty(&first->node)) {
3040 desc = list_entry(first->node.next,
3041 struct dma_pl330_desc, node);
3042 list_move_tail(&desc->node, &pdmac->desc_pool);
3045 list_move_tail(&first->node, &pdmac->desc_pool);
3047 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
3055 list_add_tail(&desc->node, &first->node);
3057 if (direction == DMA_MEM_TO_DEV) {
3058 desc->rqcfg.src_inc = 1;
3059 desc->rqcfg.dst_inc = 0;
3060 desc->req.rqtype = MEMTODEV;
3062 addr, sg_dma_address(sg), sg_dma_len(sg));
3064 desc->rqcfg.src_inc = 0;
3065 desc->rqcfg.dst_inc = 1;
3066 desc->req.rqtype = DEVTOMEM;
3068 sg_dma_address(sg), addr, sg_dma_len(sg));
3071 desc->rqcfg.brst_size = pch->burst_sz;
3072 #ifdef CONFIG_ARCH_ROCKCHIP
3073 desc->rqcfg.brst_len = pch->burst_len;
3075 desc->rqcfg.brst_len = 1;
3079 /* Return the last desc in the chain */
3080 desc->txd.flags = flg;
3084 static irqreturn_t pl330_irq_handler(int irq, void *data)
3086 if (pl330_update(data))
3092 int pl330_dma_getposition(struct dma_chan *chan,
3093 dma_addr_t *src, dma_addr_t *dst)
3095 struct dma_pl330_chan *pch = to_pchan(chan);
3096 struct pl330_info *pi;
3098 struct pl330_thread *thrd;
3103 thrd = pch->pl330_chid;
3104 pi = &pch->dmac->pif;
3107 *src = readl(regs + SA(thrd->id));
3108 *dst = readl(regs + DA(thrd->id));
3112 EXPORT_SYMBOL(pl330_dma_getposition);
3115 pl330_probe(struct amba_device *adev, const struct amba_id *id)
3117 struct dma_pl330_platdata *pdat;
3118 struct dma_pl330_dmac *pdmac;
3119 struct dma_pl330_chan *pch, *_p;
3120 struct pl330_info *pi;
3121 struct dma_device *pd;
3122 struct resource *res;
3126 pdat = adev->dev.platform_data;
3128 /* Allocate a new DMAC and its Channels */
3129 pdmac = devm_kzalloc(&adev->dev, sizeof(*pdmac), GFP_KERNEL);
3131 dev_err(&adev->dev, "unable to allocate mem\n");
3136 pi->dev = &adev->dev;
3137 pi->pl330_data = NULL;
3138 pi->mcbufsz = pdat ? pdat->mcbuf_sz : 0;
3141 pi->base = devm_ioremap_resource(&adev->dev, res);
3142 if (IS_ERR(pi->base))
3143 return PTR_ERR(pi->base);
3145 amba_set_drvdata(adev, pdmac);
3148 ret = request_irq(irq, pl330_irq_handler, 0,
3149 dev_name(&adev->dev), pi);
3153 ret = pl330_add(pi);
3157 INIT_LIST_HEAD(&pdmac->desc_pool);
3158 spin_lock_init(&pdmac->pool_lock);
3160 /* Create a descriptor pool of default size */
3161 if (!add_desc(pdmac, GFP_KERNEL, NR_DEFAULT_DESC))
3162 dev_warn(&adev->dev, "unable to allocate desc\n");
3165 INIT_LIST_HEAD(&pd->channels);
3167 /* Initialize channel parameters */
3169 num_chan = max_t(int, pdat->nr_valid_peri, pi->pcfg.num_chan);
3171 num_chan = max_t(int, pi->pcfg.num_peri, pi->pcfg.num_chan);
3173 pdmac->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
3174 if (!pdmac->peripherals) {
3176 dev_err(&adev->dev, "unable to allocate pdmac->peripherals\n");
3180 for (i = 0; i < num_chan; i++) {
3181 pch = &pdmac->peripherals[i];
3182 if (!adev->dev.of_node)
3183 pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
3185 pch->chan.private = adev->dev.of_node;
3187 INIT_LIST_HEAD(&pch->work_list);
3188 spin_lock_init(&pch->lock);
3189 pch->pl330_chid = NULL;
3190 pch->chan.device = pd;
3193 /* Add the channel to the DMAC list */
3194 list_add_tail(&pch->chan.device_node, &pd->channels);
3197 pd->dev = &adev->dev;
3199 pd->cap_mask = pdat->cap_mask;
3201 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
3202 if (pi->pcfg.num_peri) {
3203 dma_cap_set(DMA_SLAVE, pd->cap_mask);
3204 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
3205 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
3209 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
3210 pd->device_free_chan_resources = pl330_free_chan_resources;
3211 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
3212 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
3213 pd->device_tx_status = pl330_tx_status;
3214 pd->device_prep_slave_sg = pl330_prep_slave_sg;
3215 pd->device_control = pl330_control;
3216 pd->device_issue_pending = pl330_issue_pending;
3217 #ifdef CONFIG_ARCH_ROCKCHIP
3218 pd->dma_getposition = pl330_dma_getposition;
3221 ret = dma_async_device_register(pd);
3223 dev_err(&adev->dev, "unable to register DMAC\n");
3227 if (adev->dev.of_node) {
3228 ret = of_dma_controller_register(adev->dev.of_node,
3229 of_dma_pl330_xlate, pdmac);
3232 "unable to register DMA to the generic DT DMA helpers\n");
3236 dev_info(&adev->dev,
3237 "Loaded driver for PL330 DMAC-%d\n", adev->periphid);
3238 dev_info(&adev->dev,
3239 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
3240 pi->pcfg.data_buf_dep,
3241 pi->pcfg.data_bus_width / 8, pi->pcfg.num_chan,
3242 pi->pcfg.num_peri, pi->pcfg.num_events);
3246 amba_set_drvdata(adev, NULL);
3249 list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels,
3252 /* Remove the channel */
3253 list_del(&pch->chan.device_node);
3255 /* Flush the channel */
3256 pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0);
3257 pl330_free_chan_resources(&pch->chan);
3267 static int pl330_remove(struct amba_device *adev)
3269 struct dma_pl330_dmac *pdmac = amba_get_drvdata(adev);
3270 struct dma_pl330_chan *pch, *_p;
3271 struct pl330_info *pi;
3277 if (adev->dev.of_node)
3278 of_dma_controller_free(adev->dev.of_node);
3280 dma_async_device_unregister(&pdmac->ddma);
3281 amba_set_drvdata(adev, NULL);
3284 list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels,
3287 /* Remove the channel */
3288 list_del(&pch->chan.device_node);
3290 /* Flush the channel */
3291 pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0);
3292 pl330_free_chan_resources(&pch->chan);
3305 static struct amba_id pl330_ids[] = {
3313 MODULE_DEVICE_TABLE(amba, pl330_ids);
3315 static struct amba_driver pl330_driver = {
3317 .owner = THIS_MODULE,
3318 .name = "dma-pl330",
3320 .id_table = pl330_ids,
3321 .probe = pl330_probe,
3322 .remove = pl330_remove,
3325 module_amba_driver(pl330_driver);
3327 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
3328 MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3329 MODULE_LICENSE("GPL");